Solar cell, cell assembly and photovoltaic system

Abstract

The utility model is suitable for the field of photovoltaic technology, and provides a solar cell, a cell assembly and a photovoltaic system, the solar cell comprises a silicon substrate, the silicon substrate is provided with a back surface and a front surface which are oppositely arranged; the diffusion layer is positioned in a first region on the back surface of the silicon substrate; the doping layer is positioned in a second region on the back surface of the silicon substrate, and the doping layer and the diffusion layer have opposite polarities; two opposite surfaces of the tunneling layer are respectively in contact with the diffusion layer and the doping layer; the surface, facing the doping layer, of the silicon substrate is a polished surface, the surface, back to the silicon substrate, of the diffusion layer is a suede surface, and the total area of the suede surface is larger than that of the polished surface. According to the solar cell, the hot spot risk can be reduced while the conversion efficiency of the solar cell is not greatly lost, meanwhile, the total area of the textured surface and the total area of the polished surface are optimized, the light absorption efficiency is improved, the surface recombination probability of current carriers is reduced, and the overall performance of the solar cell is improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of photovoltaics, and particularly relates to a solar cell, a battery module and a photovoltaic system. Background Art

[0002] Photovoltaic modules composed of multiple cells are usually installed in open and sunny areas. Inevitably, in long-term use, they will be covered by obstacles such as birds, dust, and fallen leaves. These obstacles form shadows on the photovoltaic modules, and inappropriate row spacings in large photovoltaic module arrays can also form shadows on each other. Due to the existence of local shadows, the current and voltage of some individual solar cells in the photovoltaic module change. Conventional solar cells have diode characteristics. The shaded cell is in reverse bias, increasing the product of the local current and voltage of the photovoltaic module, and its power consumption is extremely high, resulting in a phenomenon of local temperature rise on these photovoltaic modules. Some defects in individual cells of the photovoltaic module itself may also cause local heating during operation, and this phenomenon is called the "hot spot effect". Therefore, existing photovoltaic modules with such cells have a relatively high hot spot risk in the actual working process. After being encapsulated into a photovoltaic module, the hot spot effect may reduce the module power and pose a safety problem of local temperature rise at the same time. In related technologies, the hot spot risk of photovoltaic modules is often avoided by setting bypass diodes, but this method will increase the surface recombination probability of carriers. Therefore, it is urgent to reduce the "hot spot effect" and the surface recombination probability of carriers through other technical means. Summary of the Utility Model

[0003] The utility model provides a solar cell, a battery module and a photovoltaic system, aiming to solve the problem of how to reduce the "hot spot effect" while reducing the surface recombination probability of carriers.

[0004] The utility model is realized as follows. A solar cell includes: a silicon substrate having a back surface and a front surface disposed opposite to each other;

[0005] A diffusion layer located in a first region on the back surface of the silicon substrate;

[0006] A doped layer located in a second region on the back surface of the silicon substrate, and the doped layer and the diffusion layer have opposite polarities;

[0007] A tunneling layer, with two opposite surfaces of the tunneling layer contacting the diffusion layer and the doped layer respectively;

[0008] The surface of the silicon substrate facing the doped layer is a polished surface, and the surface of the diffusion layer facing away from the silicon substrate is a textured surface, and the total area of the textured surface is larger than the total area of the polished surface.

[0009] Optionally, the total area of the textured surface is 1.1 to 3 times the total area of the polished surface.

[0010] Optionally, the horizontal direction is the first direction, and the first region and the second region are spaced apart along the first direction; two opposite sides of the tunneling layer along the first direction are respectively in contact with the diffusion layer and the doping layer.

[0011] Optionally, the second region partially overlaps with the first region, the doping layer includes a first part, a second part, and a third part connecting the first part and the second part, the first part is placed in the overlapping region of the second region and the first region, and is disposed above the diffusion layer;

[0012] An insulating layer is disposed between the diffusion layer and the first part, and the tunneling layer is disposed on the bottom surface of the second part and the inner side surface of the third part.

[0013] Optionally, an interface passivation layer is disposed between the first part and the insulating layer within the first region.

[0014] Optionally, the tunneling layer is connected to the interface passivation layer.

[0015] Optionally, the horizontal direction is the first direction, and the first region and the second region are spaced apart along the first direction;

[0016] Along the first direction, a groove is disposed between some adjacent diffusion layers and doping layers, the groove isolates the doping layer and the diffusion layer, and the distance from the bottom of the groove to the front surface of the silicon substrate is less than the distance from the second part to the front surface of the silicon substrate.

[0017] Optionally, the total area of the grooves accounts for more than or equal to 20% of the total area of the back surface of the silicon substrate.

[0018] Optionally, the bottom and the side walls of the groove are suede.

[0019] Optionally, it further includes a first electrode connected to the diffusion layer and a second electrode connected to the doping layer, the first electrode is not electrically connected to the doping layer; the connection depth of the first electrode extending into the diffusion layer is less than the connection depth of the second electrode extending into the doping layer, and the contact area of the first electrode extending into the diffusion layer is greater than the contact area of the second electrode extending into the doping layer.

[0020] Optionally, the glass frit content in the first electrode is less than the glass frit content in the second electrode.

[0021] Optionally, the distance between the diffusion layer and the front surface of the silicon substrate is greater than the distance between the second part and the front surface of the silicon substrate. The diffusion layer extends towards the side where the second part is disposed adjacent thereto. The insulating layer follows the extension of the diffusion layer. The tunneling layer and the doping layer form a convex position along the extension direction of the diffusion layer and the insulating layer.

[0022] Optionally, the difference between the distance between the diffusion layer and the front surface of the silicon substrate and the distance between the second part and the front surface of the silicon substrate is 1 μm to 6 μm.

[0023] Optionally, the diffusion layer is a P-type doped single crystal silicon; the doping layer is an N-type doped polycrystalline silicon.

[0024] The present utility model further provides a battery assembly, including the above-mentioned solar cell.

[0025] The present utility model further provides a photovoltaic system, including the above-mentioned battery assembly.

[0026] The beneficial effects achieved by the present utility model are as follows: By reasonably designing the area of the conductive contact structure and its position on the solar cell, the relationship between the photoelectric conversion efficiency of the solar cell and the control of the hot spot risk can be balanced. The hot spot risk can be reduced while ensuring that the conversion efficiency of the solar cell has no significant loss. At the same time, by optimizing the total area of the textured surface and the total area of the polished surface, the light absorption efficiency is improved, the surface recombination probability of carriers is reduced, which helps to improve the overall performance of the solar cell. Description of the Drawings

[0027] Figure 1 is a partial structural schematic diagram of the first solar cell provided by the present utility model;

[0028] Figure 2 is a partial structural schematic diagram of the second solar cell provided by the present utility model;

[0029] Figure 3 is a partial structural schematic diagram of the third solar cell provided by the present utility model;

[0030] Figure 4 is a partial structural schematic diagram of the fourth solar cell provided by the present utility model;

[0031] Figure 5 is a first position relationship schematic diagram of the diffusion layer, the doping layer and the tunneling layer in the solar cell provided by the present utility model;

[0032] Figure 6 is a second position relationship schematic diagram of the diffusion layer, the doping layer and the tunneling layer in the solar cell provided by the present utility model.

[0033] Description of the Reference Numerals:

[0034] 100, solar cell; 110, first region; 111, diffusion layer; 120, second region; 121, doping layer; 1211, first part; 1212, third part; 1213, second part; 130, insulating layer; 140, tunneling layer; 150, silicon substrate; 160, first electrode; 170, second electrode; 180, interface passivation layer; 190, trench;

[0035] 101, matte surface; 102, polished surface. Detailed implementation manners

[0036] In order to make the objectives, technical solutions and advantages of the present utility model clearer and more understandable, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present utility model and should not be construed as a limitation to the present utility model. In addition, it should be understood that the specific embodiments described herein are only used to explain the present utility model and are not used to limit the present utility model.

[0037] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by terms such as "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present utility model.

[0038] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present utility model, "a plurality" means two or more unless otherwise specifically defined.

[0039] In the description of the present utility model, it should be noted that unless otherwise clearly defined and limited, the terms "installation", "connection", and "coupling" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a connection that allows mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, and can be the internal communication between two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0040] In the present utility model, unless otherwise clearly defined and limited, the first feature being "above" or "below" the second feature may include direct contact between the first and second features, or may include the first and second features not being in direct contact but in contact through other features therebetween. Moreover, the first feature being "above", "over", and "on top of" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature has a higher horizontal height than the second feature. The first feature being "below", "beneath", and "underneath" the second feature includes the first feature being directly below and obliquely below the second feature, or merely indicating that the first feature has a lower horizontal height than the second feature.

[0041] The following disclosure provides many different embodiments or examples for implementing different structures of the present utility model. To simplify the disclosure of the present utility model, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present utility model. In addition, the present utility model may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present utility model provides examples of various specific processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0042] In the present application of the present utility model, by reasonably designing the area of the conductive contact structure and its position on the solar cell, the relationship between the photoelectric conversion efficiency of the solar cell and the control of the hot spot risk can be balanced. While ensuring that the conversion efficiency of the solar cell is not significantly lost, the hot spot risk can be reduced. At the same time, by optimizing the total area of the textured surface and the total area of the polished surface, the light absorption efficiency can be improved, the surface recombination probability of carriers can be reduced, which helps to improve the overall performance of the solar cell.

[0043] Example 1

[0044] As Figure 1 shown, this embodiment provides a solar cell 100, including: a silicon substrate 150 having a back surface and a front surface disposed opposite to each other;

[0045] Diffusion layer 111, located in the first region 110 on the back surface of the silicon substrate 150;

[0046] Doped layer 121, located in the second region 120 on the back surface of the silicon substrate 150, the doped layer 121 and the diffusion layer 111 have opposite polarities;

[0047] Tunneling layer 140, the two opposite sides of the tunneling layer 140 are respectively in contact with the diffusion layer 111 and the doped layer 121;

[0048] The surface of the silicon substrate 150 facing the doped layer 121 is the polished surface 102, and the side of the diffusion layer 111 facing away from the silicon substrate 150 is the matte surface 101. The total area of the matte surface 101 is larger than the total area of the polished surface 102.

[0049] For the solar cell 100 provided in this application, the "front" and "back" in the front and back surfaces of the silicon substrate 150 are relative. That is, the "front" refers to the side facing the sunlight along the vertical direction, and the "back" refers to the side facing away from the sunlight along the vertical direction.

[0050] The diffusion layer 111 is located in the first region 110, and the doped layer 121 is located in the second region 120. Both the first region 110 and the second region 120 are disposed on the back surface of the silicon substrate 150. Specifically, multiple first regions 110 and multiple second regions 120 can be arranged at intervals. The tunneling layer 140 is disposed between the diffusion layer 111 and the doped layer 121. The two opposite sides of the tunneling layer 140 are respectively in contact with the diffusion layer 111 and the doped layer 121. That is, there must be a region where the diffusion layer 111, the tunneling layer 140, and the doped layer 121 are adjacent in sequence to achieve the conductive contact between the diffusion layer 111 and the doped layer 121. Specifically, as Figure 5 shown, the two opposite sides along the horizontal direction, or as Figure 6 shown, the two opposite sides along the vertical direction.

[0051] It can be understood that the diffusion layer 111 and the doped layer 121 have opposite polarities. Then, when the diffusion layer 111 is of P type, the doped layer 121 is of N type; when the diffusion layer 111 is of N type, the doped layer 121 is of P type.

[0052] The diffusion layer 111, the silicon substrate 150, and the doped layer 121 form a PN junction structure to realize the process of separation and collection of photo-generated carriers in the solar cell 100. The tunneling layer 140 allows electrons and holes to quickly pass through the interface through the quantum tunneling effect, and the diffusion layer 111 and the doped layer 121 conduct electricity through the tunneling layer 140.

[0053] When the solar cell 100 generates electricity normally, the diffusion layer 111 and the doped layer 121 perform photoelectric conversion normally to generate electricity. At the module end, when the solar cell 100 is shaded, other solar cells 100 connected in series with it provide reverse current for the shaded solar cell 100. An appropriate composite leakage current can be generated in the area where the diffusion layer 111, the tunneling layer 140, and the doped layer 121 of the solar cell 100 are adjacent in sequence, reducing the voltage across the shaded solar cell 100 (the voltage is less than the sum of the voltages of other solar cells 100 connected in series with this solar cell 100 and not shaded). The heating power of the solar cell 100 will decrease, thereby reducing the high thermal risk of the hot spot effect.

[0054] Secondly, by deliberately introducing a conductive contact structure in the solar cell 100, it has a protective effect on the hot spot effect caused by the defects of the silicon substrate 150 itself (that is, it can reduce the heat generated by the defects), and can reduce or even cancel the control requirements for the defects of the silicon substrate 150, improving the manufacturing capacity of the solar cell 100 while reducing the hot spot risk caused by the defects of the silicon substrate 150.

[0055] The surface of the silicon substrate 150 facing the doped layer 121 is the polished surface 102. The area covered by the projection of the doped layer 121 on the silicon substrate 150 has a surface that is the polished surface 102. The polished surface 102 refers to the surface that becomes very smooth with a low surface roughness after fine processing. A smoother surface is more conducive to subsequent processing and doping control, thereby helping to improve the production yield and the overall reliability of the solar cell 100. The side of the diffusion layer 111 facing the insulating layer 130 is the textured surface 101. The textured surface 101 generally refers to a micro-conical or pyramid-shaped structure formed on the silicon wafer surface through chemical or physical etching. This surface structure can increase the surface area of the silicon wafer and, when light irradiates the silicon wafer surface, increase the light scattering and absorption, thereby reducing the reflection loss. The total area of the textured surface 101 is larger than the total area of the polished surface 102, improving the light absorption efficiency and reducing the light reflection loss, enabling more light to enter the battery interior and generate current.

[0056] The surface recombination effect on the silicon substrate 150 refers to the phenomenon that photo-generated carriers recombine and disappear on the surface before reaching the PN junction. Due to the textured surface 101 structure increasing the surface roughness, it can also increase the local electric field effect in the carrier recombination region on the surface, thereby reducing the surface recombination probability of carriers, enabling more carriers to successfully reach the PN junction and participate in the current generation.

[0057] In the present application, by reasonably designing the area of the conductive contact structure and its position on the solar cell 100, the relationship between the photoelectric conversion efficiency of the solar cell 100 and the risk of controlling hot spots can be balanced. The risk of hot spots can be reduced while ensuring that the conversion efficiency of the solar cell 100 does not suffer a large loss. At the same time, by optimizing the total area of the textured surface 101 and the total area of the polished surface 102, the light absorption efficiency can be improved, the surface recombination probability of carriers can be reduced, which helps to improve the overall performance of the solar cell 100.

[0058] It can be understood that the attached drawings of the present utility model are only example drawings, and the layers in the drawings are not necessarily drawn in proportion according to the actual situation. The overlapping parts between the layers may or may not be aligned in the vertical direction, and this is not limited herein.

[0059] Example 2

[0060] On the basis of Embodiment 1, the total area of the textured surface 101 is 1.1 to 3 times the total area of the polished surface 102.

[0061] The total area of the textured surface 101 can be 1.1 to 3 times the total area of the polished surface 102. The specific multiples can be 1.1 times, 1.2 times, 1.3 times, 1.4 times, 1.5 times, 1.6 times, 1.7 times, 1.8 times, 1.9 times, 2 times, 2.1 times, 2.2 times, 2.3 times, 2.4 times, 2.5 times, 2.6 times, 2.7 times, 2.8 times, 2.9 times, 3 times, etc. The above are not all listed.

[0062] By controlling this multiple, the solar cell 100 is optimized in terms of light trapping, carrier collection, and overall cell efficiency. This design not only improves the photoelectric conversion efficiency of the battery but also provides higher reliability and stability for the performance of the solar cell 100 in various application scenarios.

[0063] Example 3

[0064] As Figure 1 shown, on the basis of Embodiment 1, the horizontal direction is the first direction, and the first region 110 and the second region 120 are arranged at intervals along the first direction; the two opposite sides of the tunneling layer 140 along the first direction are respectively in contact with the diffusion layer 111 and the doping layer 121.

[0065] The silicon substrate 150 is placed on the placement plane, and the direction parallel to the placement plane is the horizontal direction of the present application, which is the first direction. Along the first direction, the first region 110 and the second region 120 are distributed at intervals, that is, the diffusion layer 111 and the doping layer 121 are distributed at intervals. And there is a region where the diffusion layer 111, the tunneling layer 140, and the doping layer 121 are adjacent in sequence along the first direction.

[0066] Example 4

[0067] As shown Figure 2 in FIG., on the basis of the first embodiment, the second region 120 partially overlaps with the first region 110. The doping layer 121 includes a first part 1211, a second part 1213, and a third part 1212 connecting the first part 1211 and the second part. The first part 1211 is placed in the overlapping region of the second region 120 and the first region 110, and is disposed above the diffusion layer 111;

[0068] An insulating layer 130 is disposed between the diffusion layer 111 and the first part 1211, and a tunneling layer 140 is disposed on the bottom surface of the second part 1213 and the inner side surface of the third part 1212.

[0069] In this embodiment, N and P need to be diffused or doped on the back surface of the silicon substrate 150 in two times. It may be that N is diffused first and then P is doped, or it may be that P is diffused first and then N is doped. Taking the diffusion layer 111 as P-type and the doping layer 121 as N-type, and taking the example of P-type diffusion first and then N-type doping:

[0070] For the first time, P-type diffusion is carried out. P-type diffusion is carried out in the first region 110 on the back surface of the silicon substrate 150. A dopant such as boron is introduced into the silicon substrate 150 to form a P-type diffusion layer 111. For the second time, N-type doping is carried out. N-type doping is carried out in the second region 120 on the back surface of the silicon substrate 150. A dopant such as phosphorus is introduced into the silicon substrate 150 to form an N-type doping layer 121. Since the second region 120 partially overlaps with the first region 110, when N-type doping is carried out, the N-type dopant is partially stacked on the P-type doping layer 121 to form a stepped surface.

[0071] Before starting N-type doping after the completion of P-type diffusion, a tunneling layer 140 is also introduced. Common materials used for the tunneling layer 140 include SiO2, Al2O3, SiNx, etc. The tunneling layer 140 is isolated between the doping layer 121 and adjacent layers, playing a role of isolation, reducing the interface defects and recombination centers between the doping layer 121 and the silicon substrate 150, and improving the lifetime and collection efficiency of photo-generated carriers.

[0072] The first part 1211 is placed in the overlapping area of the second region 120 and the first region 110, and is stacked on the P-type diffusion layer 111. The second part 1213 is located in the part of the second region 120 that does not overlap with the first region 110, forming a pure N-type doped region. An insulating layer 130 is provided between the diffusion layer 111 and the first part 1211 to prevent the P-type diffusion layer 111 from directly contacting the N-type first part 1211. The third part 1212 connects the first part 1211 and the second part 1213, and is in electrical contact with the P-type doped layer 121 through the tunneling layer 140 on the side of the third part 1212, ensuring electrical contact between the doped layer 121 and the diffusion layer 111.

[0073] In some embodiments, an interface passivation layer 180 is provided between the first part 1211 and the diffusion layer 111 in the first region 110.

[0074] Specifically, the interface passivation layer 180 can be made of the same material as the tunneling layer 140 and is formed in the same process step as the tunneling layer 140. In this process, the tunneling material is deposited. The tunneling layer 140 is deposited on the bottom surface of the second part 1213 and the inner side surface of the third part 1212, and the interface passivation layer 180 is deposited between the first part 1211 and the insulating layer 130.

[0075] It can be understood that since they can be completed in the same process, the tunneling layer 140 and the interface passivation layer 180 can be connected.

[0076] Example 5

[0077] As Figure 3 shown, on the basis of Embodiment 3, the horizontal direction is the first direction, and the first region 110 and the second region 120 are arranged at intervals along the first direction;

[0078] Along the first direction, a groove 190 is provided between some adjacent diffusion layers 111 and doped layers 121. The groove 190 isolates the doped layer 121 and the diffusion layer 111, and the distance from the bottom of the groove 190 to the front surface of the silicon substrate 150 is less than the distance from the second part 1213 to the front surface of the silicon substrate 150.

[0079] The groove 190 penetrates through the corresponding tunneling layer 140 and the doped layer 121, separating the doped layer 121 and the diffusion layer 111. This physical isolation helps to avoid the mutual diffusion between different doped regions, thereby maintaining the electrical characteristics and functional stability of each region, and reducing current leakage and carrier recombination.

[0080] Example 6

[0081] On the basis of Embodiment 5, the total area of the groove 190 accounts for more than or equal to 20% of the total front area of the silicon substrate 150.

[0082] When the total area of the trenches 190 accounts for 20% or more of the total back area of the silicon substrate 150, it means that a relatively large area of the trenches 190 is distributed in the working area of the battery. This design helps to strengthen the electrical isolation effect between the doped layer 121 and the diffusion layer 111, reducing the mutual interference between different functional regions. The relatively large area of the trenches 190 can also effectively guide the separation and transmission path of photo-generated carriers, reducing the recombination of carriers in unwanted regions, thereby improving the photoelectric conversion efficiency of the battery.

[0083] Example 7

[0084] Based on Embodiment Five, the bottom and sidewalls of the trench 190 are the textured surface 101.

[0085] The bottom and sidewalls of the trench 190 being the textured surface 101 increases the surface roughness, enhances light trapping and absorption, and reduces light reflection losses.

[0086] The textured surface 101 structure of the trench 190 can be achieved by various existing manufacturing processes, such as chemical etching or laser etching. These processes are already very mature in the manufacturing of the solar cell 100. Therefore, when introducing the textured surface 101 trench design, it will not significantly increase the manufacturing difficulty or cost. In addition, the processing of the textured surface 101 can be combined with other surface treatment processes to achieve more function integration.

[0087] Example 8

[0088] Based on Embodiment One, the solar cell further includes a first electrode 160 connected to the diffusion layer 111 and a second electrode 170 connected to the doped layer 121. The first electrode 160 is not electrically conductive with the doped layer 121; the connection depth of the first electrode 160 extending into the diffusion layer 111 is less than the connection depth of the second electrode 170 extending into the doped layer 121, and the contact area of the first electrode 160 extending into the diffusion layer 111 is greater than the contact area of the second electrode 170 extending into the doped layer 121.

[0089] The first electrode 160 is connected to the diffusion layer 111. The diffusion layer 111 is formed on the silicon substrate 150 through a doping process, usually N-type or P-type single crystal silicon diffusion. The doping concentration of the diffusion layer 111 is generally low, and the density of mobile carriers (such as electrons or holes) is relatively low, but it is widely distributed. The first electrode 160 requires a larger contact area in the diffusion layer 111 to effectively collect charge carriers. This can reduce the resistance of the current transmission path and increase the charge collection efficiency. Although the contact area is large, the diffusion layer 111 is usually thin. Therefore, the first electrode 160 does not need an overly deep connection depth to achieve effective current collection. If the electrode extends too deep, it may increase the risk of short circuit between the electrode and the substrate or damage other layers.

[0090] It can be understood that in this embodiment, the first electrode 160 is connected to the diffusion layer 111, and the diffusion layer 111 is connected to the doping layer 121 through the tunneling layer 140, that is, the first electrode 160 and the doping layer 121 are indirectly conducted through the diffusion layer 111 and the tunneling layer 140. Except for this conduction path, there is no other direct or indirect conduction path between the first electrode 160 and the doping layer 121 in the solar cell 100. Specifically, a gap or an insulating medium can be provided between the first electrode 160 and the doping layer 121.

[0091] The connection depth of the first electrode 160 extending into the diffusion layer 111 is less than the connection depth of the second electrode 170 extending into the doping layer 121, and the contact area of the first electrode 160 extending into the diffusion layer 111 is greater than the contact area of the second electrode 170 extending into the doping layer 121. The connection depth refers to the penetration distance of the first electrode 160 extending into the diffusion layer 111 or the second electrode 170 extending into the doping layer 121 in the vertical direction, such as Figure 1 h1 and h2 in. The contact area refers to the total area of contact between the bottom surface and the side surface.

[0092] The second electrode 170 is connected to the doping layer 121, and the carrier density of the doping layer 121 is relatively high. Therefore, only a small contact area is required between the electrode and the doping layer 121 to effectively collect charges. The small-area contact can reduce the complexity in the manufacturing process and the use of electrode materials. The doping concentration of the doping layer 121 is relatively high, and its resistivity is relatively low, allowing a deeper electrode connection depth to ensure the effective conduction of a larger current. The deeper connection depth helps to reduce the impedance on the current transmission path and improve the current collection efficiency.

[0093] The contact area of the first electrode 160 extending into the diffusion layer 111 is greater than the contact area of the second electrode 170 extending into the doping layer 121, which helps to ensure the collection efficiency of charge carriers. The connection depth of the first electrode 160 extending into the diffusion layer 111 is less than the connection depth of the second electrode 170 extending into the doping layer 121, which can avoid the interference or short-circuit risk between the electrode and the silicon substrate 150 and ensure the stability of the device.

[0094] Example 9

[0095] On the basis of Embodiment VIII, the content of the glass frit in the first electrode 160 is less than the content of the glass frit in the second electrode 170.

[0096] The main role of the frit (usually glass powder) in the electrode is to enhance the adhesion of the electrode material, improve the contact quality between the electrode and the silicon wafer, and also contribute to forming a stable electrical connection during the sintering process. By reducing the frit content in the first electrode 160, it means that the first electrode 160 may focus more on conductivity and low contact resistance, while the second electrode 170, due to its higher frit content, has better mechanical strength and adhesion.

[0097] Reducing the frit content in the first electrode 160 can reduce the resistance of the electrode material, improve conductivity, thereby reducing the contact resistance between the electrode and the silicon substrate 150, which helps to improve the efficiency and output power of the battery. The second electrode 170 contains a higher amount of frit, which can enhance the mechanical strength and adhesion of the electrode, ensuring the stability and reliability of the electrode during long-term use, and helping to prevent the electrode material from falling off or cracking during sintering or operation.

[0098] Specifically, by fabricating the first electrode 160 and the second electrode 170 step by step, precise control of the frit content in the first electrode 160 and the second electrode 170 can be achieved. At the same time, combined with the laser enhanced contact optimization (LECO) process, the contact resistance between the electrode and the silicon substrate 150 can be optimized, and different electrical properties can be realized in different regions.

[0099] Example 10

[0100] As Figure 4 shown, based on Example 3, the distance between the diffusion layer 111 and the front surface of the silicon substrate 150 is greater than the distance between the second part 1213 and the front surface of the silicon substrate 150. The diffusion layer 111 extends towards the side adjacent to the second part 1213. The insulating layer 130 follows the extension of the diffusion layer 111, and the tunneling layer 140 and the doping layer 121 form a convex position along the extension direction of the diffusion layer 111 and the insulating layer 130.

[0101] The distance between the diffusion layer 111 and the front surface of the silicon substrate 150 is greater than the distance of the second part 1213, and the two are offset in the vertical direction and not on the same horizontal plane. The diffusion layer 111 extends towards the side adjacent to the second part 1213. However, due to the offset in the vertical direction from the second part 1213, the extended diffusion layer 111 does not overlap with the second part 1213. The diffusion layer 111 has a larger coverage area, further increasing the light-receiving area. The insulating layer 130 closely follows the extension of the diffusion layer 111, providing electrical isolation and protection. The tunneling layer 140 and the doping layer 121 form a convex position along the extension direction of the diffusion layer 111 and the insulating layer 130, enclosing the extended parts of the diffusion layer 111 and the insulating layer 130.

[0102] Example 11

[0103] On the basis of Embodiment 3, the difference between the distance of the diffusion layer 111 from the front surface of the silicon substrate 150 and the distance of the second part 1213 from the front surface of the silicon substrate 150 is 1 μm to 6 μm.

[0104] See Figure 2 In H of, the vertical distance between the diffusion layer 111 and the second part 1213 is 1 μm to 6 μm. Specifically, it can be 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm, 2 μm, 2.2 μm, 2.4 μm, 2.6 μm, 2.8 μm, 3 μm, 3.5 μm, 3.9 μm, 4 μm, 4.5 μm, 4.8 μm, 5 μm, 5.3 μm, 5.6 μm, 5.9 μm, 6 μm, etc. The above are not all listed.

[0105] By controlling this distance, a strong built-in electric field can be formed between the diffusion layer 111 and the second part 1213, promoting the effective separation of photo-generated carriers, reducing recombination losses, and thus improving the photoelectric conversion efficiency of the battery.

[0106] Example 12

[0107] On the basis of Embodiment 1, the diffusion layer 111 is a P-type doped single crystal silicon; the doping layer 121 is an N-type doped polycrystalline silicon.

[0108] Single crystal silicon is a material with a highly ordered crystal structure and no grain boundaries or other large-area defects. Due to its highly consistent lattice arrangement, single crystal silicon can ensure uniform distribution of doping atoms during the diffusion process, forming a high-quality diffusion layer 111. P-type single crystal silicon has a high carrier mobility and a low defect density, which can provide good electrical properties and photoelectric conversion efficiency.

[0109] The production process of polycrystalline silicon is relatively simple and the cost is relatively low, making it an ideal choice for large-area doping layer 121. During chemical vapor deposition (CVD) or physical vapor deposition (PVD) of polycrystalline silicon, the doping concentration can be easily controlled. By adjusting the deposition parameters, polycrystalline silicon can achieve different doping concentrations and distributions, thereby optimizing the electrical properties of the doping layer 121 and improving the overall efficiency of the solar cell 100. N-type doped polycrystalline silicon not only has a low cost, but also can achieve uniform control of the doping concentration over a large area, which is suitable for large-scale manufacturing.

[0110] The combination of P-type single crystal silicon and N-type polycrystalline silicon makes full use of the advantages of the two materials, forming an efficient heterojunction structure. Single crystal silicon provides the characteristics of high mobility and low recombination loss, while polycrystalline silicon further enhances the battery performance through its doping flexibility and cost-effectiveness.

[0111] Example 13

[0112] This embodiment provides a battery assembly, including the solar cell 100 of the above embodiment.

[0113] Generally, multiple solar cells 100 in a photovoltaic module can be connected in series in sequence to form a battery string. Each battery string can be connected in series, in parallel, or in a series-parallel combination to achieve the current collection and output. For example, the connection between each solar cell 100 can be realized by welding a solder strip, and the connection between each battery string can be realized by a bus bar.

[0114] The beneficial effects of the photovoltaic module of this embodiment are equivalent to those of the above solar cell 100, and will not be elaborated here.

[0115] Example 14

[0116] This embodiment provides a photovoltaic system, including the battery assembly of the above embodiment.

[0117] The beneficial effects of the photovoltaic system of this embodiment are equivalent to those of the above solar cell 100, and will not be elaborated here.

[0118] The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A solar cell, characterized in that, Comprising: A silicon substrate having a back surface and a front surface disposed opposite to each other; A diffusion layer located in a first region on the back surface of the silicon substrate; A doped layer located in a second region on the back surface of the silicon substrate, the doped layer and the diffusion layer having opposite polarities; A tunneling layer, with opposite sides of the tunneling layer respectively contacting the diffusion layer and the doped layer; The surface of the silicon substrate facing the doped layer is a polished surface, and the surface of the diffusion layer facing away from the silicon substrate is a textured surface, and the total area of the textured surface is larger than the total area of the polished surface.

2. The solar cell according to claim 1, wherein The total area of the textured surface is 1.1 to 3 times the total area of the polished surface.

3. The solar cell according to claim 1, characterized in that, Taking the horizontal direction as the first direction, the first region and the second region are spaced apart along the first direction; opposite sides of the tunneling layer along the first direction respectively contact the diffusion layer and the doped layer.

4. The solar cell according to claim 1, wherein, The second region partially overlaps with the first region, the doped layer includes a first part, a second part, and a third part connecting the first part and the second part, the first part is placed in the overlapping region of the second region and the first region, and is disposed above the diffusion layer; An insulating layer is provided between the diffusion layer and the first part, and the tunneling layer is provided on the bottom surface of the second part and the inner side surface of the third part.

5. The solar cell according to claim 4, characterized in that, An interface passivation layer is provided between the first part and the insulating layer within the first region.

6. The solar cell according to claim 5, characterized in that, The tunneling layer is connected to the interface passivation layer.

7. The solar cell according to claim 4, wherein Taking the horizontal direction as the first direction, the first region and the second region are spaced apart along the first direction; Along the first direction, a groove is provided between some adjacent diffusion layer and doped layer, the groove isolates the doped layer and the diffusion layer, and the distance from the bottom of the groove to the front surface of the silicon substrate is less than the distance from the second part to the front surface of the silicon substrate.

8. The solar cell according to claim 7, characterized in that, The total area of the groove accounts for more than or equal to 20% of the total area of the back surface of the silicon substrate.

9. The solar cell according to claim 7, characterized in that, The bottom and the side walls of the groove are textured surfaces.

10. The solar cell according to claim 1, wherein, It further includes a first electrode connected to the diffusion layer and a second electrode connected to the doped layer, the first electrode is not electrically connected to the doped layer; the connection depth of the first electrode extending into the diffusion layer is less than the connection depth of the second electrode extending into the doped layer, and the contact area of the first electrode extending into the diffusion layer is larger than the contact area of the second electrode extending into the doped layer.

11. The solar cell according to claim 10, characterized in that, The content of glass frit in the first electrode is less than the content of glass frit in the second electrode.

12. The solar cell according to claim 4, wherein The distance from the diffusion layer to the front surface of the silicon substrate is greater than the distance from the second part to the front surface of the silicon substrate, the diffusion layer extends towards the side where the second part is adjacent, the insulating layer follows the extension of the diffusion layer, and the tunneling layer and the doped layer form a convex position along the extension direction of the diffusion layer and the insulating layer.

13. The solar cell according to claim 4, wherein, The difference between the distance from the diffusion layer to the front surface of the silicon substrate and the distance from the second part to the front surface of the silicon substrate is 1 μm to 6 μm.

14. The solar cell according to claim 1, wherein The diffusion layer is a P-type doped single crystal silicon; the doped layer is an N-type doped polycrystalline silicon.

15. A battery assembly, characterized in that, Comprising the solar cell according to any one of claims 1 to 14.

16. A photovoltaic system, characterized in that, Comprising the battery module according to claim 15.

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