BUCK step-down circuit capable of realizing ZVS (Zero Voltage Suppressor) of upper tube and lower tube

Abstract

The utility model relates to a BUCK step-down circuit capable of realizing ZVS of both an upper tube and a lower tube, which comprises a control chip U1 and a control chip U1, the control chip U1 controls an upper tube Q1 and a lower tube Q2 by detecting voltage at two ends of an inductor so as to enable the upper tube Q1 to work in a ZVS mode, and the control chip generates control signals which are respectively connected with grid electrodes of the upper tube Q1 and the lower tube Q2; and the control chip generates control signals which are respectively connected with the grid electrodes of the upper tube Q1 and the lower tube Q2. In the utility model, as the upper tube can also realize ZVS (Zero Voltage Suppressor), the energy efficiency can be improved.

Description

Technical Field

[0001] The utility model relates to a BUCK step-down circuit, in particular to a BUCK step-down circuit that can achieve ZVS for both the upper and lower tubes. Background Art

[0002] Currently, there are more and more types of consumer electronic products, resulting in a growing demand for charging devices. Each digital e-commerce accessory manufacturer has correspondingly launched multi-port output chargers. Most consumer electronic products are currently fast-charging, and when charging simultaneously, the output voltage of each port will not be the same. Therefore, it is required that each port is preferably an independent circuit. The common structures on the market are as Figure 1 shown, mainly consisting of two parts. First, AC TO DC and then DC TO DC, that is, first the mains AC is converted to DC total output by a switching power supply, and then the DC is converted to DC outputs of different voltages. And for portability, the volume is getting smaller and smaller. As the volume gets smaller and smaller, only the charging energy efficiency can be made higher and higher, and the switching frequency of the product can only be made higher and higher. Since the output to the USB port and then to power the electronic product goes through two-stage circuits, first AC-DC and then DC-DC, each part of the circuit has losses. The greater the losses, the lower the efficiency. At the same temperature under the same requirements, the product size is also required to be larger.

[0003] Currently, the DC-DC circuit is generally implemented using a BUCK step-down circuit. The BUCK circuit is as Figure 2 shown: Also known as a step-down circuit, its basic feature is a DC-DC conversion circuit, where the output voltage is lower than the input voltage. The input current is pulsating, and the output current is continuous. As Figure 2 shown, the output of the switching power supply that realizes AC to DC (AC-DC) is used here as the DC input Vin of the BUCK. There are two switches, which can generally be implemented using MOS transistors or other switching devices. Here, K1 represents the electronic switch, an electronic switch controlled by a PWM signal. K2 is a diode, and its function is to conduct unidirectionally. In many cases, it is also implemented using an electronic switch. When K1 and K2 are implemented using MOS transistors, they are also respectively called the upper tube and the lower tube.

[0004] Currently, in order to improve efficiency, reduce losses, and thus reduce the heat generation and ultimately reduce the product size, R & D engineers have separately improved the efficiency of the circuit blocks. Advanced high-frequency and low-loss materials are used in terms of materials, and the AC-DC circuit architecture adopts the currently most advanced LLC resonance architecture, which is almost perfect. The DC-DC uses a general BUCK step-down circuit such as Figure 2 , however, there is currently a problem of low conversion efficiency in the BUCK step-down circuit with high input and low output, and the problem that the higher the DC-DC operating frequency, the lower the efficiency. This time, the main focus is on improving the problem of low DC-DC conversion efficiency.

[0005] AsFigure 2 As shown: The main losses of the BUCK circuit are currently in the switching transistors K1, K2, and the inductor L. The loss of the inductor L is determined by the material and has little impact on the current architecture, and it can be customized according to cost. The switching transistors K1 and K2 are MOS semiconductor devices, and the lowest loss can be achieved in terms of materials, but the characteristics of the current circuit architecture also greatly determine the loss. From Figure 2 it can be seen that the loss of the switching transistor K2 in the current BUCK bucking circuit is relatively low, working in the soft-switching state and capable of achieving ZVS turn-on, but the switching transistor K works in the hard-switching state, resulting in extremely large switching losses. The off-the-shelf BUCK bucking circuits on the market currently cannot achieve soft-switching ZVS, which also leads to an increase in the charger's heat generation and the energy efficiency in the 5V gear not meeting the requirements. Summary of the Invention

[0006] Aiming at the deficiency that the energy efficiency in the current BUCK bucking circuit cannot meet the requirements of users, the present invention provides a BUCK bucking circuit that can achieve ZVS for both the upper and lower transistors. In this circuit, not only the switching transistor K2 can achieve ZVS turn-on, but also the switching transistor K1 can achieve ZVS turn-on, improving the energy efficiency.

[0007] The technical solution of the present invention is: A BUCK bucking circuit that can achieve ZVS for both the upper and lower transistors converts the input DC power supply Vin into the output DC power supply Vout by bucking; it includes the upper transistor Q1 and the lower transistor Q2, the inductor L1, and the electrolytic capacitor EC1; both the upper transistor Q1 and the lower transistor Q2 are MOS transistors. The anode of the input DC power supply Vin is connected to the drain of the upper transistor Q1, the source of the upper transistor Q1 is respectively connected to one end of the inductor L1 and the drain of the lower transistor Q2, and the source of the lower transistor Q2 is connected to the cathode of the input DC power supply Vin; the other end of the inductor L1 is connected to the anode of the electrolytic capacitor EC1, and the cathode of the electrolytic capacitor EC1 is connected to the cathode of the input DC power supply Vin;

[0008] It also includes a control chip U1 that controls the upper transistor Q1 and the lower transistor Q2 by detecting the voltage across the inductor, so that the upper transistor Q1 works in the ZVS mode. The control signals generated by the control chip are respectively connected to the gates of the upper transistor Q1 and the lower transistor Q2.

[0009] Further, in the above-mentioned BUCK bucking circuit that can achieve ZVS for both the upper and lower transistors: The input DC power supply Vin is 21VDC, and the output DC power supply Vout is between 5VDC and 20VDC.

[0010] Further, in the above-mentioned BUCK bucking circuit that can achieve ZVS for both the upper and lower transistors: The detected voltage across the inductor L1 is greater than the set value of 9V.

[0011] Further, in the above-mentioned BUCK buck-boost circuit that can achieve ZVS for both the upper and lower transistors: when detecting the zero crossing of inductor L1, voltage-dividing resistors R2 and R3 between the downstream of the inductor and ground are adopted. When the voltage between voltage-dividing resistors R2 and R3 is 0V, the control chip determines the zero crossing.

[0012] Further, in the above-mentioned BUCK buck-boost circuit that can achieve ZVS for both the upper and lower transistors: the turn-on time of lower transistor Q2 is 200 ns.

[0013] Further, in the above-mentioned BUCK buck-boost circuit that can achieve ZVS for both the upper and lower transistors: the electrolytic capacitor EC1 provides a backflow current of 84 mA to inductor L1.

[0014] Further, in the above-mentioned BUCK buck-boost circuit that can achieve ZVS for both the upper and lower transistors: the electrolytic capacitor EC1 is set to 470 μF; the junction capacitances of lower transistor Q2 and upper transistor Q1 are both set to 200 pF.

[0015] In the present utility model, since the upper transistor can also achieve ZVS, the energy efficiency will be improved.

[0016] The following describes the present utility model in detail with reference to the drawings and specific embodiments. Description of the Drawings

[0017] Figure 1 is a structural diagram of a common charger on the market;

[0018] Figure 2 is a schematic diagram of a BUCK principle;

[0019] Figure 3 is a schematic diagram of the BUCK buck-boost circuit of Embodiment 1 of the present utility model;

[0020] Figure 4 is a schematic diagram of the hard switching of upper transistor Q1 in the BUCK circuit without ZVS loss;

[0021] Figure 5 is a schematic diagram of the soft switching of upper transistor Q1 in the BUCK circuit with ZVS loss. Detailed Embodiment

[0022] This embodiment is a BUCK buck-boost circuit that can achieve ZVS for both the upper and lower transistors. As Figure 3 shown, the circuit mainly consists of upper transistor Q1, lower transistor Q2, inductor L1, and electrolytic capacitor EC1. Among them, MOS transistors are used for upper transistor Q1 and lower transistor Q2 as switches, and the gates of upper transistor Q1 and lower transistor Q2 are controlled by control chip U1.

[0023] In the BUCK buck - down circuit of this embodiment, the input DC power supply Vin is stepped down to convert into the output DC power supply Vout. The anode of the input DC power supply Vin is connected to the drain of the upper transistor Q1, the source of the upper transistor Q1 is respectively connected to one end of the inductor L1 and the drain of the lower transistor Q2, and the source of the lower transistor Q2 is connected to the cathode of the input DC power supply Vin. The other end of the inductor L1 is connected to the anode of the electrolytic capacitor EC1, and the cathode of the electrolytic capacitor EC1 is connected to the cathode of the input DC power supply Vin. In fact, the output DC power supply Vout is formed across the two ends of the electrolytic capacitor.

[0024] The control chip U1 generates control signals and connects them to the gates of the upper transistor Q1 and the lower transistor Q2 respectively. As we know, the working modes of the Buck circuit mainly include CCM (Continuous Conduction Mode), BCM (Boundary Conduction Mode), and DCM (Discontinuous Conduction Mode). Among them, the CCM mode is the normal working mode of the Buck circuit, at this time the inductor current is continuous throughout the switching period. In the CCM mode, the rise and fall of the inductor current are smooth and there is no sudden change. The control chip U1 realizes the above - mentioned various working modes by controlling the gates of the upper transistor Q1 and the lower transistor Q2. Discontinuous Conduction Mode (DCM): Within one switching period, the inductor current will return to zero, and the inductor current is zero. Boundary Conduction Mode (BCM): A working mode between CCM and DCM. The CCM mode is the normal working mode of the BUCK. In this embodiment, according to the task of the control chip itself, a control chip U1 is designed like this.

[0025] In this embodiment, the control chip U1 controls the working mode of the inductor L1 to be in the CCM working mode. When it detects that the voltage across the inductor L1 is greater than the set value, it controls the working mode of the inductor L1 to be changed to the QR mode. In the QR mode, zero - crossing detection of the inductor L1 is performed, and the lower transistor Q2 is forced to turn on once to allow the electrolytic capacitor EC1 to back - feed current to the inductor L1, thereby realizing the ZVS function of the upper transistor Q1. In this embodiment, in practice, the control chip U1 can control the upper transistor Q1 to work in the ZVS mode. In fact, the SW pin of the control chip U1 collects the voltage signal on the left side of the inductor L1 and compares it with the voltage of the Vref pin inside the chip. Here, the Vref pin uses the signal obtained by dividing the voltage on the right side of the inductor L1 by two 100K resistors R2 and R3. The difference between them is actually the voltage across the inductor L1. When this voltage value is greater than 9V, it enters the QR mode, and further makes the upper transistor Q1 enter the ZVS working mode.

[0026] Such as Figure 3As shown in the figure, currently, the main losses in the BUCK circuit are in the upper transistor Q1, the lower transistor Q2, and the inductor L1. The loss of the inductor L1 is determined by the material and has little impact on the current architecture, and it can be customized according to cost. The upper transistor Q1 and the lower transistor Q2 are MOS semiconductor devices, and the lowest loss can be achieved in terms of materials, but the characteristics of the current circuit architecture also have a great influence on the loss. From Figure 3 it can be seen that currently, the loss of the lower transistor Q2 in the BUCK buck circuit is relatively low, working in the soft-switching state, and can achieve ZVS turn-on. However, the upper transistor Q1 works in the hard-switching state, resulting in extremely large switching losses. The ready-made BUCK buck circuits on the market currently cannot achieve soft-switching ZVS (referring to the MOS-DS pole 0.7V voltage turn-on function), which also leads to an increase in charger heating and the energy efficiency in the 5V gear not meeting the requirements. The switching loss is mainly determined by the turn-on voltage across the MOS. Simply understood, the turn-on loss P = Vds * Id * Fk (Id is determined by the load and remains unchanged. The larger Vds is, the larger P is. Fk is the IC control frequency. The higher the frequency, the larger the switching loss). Currently, the common frequencies for small sizes are 120k, 180K, and 350K.

[0027] The corresponding conversion efficiency in the current BUCK circuit is as follows: (tested at the working frequency of 180K of the IC), the inductor L1 is in an ideal state and is close to 0V

[0028]

[0029] The efficiency in the above table only gives examples and comparisons for switching losses. Other losses account for a small proportion of the output voltage change. From the data, the higher the VDS turn-on voltage, the worse the corresponding conversion efficiency, and the efficiency is even lower at 25% load and low current in each gear. If the DC BUCK circuit is moved to the AC TO DC circuit, it will be very difficult for the 5V gear efficiency to meet the requirements of level 6 energy efficiency, and it will be impossible to obtain relevant energy efficiency certification certificates. From the current data and analysis, the main source of the switching loss is the upper transistor Q1 because it cannot achieve the ZVS function. This embodiment is to improve the circuit for the upper transistor Q1.

[0030] The main improvement is:

[0031] Change the working mode of the original BUCK circuit from the CCM mode to the QR mode by identifying the output voltage for adjustment. Then, under the QR mode, perform zero-crossing detection and forcibly turn on the lower transistor Q2 for a short time to allow the electrolytic capacitor EC1 to backfeed current to the inductor L1, thereby reducing the VDS voltage of the upper transistor Q1 to 0V, thus achieving the ZVS function.

[0032] QR implementation process: The voltages across both ends of inductor L1 are detected by the 3rd pin (SW) and the 2nd pin (Vref) of control chip U1 respectively, which are the VDS turn-on voltages during normal operation. If the voltage difference is greater than 9V, the circuit control logic mode is changed to the QR mode. If the voltage difference is less than 9V, the circuit operating mode remains CCM (it can be known from the above table that when VDS is greater than 9V, the efficiency is acceptable when the voltage difference is less than 9V as shown in the above table), so the inductor parameters will not change significantly. Although QR realizes the zero-crossing function, due to the existence of the Miller capacitance in the MOS, there is still switching loss. Therefore, Q1 needs to be designed with ZVS (zero voltage turn-on, making the voltage across Vds 0V) turn-on ability. P (turn-on loss) = 1 / 2 * Vds * Id * Fk (when Vds is 0V or 0.7V compared to when Vds is 16V, the P switching loss can only be nearly 0W).

[0033] Process of realizing ZVS for the upper transistor Q1: To realize ZVS, the current in inductor L must pass through zero. Therefore, only QR can realize the ZVS function. CCM is the continuous mode, and the inductor current cannot pass through zero, so the ZVS function cannot be realized. The zero-crossing detection is completed by the 3rd pin of controller U1. After the inductor passes through zero, when the SW pin detects 0V, it is determined that the current in inductor L1 has passed through zero. The upper transistor Q1 continues to be turned off, and the load is powered by electrolytic capacitor EC1. At this time, the lower transistor Q2 is turned on for about 200ns to make electrolytic capacitor EC1 charge inductor L1 reversely, similar to a boost inductor. After 200ns, the lower transistor Q2 is turned off, and no current can flow through the lower transistor Q2. Since the current in inductor L1 cannot change suddenly, the current continues to be negative from right to left, charging the junction capacitance Cds of the lower transistor Q2 and discharging the junction capacitance Cds of the upper transistor Q1. As long as the voltage charged on the junction capacitance Cds of the lower transistor Q2 is greater than 21V + 0.7V, the body diode of the upper transistor Q1 conducts naturally, and the voltage drop of the upper transistor Q1 Vds is 0.7V. At this time, applying a driving voltage to the upper transistor Q1, the upper transistor Q1 realizes the ZVS turn-on function.

[0034] In this embodiment, the reverse current of the lower transistor Q2 is: Ipeak = C * U / T = 21.7V * 220pf * 4 / 200nS = 84mA, which can charge the junction capacitance of the lower transistor Q2 to 21.7V to ensure the conduction of the body diode of the upper transistor Q1, thereby realizing the ZVS function of the upper transistor Q1. The power consumption P generated by 84mA = 0.084 * 0.084 * 0.07 < 0.01W and can be ignored.

[0035] In this embodiment, the electrolytic capacitor EC1 is set to 470 μF, and the Q2 / Q1 junction capacitance is set to 200 pF. The electrolytic capacitor EC1 charges the lower transistor Q2 reversely to 21.7 V, and the voltage drop is: 0.5 * 800 * 21.7^2 = 0.5 * 470 * Vout1^2 - Vout2^. Finally, it is calculated that the voltage drop of the electrolytic capacitor EC1 is 0.00008 V, which is almost negligible and has no impact on the output voltage.

[0036] Such as Figure 4 And Figure 5 are the losses of the hard switch without ZVS and the soft switch with ZVS respectively. It can be seen that in the case of the soft switch with ZVS, the turn-on loss is close to 0.

[0037] Test and comparison of the conversion efficiency of the improved circuit:

[0038]

[0039] The verification and comparison effect of the BUCK circuit in this embodiment is improved significantly after improvement, which proves that there is an actual effect.

Claims

1. A BUCK bucking circuit that can achieve ZVS for both the upper and lower transistors, which steps down the input DC power supply Vin to convert it into the output DC power supply Vout; it includes the upper transistor Q1, the lower transistor Q2, the inductor L1, and the electrolytic capacitor EC1; it is characterized in that: Both the upper transistor Q1 and the lower transistor Q2 are MOS transistors. The anode of the input DC power supply Vin is connected to the drain of the upper transistor Q1. The source of the upper transistor Q1 is respectively connected to one end of the inductor L1 and the drain of the lower transistor Q2. The source of the lower transistor Q2 is connected to the cathode of the input DC power supply Vin. The other end of the inductor L1 is connected to the anode of the electrolytic capacitor EC1, and the cathode of the electrolytic capacitor EC1 is connected to the cathode of the input DC power supply Vin. It further includes a control chip U1 that controls the upper transistor Q1 and the lower transistor Q2 by detecting the voltage across the inductor, so that the upper transistor Q1 operates in the ZVS mode. The control signals generated by the control chip U1 are respectively connected to the gates of the upper transistor Q1 and the lower transistor Q2.

2. The BUCK bucking circuit that enables ZVS for both the upper and lower tubes according to claim 1, characterized in that: The input DC power supply Vin is 21VDC, and the output DC power supply Vout is between 5VDC and 20VDC.

3. The BUCK buck - down circuit capable of achieving ZVS for both the upper and lower tubes according to claim 2, wherein: The detected voltage across the inductor L1 is greater than the set value of 9V.

4. The BUCK bucking circuit capable of achieving ZVS for both the upper and lower tubes according to claim 2, characterized in that: The on-time of the lower transistor Q2 is 200ns.

5. The BUCK buck - down circuit capable of achieving ZVS for both the upper and lower tubes according to claim 2, characterized in that: The electrolytic capacitor EC1 provides a reverse current of 84mA to the inductor L1.

6. The BUCK buck - down circuit that can achieve ZVS for both the upper and lower tubes according to claim 2, characterized in that: The electrolytic capacitor EC1 is set to 470UF; the junction capacitances of both the lower transistor Q2 and the upper transistor Q1 are set to 200PF.

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