Active crystal oscillator circuit with false triggering prevention function
The described circuit design using NMOS transistors and capacitors isolates and filters unwanted signals to prevent misfiring of crystal oscillators, ensuring accurate clock signals and system stability in electronic devices.
Patent Information
- Application Number
- CN202422262996.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-14
- Publication Date
- 2025-07-15
- Estimated Expiration
- 2034-09-14
AI Technical Summary
Active crystal oscillator is easily triggered by mistake when there are microsecond-level pulses in the power supply or enable signal, resulting in inaccurate clock signal and affecting the timing of the integrated circuit and system stability.
The first NMOS tube and the second NMOS tube are used to form an isolation circuit to isolate the enable control signal of the external control module and the active crystal oscillator, and filter out the pulses at the power supply terminal through the parallel capacitor circuit to prevent false triggering.
Effectively prevent active crystal oscillator from being triggered by mistake during power-on or power-on, ensure accurate clock signals and ensure system stability.
Smart Images
Figure CN223109978U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of oscillation circuits, in particular to an active crystal oscillator circuit with an anti-false triggering function. Background Art
[0002] A crystal oscillator is an electronic component that uses the piezoelectric effect and resonance characteristics of a crystal to generate a stable frequency signal. Because it can generate a stable frequency signal, crystal oscillators are widely used in various electronic devices to provide a stable frequency source and clock signal.
[0003] Crystal oscillators can be divided into two types: passive crystal oscillators and active crystal oscillators. Passive crystal oscillators require external circuits to provide excitation signals and amplifier circuits to achieve oscillation; active crystal oscillators integrate complete oscillation circuits and amplifier circuits, and can directly output stable frequency signals without external circuits. In contrast, active crystal oscillators can provide clock and frequency signals with higher accuracy and stability, so they are more widely used in applications that require accurate clock and frequency control, such as computers, communication equipment, precision instruments and other electronic equipment.
[0004] Active crystal oscillators are widely used in the hardware circuit design of electronic equipment such as computers, communication equipment, and precision instruments. They are basically used in various integrated circuits (ICs) such as hubs (HUBs), bridges (Bridges), and host bus adapters (HBAs). In practical applications, many integrated circuits have extremely high requirements for the timing of crystal oscillators. It is necessary to ensure that the crystal oscillator can only start at a specific time, and it is necessary to ensure that the crystal oscillator is not falsely triggered when the machine is turned on or powered on. However, in the actual testing process, it was found that many active crystal oscillators will be falsely triggered when the power supply or enable signal has a microsecond (μs) level pulse, generating a microsecond (μs) or millisecond (ms) time sine wave, which will lead to inaccurate clock signals, affect the timing of the integrated circuit, and cause system instability.
[0005] Therefore, how to prevent the active crystal oscillator from being falsely triggered is a technical problem that needs to be solved urgently. Summary of the invention
[0006] The utility model aims to provide an active crystal oscillator circuit with an anti-false triggering function, which can effectively prevent the active crystal oscillator from being falsely triggered.
[0007] To achieve the above object, the present utility model provides an active crystal oscillator circuit with an anti-mis-triggering function, which includes an active crystal oscillator, a first NMOS transistor, a second NMOS transistor, a first resistor, a second resistor, and a third resistor. Among them, the gate of the first NMOS transistor is used to receive an enable control signal provided by an external control module for the active crystal oscillator, the source of the first NMOS transistor is grounded, and the drain of the first NMOS transistor is connected to a first power supply through the first resistor; the gate of the second NMOS transistor is connected to the drain of the first NMOS transistor, and the source of the second NMOS transistor is grounded; the second resistor and the third resistor are connected in series between a second power supply and ground, and the drain of the second NMOS transistor is connected between the second resistor and the third resistor and is connected to the enable end of the active crystal oscillator.
[0008] Preferably, the active crystal oscillator circuit further includes a parallel capacitor circuit. The power supply terminal of the active crystal oscillator is connected to a third power supply and is connected to the parallel capacitor circuit. The parallel capacitor circuit includes a plurality of capacitors. One end of each capacitor is connected to the power supply terminal, and the other end of each capacitor is grounded. And the plurality of capacitors includes a first capacitor, and the capacitance value of the first capacitor is greater than or equal to 10 microfarads.
[0009] Preferably, the plurality of capacitors further includes a second capacitor and a third capacitor. The capacitance value of the second capacitor is 0.01 microfarads, the capacitance value of the third capacitor is 1 microfarad, and the capacitance value of the first capacitor is 10 microfarads.
[0010] Preferably, the power supply terminal of the active crystal oscillator is connected to the third power supply through a chip bead.
[0011] Preferably, the third resistor is connected between the second resistor and ground, and the resistance value of the third resistor is 10 times the resistance value of the second resistor.
[0012] Preferably, the active crystal oscillator circuit is an active crystal oscillator circuit on a computer motherboard. The first power supply and the second power supply are the P3V3SB power supply of the computer motherboard, and the third power supply is the P3V3 power supply of the computer motherboard.
[0013] Preferably, the gate of the first NMOS transistor is connected to an embedded controller or a complex programmable logic device.
[0014] Preferably, the first NMOS transistor and the second NMOS transistor are implemented by a dual N-channel MOS transistor.
[0015] Preferably, the ground terminal of the active crystal oscillator is grounded, and the output terminal of the active crystal oscillator outputs a clock signal.
[0016] Advantages of the present utility model: The active crystal oscillator circuit with an anti-mis-triggering function of the present utility model uses a first NMOS transistor and a second NMOS transistor to form an isolation circuit between an external control module and the active crystal oscillator, isolating the enable control signal sent by the external control module to the active crystal oscillator from the enable terminal of the active crystal oscillator, so that even if the external control module sends out pulses by mistake, it will not affect the active crystal oscillator. In this way, when the electronic device to which the active crystal oscillator circuit of the present utility model is applied is powered on or starts up, pulses sent by mistake by the control module of the active crystal oscillator, such as an embedded controller or a complex programmable logic device, will not affect the active crystal oscillator, and the active crystal oscillator will not be mis-triggered to generate a sine wave with a microsecond or millisecond time, thus effectively preventing the enable terminal of the active crystal oscillator from being mis-triggered, ensuring that the active crystal oscillator can provide an accurate clock signal, and guaranteeing system stability; moreover, the active crystal oscillator circuit of the present utility model is also connected with a parallel capacitor circuit at the power supply terminal of the active crystal oscillator. At least one capacitor with a capacitance of not less than 10 microfarads is provided in the parallel capacitor circuit to slow down the rising edge of the power supply of the active crystal oscillator and increase the response time of the active crystal oscillator, so as to filter out pulses that may be generated by the third power supply connected to the power supply terminal of the active crystal oscillator, effectively avoiding the situation that when there are pulses in the third power supply, the active crystal oscillator will be mis-triggered to generate a sine wave. In this way, when the electronic device to which the active crystal oscillator circuit of the present utility model is applied is powered on or starts up, pulses sent by mistake by the third power supply will not affect the active crystal oscillator, and the active crystal oscillator will not be mis-triggered to generate a sine wave with a microsecond or millisecond time, thus effectively preventing the power supply terminal of the active crystal oscillator from being mis-triggered, ensuring that the active crystal oscillator can provide an accurate clock signal, and guaranteeing system stability. It can be seen from this that the active crystal oscillator circuit of the present utility model can not only prevent the enable terminal of the active crystal oscillator from being mis-triggered, but also prevent the power supply terminal of the active crystal oscillator from being mis-triggered, thus effectively preventing the active crystal oscillator from being mis-triggered. Description of the Drawings
[0017] In order to further understand the features and technical content of the present utility model, please refer to the following detailed description and drawings of the present utility model. However, the drawings are only for reference and illustration, and are not used to limit the present utility model. In the drawings,
[0018] Figure 1 is the circuit wiring diagram of the active crystal oscillator circuit with an anti-mis-triggering function of the present utility model. Detailed Embodiments
[0019] To further elaborate on the technical means and effects adopted by the present utility model, the following describes in detail the preferred embodiments of the present utility model and their accompanying drawings.
[0020] As Figure 1As shown in the figure, the present utility model provides an active crystal oscillator circuit 10 with an anti-mis-triggering function, which includes an active crystal oscillator 11, a first NMOS transistor Q1, a second NMOS transistor Q2, a first resistor R1, a second resistor R2, and a third resistor R3. Among them, the gate of the first NMOS transistor Q1 is used to receive the enable control signal OSC_EN provided by an external control module for the active crystal oscillator 11. The source of the first NMOS transistor Q1 is grounded, and the drain of the first NMOS transistor Q1 (the OSC_EN_Q signal terminal in the figure) is connected to a first power supply P1 through the first resistor R1. The gate of the second NMOS transistor Q2 is connected to the drain of the first NMOS transistor Q1, and the source of the second NMOS transistor Q2 is grounded. The second resistor R2 and the third resistor R3 are connected in series between a second power supply P2 and the ground, and the drain of the second NMOS transistor Q2 is connected between the second resistor R2 and the third resistor R3 and is connected to the enable terminal OE_N / ST / NC of the active crystal oscillator 11.
[0021] When the external control module provides a normal high-level enable control signal for the active crystal oscillator 11, the gate of the first NMOS transistor Q1 receives the high-level enable control signal, the first NMOS transistor Q1 conducts, and the second NMOS transistor Q2 cuts off. Due to the settings of the second power supply P2, the second resistor R2, and the third resistor R3, the drain of the second NMOS transistor Q2 is at a high level, and the enable terminal OE_N / ST / NC of the active crystal oscillator 11 is also pulled up to a high level. Therefore, the active crystal oscillator 11 can work normally and generate an output signal.
[0022] When the external control module does not provide a high-level enable control signal, the gate of the first NMOS transistor Q1 is in a low-level state, the first NMOS transistor Q1 cuts off, the second NMOS transistor Q2 conducts, and the drain of the second NMOS transistor Q2 provides a low-level signal to the enable terminal OE_N / ST / NC of the active crystal oscillator 11. Then the active crystal oscillator 11 does not work and does not generate an output signal.
[0023] When the external control module accidentally sends a pulse to the active crystal oscillator circuit 10, that is, the gate of the first NMOS transistor Q1 receives a pulse signal. Although the first NMOS transistor Q1 may also be turned on due to the influence of the pulse, due to the parasitic capacitance and conduction delay characteristics of the first NMOS transistor Q1 and the second NMOS transistor Q2 themselves, the first NMOS transistor Q1 and the second NMOS transistor Q2 can optimize the pulse so that it cannot be transmitted to the enable terminal OE_N / ST / NC of the active crystal oscillator 11. The active crystal oscillator 11 will not be accidentally triggered due to the accidental pulse sent by the external control module, avoiding the situation that the active crystal oscillator 11 will be accidentally triggered when there is a pulse at the microsecond level in the enable control signal and generate a sine wave with a microsecond or millisecond time.
[0024] It can be seen that the active crystal oscillator circuit of the present invention forms an isolation circuit by the first NMOS transistor Q1 and the second NMOS transistor Q2, isolating the enable control signal sent by the external control module to the active crystal oscillator 11 from the enable terminal of the active crystal oscillator 11, so that the accidental pulse sent by the external control module will not affect the active crystal oscillator 11.
[0025] In a specific embodiment, the external control module may be an Embedded Controller (EC) or a Complex Programmable Logic Device (CPLD). That is, the gate of the first NMOS transistor Q1 is connected to the embedded controller or the complex programmable logic device to receive the enable control signal from the embedded controller or the complex programmable logic device. The active crystal oscillator circuit of the present invention can ensure that when the applied electronic device is powered on or powered up, the accidental pulse sent by the embedded controller or the complex programmable logic device will not affect the active crystal oscillator 11 and will not accidentally trigger the active crystal oscillator 11 to generate a sine wave with a microsecond or millisecond time.
[0026] Further, the third resistor R3 is connected between the second resistor R2 and the ground, and the resistance value of the third resistor R3 is 10 times that of the second resistor R2. In the illustrated embodiment, the resistance value of the third resistor R3 may be 10K ohms, and the resistance value of the second resistor R2 may be 1K ohm, but it is not limited thereto, to ensure that the enable terminal OE_N / ST / NC of the active crystal oscillator 11 is in a high level state when the gate of the first NMOS transistor Q1 receives a high level enable control signal, the first NMOS transistor Q1 is turned on, and the second NMOS transistor Q2 is turned off, so that the active crystal oscillator 11 can work normally.
[0027] Further, the active crystal oscillator circuit 10 further includes a parallel capacitor circuit 12. The power supply terminal VDD of the active crystal oscillator 11 is connected to the third power supply P3 and is connected to the parallel capacitor circuit 12. The parallel capacitor circuit 12 includes a plurality of capacitors. One end of each capacitor is connected to the power supply terminal VDD, and the other end of each capacitor is grounded. The plurality of capacitors includes a first capacitor C1, and the capacitance value of the first capacitor C1 is greater than or equal to 10 microfarads (μF).
[0028] With the parallel capacitor circuit 12, the active crystal oscillator circuit 10 of the present invention can filter out the pulses that may be generated by the third power supply P3 connected to the power supply terminal VDD of the active crystal oscillator 11. In particular, the setting of the relatively large first capacitor C1 with a capacitance value of not less than 10 microfarads can slow down the rising edge of the power supply of the active crystal oscillator 11, thereby increasing the response time of the active crystal oscillator 11, and effectively avoiding the situation that the active crystal oscillator 11 is mis-triggered to generate a sine wave when there are pulses in the third power supply P3.
[0029] In a preferred embodiment, the plurality of capacitors further includes a second capacitor C2 and a third capacitor C3. Among them, the capacitance value of the first capacitor C1 is 10 microfarads, the capacitance value of the second capacitor C2 is 0.01 microfarads, and the capacitance value of the third capacitor C3 is 1 microfarad.
[0030] Further, the power supply terminal VDD of the active crystal oscillator 11 is connected to the third power supply P3 through a chip ferrite bead FB (Ferrite Bead). The chip ferrite bead FB can suppress high-frequency noise and spike interference on the power transmission line, and can also absorb electrostatic pulses.
[0031] Of course, the ground terminal GND of the active crystal oscillator 11 is grounded, and the output terminal OUT of the active crystal oscillator 11 outputs a clock signal OSC_CLK. The output terminal OUT can provide a reference clock signal OSC_CLK_REF through a fourth resistor R4.
[0032] In a specific embodiment, the active crystal oscillator circuit 10 of the present invention is an active crystal oscillator circuit on a computer motherboard. The gate of the first NMOS transistor Q1 is connected to an embedded controller or a complex programmable logic device on the computer motherboard, and receives an enable control signal from the embedded controller or the complex programmable logic device; the first power supply P1 and the second power supply P2 are the P3V3SB power supply of the computer motherboard, and the third power supply P3 is the P3V3 power supply of the computer motherboard.
[0033] In a preferred embodiment, the first NMOS transistor Q1 and the second NMOS transistor Q2 can be implemented by a double N-channel MOS transistor, and its model can be L2N7002DW1T1G; the active crystal oscillator 11 can be an active crystal oscillator with the model OSC4-3225; the chip bead FB can be a chip bead with the model FB0603; but not limited thereto.
[0034] In summary, the active crystal oscillator circuit with an anti-mis-triggering function of the present invention forms an isolation circuit between the external control module and the active crystal oscillator by using the first NMOS transistor and the second NMOS transistor, isolating the enable control signal sent by the external control module to the active crystal oscillator from the enable terminal of the active crystal oscillator, so that even if the external control module sends pulses erroneously, it will not affect the active crystal oscillator. In this way, when the electronic device to which the active crystal oscillator circuit of the present invention is applied is powered on or starts up, the pulses erroneously sent by the control module of the active crystal oscillator, such as an embedded controller or a complex programmable logic device, will not affect the active crystal oscillator, and will not mis-trigger the active crystal oscillator to generate a sine wave with a microsecond or millisecond time, thereby effectively preventing the enable terminal of the active crystal oscillator from being mis-triggered, ensuring that the active crystal oscillator can provide an accurate clock signal, and guaranteeing system stability.
[0035] Moreover, the active crystal oscillator circuit of the present invention is also connected with a parallel capacitor circuit at the power supply terminal of the active crystal oscillator. At least one capacitor with a capacitance of not less than 10 microfarads is provided in the parallel capacitor circuit to slow down the rising edge of the power supply of the active crystal oscillator and increase the response time of the active crystal oscillator, so as to filter out the pulses that may be generated by the third power supply connected to the power supply terminal of the active crystal oscillator, effectively avoiding the situation that the active crystal oscillator is mis-triggered to generate a sine wave when there are pulses in the third power supply. In this way, when the electronic device to which the active crystal oscillator circuit of the present invention is applied is powered on or starts up, the pulses erroneously sent by the third power supply will not affect the active crystal oscillator, and will not mis-trigger the active crystal oscillator to generate a sine wave with a microsecond or millisecond time, thereby effectively preventing the power supply terminal of the active crystal oscillator from being mis-triggered, ensuring that the active crystal oscillator can provide an accurate clock signal, and guaranteeing system stability.
[0036] It can be seen that the active crystal oscillator circuit of the present invention can not only prevent the enable terminal of the active crystal oscillator from being mis-triggered, but also prevent the power supply terminal of the active crystal oscillator from being mis-triggered, thereby effectively preventing the active crystal oscillator from being mis-triggered.
[0037] As described above, for those of ordinary skill in the art, various corresponding changes and deformations can be made according to the technical solutions and technical concepts of the present invention, and all these changes and deformations should fall within the protection scope of the claims of the present invention.
Claims
1. An active crystal oscillator circuit with an anti-mis-triggering function, characterized in that, It includes an active crystal oscillator, a first NMOS transistor, a second NMOS transistor, a first resistor, a second resistor, and a third resistor. Among them, the gate of the first NMOS transistor is used to receive the enable control signal provided by an external control module for the active crystal oscillator. The source of the first NMOS transistor is grounded, and the drain of the first NMOS transistor is connected to a first power supply through the first resistor. The gate of the second NMOS transistor is connected to the drain of the first NMOS transistor, and the source of the second NMOS transistor is grounded. The second resistor and the third resistor are connected in series between a second power supply and ground, and the drain of the second NMOS transistor is connected between the second resistor and the third resistor and is connected to the enable terminal of the active crystal oscillator.
2. The active crystal oscillator circuit according to claim 1, wherein The active crystal oscillator circuit further includes a parallel capacitor circuit. The power supply terminal of the active crystal oscillator is connected to a third power supply and is connected to the parallel capacitor circuit. The parallel capacitor circuit includes a plurality of capacitors. One end of each capacitor is connected to the power supply terminal, and the other end of each capacitor is grounded. And the plurality of capacitors include a first capacitor, and the capacitance value of the first capacitor is greater than or equal to 10 microfarads.
3. The active crystal oscillator circuit according to claim 2, wherein The plurality of capacitors further include a second capacitor and a third capacitor. The capacitance value of the second capacitor is 0.01 microfarads, the capacitance value of the third capacitor is 1 microfarad, and the capacitance value of the first capacitor is 10 microfarads.
4. The active crystal oscillator circuit according to claim 2 or 3, characterized in that, The power supply terminal of the active crystal oscillator is connected to the third power supply through a chip bead.
5. The active crystal oscillator circuit according to claim 1, wherein, The third resistor is connected between the second resistor and ground, and the resistance value of the third resistor is 10 times the resistance value of the second resistor.
6. The active crystal oscillator circuit according to claim 2, wherein The active crystal oscillator circuit is an active crystal oscillator circuit on a computer motherboard. The first power supply and the second power supply are the P3V3SB power supply of the computer motherboard, and the third power supply is the P3V3 power supply of the computer motherboard.
7. The active crystal oscillator circuit according to claim 1 or 6, characterized in that The gate of the first NMOS transistor is connected to an embedded controller or a complex programmable logic device.
8. The active crystal oscillator circuit according to claim 1, wherein The first NMOS transistor and the second NMOS transistor are implemented by a dual N-channel MOS transistor.
9. The active crystal oscillator circuit according to claim 1, characterized in that, The ground terminal of the active crystal oscillator is grounded, and the output terminal of the active crystal oscillator outputs a clock signal.