Pulse voltage generating device and test system

Abstract

The utility model discloses a pulse voltage generating device and a test system. The pulse voltage generating device comprises a main control unit which comprises a first control end and a second control end; the first control end sends a first control signal, and the second control end sends a second control signal; the first pulse voltage generation circuit comprises a first input end, a first trigger end and a first output end, the first input end is connected with a first power supply voltage, and the first trigger end is connected to the first control end; when the first trigger end receives a first control signal, the first output end outputs a first pulse voltage; the second pulse voltage generation circuit comprises a second input end, a second trigger end and a second output end, the second input end is connected with a second power supply voltage, and the second trigger end is connected with the second control end; and when the second trigger end receives a second control signal, the second output end outputs a second pulse voltage. According to the pulse voltage generating device provided by the utility model, two kinds of pulse voltage can be flexibly controlled to be output.

Description

Technical Field

[0001] This application relates to the technical field of pulse detection, and particularly to a pulse voltage generating device and a test system. Background Art

[0002] Currently, the rated operating voltage of most MCUs is generally between 2.5V and 5.5V. Excessive voltage will affect the normal operation of the MCU and even cause damage to the MCU, while too low voltage will affect the driving ability of the peripheral circuits of the MCU.

[0003] An MCU generally serves as the control core of a system. When the power supply in the system is interfered with, it may generate a pulse voltage that briefly exceeds 5.5V. In addition, in some circuits containing inductors, when the current in the inductor changes (such as the operation of a switching power supply), the inductor will maintain the continuity of its current, resulting in the generation of a negative reverse pulse voltage, thus affecting the power supply of the MCU.

[0004] Therefore, it is necessary to develop a test system to simulate the change of the power supply voltage outside the MCU and test the ultimate tolerance of the MCU to the power supply voltage. Summary of the Invention

[0005] In order to solve the problems of testing the ultimate tolerance of the MCU to the power supply voltage and simulating the power supply voltage outside the MCU, the present utility model provides a pulse voltage generating device and a test system. The specific technical solutions are as follows:

[0006] The present utility model provides a pulse voltage generating device, including:

[0007] A main control unit, including a first control end and a second control end; the first control end sends a first control signal, and the second control end sends a second control signal.

[0008] A first pulse voltage generating circuit, including a first input end, a first trigger end, and a first output end. The first input end is connected to a first power supply voltage, and the first trigger end is connected to the first control end; when the first control signal is received at the first trigger end, the first output end outputs a first pulse voltage.

[0009] A second pulse voltage generating circuit, including a second input end, a second trigger end, and a second output end. The second input end is connected to a second power supply voltage, and the second trigger end is connected to the second control end; when the second control signal is received at the second trigger end, the second output end outputs a second pulse voltage.

[0010] Specifically, the pulse voltage generating device provided by the present utility model controls the first pulse voltage generating circuit and the second pulse voltage generating circuit respectively through the main control unit, realizes simulating the change of the power supply voltage outside the MCU, and outputs a negative first pulse voltage and a positive second pulse voltage.

[0011] In one embodiment, the first pulse voltage generating circuit includes:

[0012] A first trigger sub - circuit, including a third input terminal, a first input terminal, and a first trigger terminal; the first input terminal is connected to a first power supply voltage, and the third input terminal is connected to a third power supply voltage; when receiving the first power supply voltage and the third power supply voltage, under the action of a first control signal, the first trigger sub - circuit selectively outputs the third power supply voltage as the first trigger voltage.

[0013] A first oscillator sub - circuit, including a first output terminal, which outputs a first pulse voltage when receiving the first trigger voltage.

[0014] Specifically, the first trigger sub - circuit provided by the present utility model activates the first oscillator sub - circuit by controlling the output first trigger voltage, and then outputs the first pulse voltage.

[0015] In one embodiment, the first trigger sub - circuit is a first analog switch chip or a first level conversion circuit.

[0016] Specifically, the first analog switch chip or the first level conversion circuit provided by the present utility model functions to connect and disconnect signals between the first trigger sub - circuit and the first oscillator sub - circuit.

[0017] In one embodiment, the first oscillator sub - circuit includes:

[0018] A first MOS transistor, the source of the first MOS transistor is connected to the first power supply voltage; the drain of the first MOS transistor forms the first output terminal; the gate of the first MOS transistor is connected to the first trigger sub - circuit, and when the first trigger voltage is received at the gate of the first MOS transistor, the drain of the first MOS transistor outputs the first pulse voltage.

[0019] A first resistor, one end is grounded and the other end is connected to the drain of the first MOS transistor.

[0020] A second resistor, used to generate a gate - source voltage to turn on the first MOS transistor, one end is connected to the gate of the first MOS transistor and the other end is connected to the first power supply voltage.

[0021] Specifically, the first oscillator sub - circuit provided by the present utility model uses the first resistor and the second resistor to reduce oscillation to avoid causing circuit failures and protect the drain - source of the first MOS transistor from being broken down.

[0022] In one embodiment, the second pulse voltage generating circuit includes:

[0023] The second trigger sub-circuit includes a fourth input terminal, a second input terminal, and a second trigger terminal; the second input terminal is connected to a second power supply voltage, and the fourth input terminal is connected to a third power supply voltage; when receiving the second power supply voltage and the third power supply voltage, under the action of a second control signal, the second trigger sub-circuit selectively outputs the third power supply voltage as the second trigger voltage.

[0024] The second oscillation sub-circuit includes a second output terminal, and when receiving the second trigger voltage, the second oscillation sub-circuit outputs a second pulse voltage.

[0025] Specifically, the second trigger sub-circuit provided by the present utility model activates the second oscillation sub-circuit by controlling the output second trigger voltage, and then outputs a second pulse voltage.

[0026] In one embodiment, the second trigger sub-circuit is a second analog switch chip or a second level conversion circuit.

[0027] Specifically, the second analog switch chip or the second level conversion circuit provided by the present utility model functions to connect and disconnect signals between the second trigger sub-circuit and the second oscillation sub-circuit.

[0028] In one embodiment, the second oscillation sub-circuit includes:

[0029] A second MOS transistor, the source of the second MOS transistor is connected to the second power supply voltage; the drain of the second MOS transistor forms the second output terminal; the gate of the second MOS transistor is connected to the second trigger sub-circuit, and when the second trigger voltage is received at the gate of the second MOS transistor, the drain of the second MOS transistor outputs a second pulse voltage.

[0030] A third resistor, one end is grounded, and the other end is connected to the drain of the second MOS transistor.

[0031] A fourth resistor is used to generate a gate-source voltage to turn on the second MOS transistor, one end is connected to the gate of the second MOS transistor, and the other end is used to connect to the second power supply voltage.

[0032] Specifically, the second oscillation sub-circuit provided by the present utility model uses the third resistor and the fourth resistor to reduce oscillation to avoid causing circuit faults and protect the drain-source of the second MOS transistor from being broken down.

[0033] In one embodiment, the pulse voltage generating device further includes:

[0034] A power supply voltage conversion circuit is connected to the second power supply voltage and converts and outputs a first power supply voltage and a third power supply voltage; the second power supply voltage is a positive voltage, the first power supply voltage is a negative voltage, and the third power supply voltage is the conduction voltage of the MOS transistor; the first pulse voltage is a negative pulse voltage, and the second pulse voltage is a positive pulse voltage.

[0035] Specifically, the power supply voltage conversion circuit provided by the present utility model realizes the input of a power supply voltage and the output of multiple voltage values to meet the requirements of the pulse voltage generating device for generating pulse voltages.

[0036] The present utility model also provides a pulse voltage testing system, which includes the pulse voltage generating device described in any one of the above items. The pulse voltage testing system further includes:

[0037] The MCU to be tested, to which the first pulse voltage or the second pulse voltage is output through the pulse voltage generating device, for testing the voltage tolerance range of the MCU to be tested.

[0038] Specifically, the pulse voltage testing system provided by the present utility model simulates the change of the power supply voltage outside the MCU to realize the testing of the voltage tolerance range of the MCU.

[0039] In one embodiment, the pulse voltage testing system further includes:

[0040] A power supply circuit, connected to the pulse voltage generating device, for providing a second power supply voltage to the pulse voltage generating device.

[0041] Through the pulse voltage generating device and testing system provided by the present utility model, the change of the power supply voltage outside the MCU is simulated, and two different pulse voltages are output to test the ultimate tolerance of the MCU to the power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0043] Figure 1 is the application block diagram of the pulse voltage generating device according to an embodiment of the present utility model;

[0044] Figure 2 is the structural schematic diagram of the pulse voltage generating device according to an embodiment of the present utility model;

[0045] Figure 3 is the circuit diagram of the first pulse voltage generating circuit of the pulse voltage generating device according to an embodiment of the present utility model;

[0046] Figure 4 is the simplified schematic diagram of the first analog switch chip of the pulse voltage generating device according to an embodiment of the present utility model;

[0047] Figure 5 It is a circuit diagram of the second pulse voltage generation circuit of the pulse voltage generation device according to an embodiment of the present utility model;

[0048] Reference numerals in the attached drawings: power supply circuit - 100, pulse voltage generation device - 200, MCU to be tested - 300, main control unit - 210, first pulse voltage generation circuit - 220, first trigger sub - circuit - 221, first oscillator sub - circuit 222, second pulse voltage generation circuit - 230, second trigger sub - circuit 231, second oscillator sub - circuit 232, and power supply voltage conversion circuit - 240. Detailed implementation manners

[0049] In the following description, for the purpose of illustration rather than limitation, specific details such as specific system structures and technologies are set forth in order to provide a thorough understanding of the embodiments of the present application. However, those skilled in the art should clearly understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well - known systems, devices, circuits, and methods are omitted to avoid unnecessary details from obscuring the description of the present application.

[0050] It should be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, wholes, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups.

[0051] It should also be further understood that the term "and / or" as used in the specification and appended claims of the present application refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0052] In addition, in the description of the present application, terms such as "first", "second", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific implementation manners of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings, and other implementation manners can also be obtained.

[0054] MCU (Microcontroller Unit), integrates the central processing unit (CPU), memory (RAM), input / output interface (I / O), etc. all on "a single integrated circuit". Generally, the MCU needs to work within a specified operating voltage range. Too high voltage will affect the normal operation of the MCU or even burn out the MCU, and too low voltage will affect the driving ability of the peripheral circuits of the MCU and even cause the peripheral circuits to fail to work properly.

[0055] Currently, it is usually to use a pulsed voltage to test the limit operating range of the MCU for the supply voltage. A pulse generally refers to an electrical impulse (voltage or current) signal that is short and has a limited amplitude in electronic technology. Its main characteristic parameters are waveform, amplitude, width, and repetition frequency. Compared with a continuous signal, a pulse signal is a discrete signal that occurs in an extremely short time and then quickly returns to zero or the baseline level.

[0056] In the prior art, a waveform generator is mainly used to generate pulses. A waveform generator is a device that can provide electrical signals of various frequencies, waveforms, and output levels. When measuring the amplitude characteristics, frequency characteristics, transmission characteristics, and other electrical parameters of various telecommunication systems or telecommunication devices, the waveform generator is used as a test signal source or excitation source.

[0057] However, a waveform generator generally can only generate one type of pulsed voltage, and the load-carrying capacity of the waveform generator is poor. Generally, it can only output a current of a few milliamperes, and the generated waveform cannot be flexibly controlled. For example, a positive waveform generator generates positive pulses (pulses with an amplitude higher than the reference voltage of 0V), a negative waveform generator generates negative pulses (pulses with an amplitude lower than the reference voltage of 0V), and the amplitude of the negative voltage generated by the negative voltage waveform generator is relatively low.

[0058] Therefore, the present utility model proposes a pulsed voltage generating device, which can flexibly control the output of two different types of pulsed voltages through a first pulsed voltage generating circuit and a second pulsed voltage generating circuit.

[0059] The present utility model also proposes a pulsed voltage testing system, including a pulsed voltage generating device, a power supply circuit, and an MCU to be tested. By connecting a power supply voltage to the pulsed voltage generating device through the power supply circuit, the first pulsed voltage or the second pulsed voltage is output to the MCU to be tested, and the tolerance of the supply voltage of the MCU to be tested is tested.

[0060] In an embodiment of the present utility model, the present utility model provides a pulsed voltage testing system, including a power supply circuit 100, a pulsed voltage generating device 200, and an MCU 300 to be tested.

[0061] A power supply circuit 100 is connected to a pulse voltage generating device 200 and is used to supply a power supply voltage to the pulse voltage generating device 200.

[0062] A MCU 300 to be tested has a first pulse voltage or a second pulse voltage output to the MCU 300 to be tested through the pulse voltage generating device 200, and the voltage tolerance range of the MCU 300 to be tested is tested.

[0063] Specifically, when testing the voltage tolerance range of the MCU 300 to be tested, the pulse voltage generating device 200 can accurately output a first pulse voltage or a second pulse voltage with a specific amplitude and width to the MCU 300 to be tested according to the test requirements. In this way, various voltage shock situations that the MCU 300 to be tested may encounter in the actual working environment can be simulated, so as to evaluate its voltage tolerance ability.

[0064] During the test process, the output voltage of the pulse voltage generating device 200 will perform periodic positive and negative pulse excitations on the MCU 300 according to a predetermined test program. The parameters of these pulse signals, such as amplitude, width, and frequency, can be preset according to the technical specifications and test standards of the MCU 300 to be tested. For example, some test standards may require the pulse voltage to simulate the overvoltage situation caused by the failure of the generator regulator or the voltage shock during auxiliary starting.

[0065] A flashing light program can be run in the MCU 300 to be tested, and the added pulse can be visually detected through the flashing light to see if it has any effect on the MCU 300 to be tested. If the added positive and negative pulse voltages have no effect on the MCU 300 to be tested, the light will flash normally; if there is an effect, the light will go out.

[0066] Through a pulse voltage test system proposed by the present utility model, it is possible to test the MCU to be tested without building a hardware test platform again, with high test efficiency, and various power interference situations can be simulated.

[0067] For an embodiment of the present utility model, please refer to Figure 1 , the present utility model provides a pulse voltage generating device 200, which includes a main control unit 210, a first pulse voltage generating circuit 220, a second pulse voltage generating circuit 230, and a power supply voltage conversion circuit 240.

[0068] The main control unit 210 includes a first control end and a second control end; the first control end sends a first control signal, and the second control end sends a second control signal.

[0069] The first pulse voltage generation circuit 220 includes a first input terminal, a first trigger terminal, and a first output terminal. The first input terminal is connected to a first power supply voltage, and the first trigger terminal is connected to a first control terminal. When a first control signal is received at the first trigger terminal, the first output terminal outputs a first pulse voltage.

[0070] The second pulse voltage generation circuit 230 includes a second input terminal, a second trigger terminal, and a second output terminal. The second input terminal is connected to a second power supply voltage, and the second trigger terminal is connected to a second control terminal. When a second control signal is received at the second trigger terminal, the second output terminal outputs a second pulse voltage.

[0071] The power supply voltage conversion circuit 240 is connected to the second power supply voltage and converts and outputs the first power supply voltage and the third power supply voltage. The second power supply voltage is a positive voltage, the first power supply voltage is a negative voltage, and the third power supply voltage is the conduction voltage of the MOS transistor. The first pulse voltage is a negative pulse voltage, and the second pulse voltage is a positive pulse voltage.

[0072] Specifically, the first control signal output by the main control unit 210 is used to control the first pulse voltage generation circuit 220, and the second control signal is used to control the second pulse voltage generation circuit 230. The control signal may be a level change or a specific time sequence, and is used to control when the two pulse voltage generation circuits generate pulse voltages. Among them, the main control unit 210 may be a single-chip microcomputer, an FPGA (Field Programmable Gate Array), a PLC (Programmable Logic Controller), etc.

[0073] The interval time and response time of the control signals sent through the first control terminal and the second control terminal of the main control unit 210 can be used to control the frequency and duty cycle of the output first pulse voltage and second pulse voltage. It is also possible to realize the timed generation of pulse voltages by combining the main control unit 210 with a timer / timing instruction.

[0074] The power supply voltage conversion circuit 240 can convert the input power supply voltage and adjust the output to the working voltages suitable for the first pulse voltage generation circuit 220 and the second pulse voltage generation circuit 230 (i.e., the first power supply voltage and the second power supply voltage). For example, the DCDC power supply module in the power supply voltage conversion circuit 240 can convert the input 12V power supply voltage into a 5V power supply voltage and a -5V power supply voltage. The DC regulated power supply module in the power supply voltage conversion circuit 240 can directly output a 12V power supply voltage.

[0075] The first pulse voltage generation circuit 220 receives a first power supply voltage from the power supply voltage conversion circuit 240 through its first input terminal. The first power supply voltage can ensure that the first pulse voltage generation circuit 220 can obtain the necessary electrical energy to generate a negative pulse. Similarly, the second pulse voltage generation circuit 230 receives a second power supply voltage from the power supply voltage conversion circuit 240 through its second input terminal, ensuring that the second pulse voltage generation circuit 230 can obtain the necessary electrical energy to generate a positive pulse.

[0076] The main control unit 210 sends a first control signal to activate the pulse generation mechanism of the first pulse voltage generation circuit 220. The first trigger terminal triggers the generation of a negative pulse by detecting the presence or absence or level change of the first control signal, and can respond quickly to the first control signal, thereby controlling the generation of the first pulse voltage (i.e., the negative pulse voltage). Similarly, the action mechanism of the second control signal on the second pulse voltage generation circuit 230 is the same and will not be elaborated here.

[0077] The pulse voltage generating device 200 provided by the present utility model realizes flexible control of the output of negative pulse voltage and positive pulse voltage through the control of the main control unit 210 over the first pulse voltage generation circuit 220 and the second pulse voltage generation circuit 230, solves the problems of low negative voltage amplitude and poor load-carrying capacity of the negative voltage waveform generator; and also uses fewer discrete components to form the device, which is more cost-saving compared to the finished waveform generator.

[0078] In an embodiment of the present utility model, based on the above embodiment, please refer to Figure 2 , the first pulse voltage generation circuit 220 may include a first trigger sub-circuit 221 and a first oscillation sub-circuit 222, and the second pulse voltage generation circuit 230 may include a second trigger sub-circuit 231 and a second oscillation sub-circuit 232.

[0079] The first trigger sub-circuit 221 includes a third input terminal, a first input terminal, and a first trigger terminal; the first input terminal is connected to the first power supply voltage, and the third input terminal is connected to the third power supply voltage; when receiving the first power supply voltage and the third power supply voltage, under the action of the first control signal, the first trigger sub-circuit 221 selects to output the third power supply voltage as the first trigger voltage.

[0080] The first oscillation sub-circuit 222 includes a first output terminal. When receiving the first trigger voltage, the first oscillation sub-circuit 222 outputs the first pulse voltage.

[0081] The second trigger sub-circuit 231 includes a fourth input terminal, a second input terminal, and a second trigger terminal; the second input terminal is connected to a second power supply voltage, and the fourth input terminal is connected to a third power supply voltage; when receiving the second power supply voltage and the third power supply voltage, under the action of the second control signal, the second trigger sub-circuit 231 selects to output the third power supply voltage and uses it as the second trigger voltage.

[0082] The second oscillation sub-circuit 232 includes a second output terminal. When receiving the second trigger voltage, the second oscillation sub-circuit 232 outputs a second pulse voltage.

[0083] Specifically, the first input terminal and the first trigger terminal of the first trigger sub-circuit 221 are the first input terminal and the first trigger terminal of the first pulse voltage generating circuit 220. The first trigger sub-circuit 221 is a key component of the first pulse voltage generating circuit 220 and is used to receive the power supply voltage and respond to the first control signal to generate the first trigger voltage that activates the first oscillation sub-circuit 222.

[0084] Under the action of the high and low levels of the first control signal, the first trigger sub-circuit 221 selects and switches between the first power supply voltage and the third power supply voltage for output, and uses the output third power supply voltage as the first trigger voltage of the first trigger sub-circuit 221.

[0085] The output terminal of the first oscillation sub-circuit 222 is the output terminal of the first pulse voltage generating circuit 220. Once the first oscillation sub-circuit 222 receives the first trigger voltage, the oscillator inside the first oscillation sub-circuit 222 starts to work, generates periodic voltage fluctuations through a positive feedback mechanism, and these voltage fluctuations are shaped and amplified within the circuit, finally forming the first pulse voltage (negative pulse voltage) with specific characteristics.

[0086] The second input terminal and the second trigger terminal of the second trigger sub-circuit 231 are the second input terminal and the second trigger terminal of the second pulse voltage generating circuit 230. Under the action of the high and low levels of the second control signal, the second trigger sub-circuit 231 selects and switches between the second power supply voltage and the third power supply voltage for output, and uses the third power supply voltage to activate the second oscillation sub-circuit 232. Finally, based on the second control signal, the second oscillation sub-circuit 232 forms the second pulse voltage (positive pulse voltage) with specific characteristics.

[0087] The working mechanisms of the second trigger sub-circuit 231 and the second oscillation sub-circuit 232 are the same as those of the first trigger sub-circuit 221 and the first oscillation sub-circuit 222 described above, and will not be elaborated here.

[0088] The pulse voltage generating device 200 provided by the present utility model constitutes a first pulse voltage generating circuit 220 for outputting a negative pulse voltage and a second pulse voltage generating circuit 230 for outputting a positive pulse voltage through two trigger sub - circuits and two oscillator sub - circuits respectively, ensuring that the generation of the pulse voltage can be accurately activated after receiving a control signal.

[0089] In an embodiment of the present utility model, the first power supply voltage value and the third power supply voltage value can be flexibly adjusted and are provided by the power supply voltage conversion circuit 240. In the present utility model, the models and quantities of the analog switch chips and resistors are not limited. Please refer to Figure 3 , the first trigger sub - circuit 221 is the first analog switch chip U1.

[0090] Specifically, the first input terminal (NC terminal) of the first analog switch chip U1 is connected to the first power supply voltage VEE (negative voltage), the third input terminal (NO terminal) is connected to the third power supply voltage GND, and the first trigger terminal (IN terminal) is connected to the first control terminal of the main control unit 210. When the first control signal PA0 is not received at the first trigger terminal (IN terminal), the first common terminal (i.e., the COM terminal) is connected to the first input terminal (NC terminal), and the first power supply voltage VEE connected to the first input terminal is output; when the first control signal PA0 is received at the first trigger terminal (IN terminal), the first common terminal (COM terminal) is connected to the third input terminal (NO terminal), and the first trigger voltage (i.e., the voltage connected to the NO terminal) is output.

[0091] A positive power supply voltage VCC1 is connected to the V + terminal of the first analog switch chip U1, and V_ is connected to the first power supply voltage VEE. The V + terminal and the V_ terminal are used to supply power to the first analog switch chip U1. For example, when the first power supply voltage is - 5V and the positive power supply voltage is + 5V, a working range of - 5 to + 5 can be provided for the first analog switch chip U1.

[0092] For example, as Figure 4 shown is the simplified schematic diagram of the first analog switch chip U1. The first input terminal (NC terminal, i.e., the normally - closed terminal) is connected to the negative voltage, the third input terminal (NO terminal, i.e., the normally - open terminal) is grounded. When there is no trigger signal, the first common terminal (COM terminal) is connected to the first input terminal (NC terminal); by outputting high and low levels through the first trigger terminal (IN terminal), the first input terminal and the third input terminal are switched back and forth, so that the first common terminal (COM terminal) has a voltage change.

[0093] In addition, in this embodiment, the third power supply voltage can be the ground voltage or can be adjusted to the conduction voltage that can turn on the first MOS transistor. If the first analog switch chip U1 is not used, a level conversion circuit can also be used for substitution.

[0094] Please refer to Figure 3, the first oscillator circuit 222 includes:

[0095] The first MOS transistor Q1, the source of the first MOS transistor Q1 is connected to the first power supply voltage VEE; the drain of the first MOS transistor Q1 forms a first output terminal; the gate of the first MOS transistor Q1 is connected to the first trigger sub-circuit 221. When the first trigger voltage is received at the gate of the first MOS transistor Q1, the drain of the first MOS transistor Q1 outputs a first pulse voltage.

[0096] The first resistor R1, one end is grounded and the other end is connected to the drain of the first MOS transistor Q1.

[0097] The second resistor R2 is used to generate a gate-source voltage to turn on the first MOS transistor Q1, one end is connected to the gate of the first MOS transistor Q1, and the other end is connected to the first power supply voltage VEE.

[0098] Specifically, in the first oscillator circuit 222, the source of the first MOS transistor Q1 is connected to the first power supply voltage VEE, the gate of the first MOS transistor Q1 is connected to the COM terminal of the first analog switch chip U1, and the drain of the first MOS transistor Q1 outputs a first pulse voltage. In this embodiment, the first MOS transistor Q1 can be an N-MOS transistor. Using other types of components can also achieve the same effect, such as replacing it with an ordinary bipolar transistor.

[0099] When the first control signal PA0 is received, the COM terminal and the NO terminal of the first analog switch chip U1 are connected, a voltage difference is formed between the gate and the source of the first MOS transistor Q1, and the first MOS transistor Q1 is turned on between the source and the drain to realize the output of the first pulse voltage (negative pulse voltage).

[0100] The first end of the first resistor R1 is grounded and the second end is connected to the drain of the first MOS transistor Q1. The first end of the second resistor R2 is connected to the gate of the first MOS transistor Q1 and the second end is connected to the first power supply voltage VEE. Through the first resistor R1 and the second resistor R2, the oscillation is reduced to avoid causing circuit failures and protect the drain-source of the first MOS transistor Q1 from being broken down.

[0101] Moreover, the adjustment of the amplitude of the first pulse voltage can be obtained by dividing the first power supply voltage VEE connected through the first resistor R1.

[0102] Through the first analog switch chip provided by the present invention, on the one hand, the on-off of the first MOS transistor can be controlled, and on the other hand, the effect of level conversion can be achieved, so as to flexibly control the amplitude of the output first pulse voltage.

[0103] In an embodiment of the present utility model, the second power supply voltage value can be flexibly adjusted and is provided by the power supply voltage conversion circuit 240. In the present utility model, the models and quantities of the analog switch chips and resistors are not limited. Please refer to Figure 5 and the second trigger sub - circuit 231 is the second analog switch chip U2.

[0104] Specifically, the second power supply voltage VCC2 input to the power supply voltage conversion circuit 240 can be directly output, or the voltage value can be adjusted before output. The amplitude of the second pulse voltage generated by the second pulse voltage generation circuit 230 is the second power supply voltage VCC2.

[0105] The second input terminal (NC terminal) of the second analog switch chip U2 is connected to the second power supply voltage VCC2 (positive voltage), the fourth input terminal (NO terminal) is connected to the third power supply voltage GND, and the second trigger terminal (IN terminal) is connected to the second control terminal of the main control unit 210. When the second control signal PA1 is not received at the second trigger terminal (IN terminal), the second common terminal (i.e., the COM terminal) is connected to the second input terminal (NC terminal), and the second power supply voltage VCC2 connected to the second input terminal is output; when the second control signal PA1 is received at the second trigger terminal (IN terminal), the second common terminal (COM terminal) is connected to the fourth input terminal (NO terminal), and the second trigger voltage (i.e., the voltage connected to the NO terminal) is output.

[0106] The second power supply voltage VCC2 is connected to the V + terminal of the second analog switch chip U2, and V_ is connected to the third power supply voltage GND. The V + terminal and the V_ terminal are used to supply power to the second analog switch chip U2. When the second power supply voltage is +12V, a working range of 0V to +12V can be provided for the second analog switch chip U2.

[0107] In addition, in this embodiment, the third power supply voltage can be the ground voltage, or can be adjusted to the conduction voltage that can turn on the second MOS transistor. If the second analog switch chip U2 is not used, a level conversion circuit can be used for replacement.

[0108] Please refer to Figure 5 and the second oscillation sub - circuit 232 includes:

[0109] The second MOS transistor Q2, the source electrode of the second MOS transistor Q2 is connected to the second power supply voltage VCC2; the drain electrode of the second MOS transistor Q2 forms the second output terminal; the gate electrode of the second MOS transistor Q2 is connected to the second trigger sub - circuit 231. When the second trigger voltage is received at the gate electrode of the second MOS transistor Q2, the drain electrode of the second MOS transistor Q2 outputs the second pulse voltage.

[0110] The third resistor R3, one end is grounded and the other end is connected to the drain electrode of the second MOS transistor Q2.

[0111] The fourth resistor R4 is used to generate a gate-source voltage to turn on the second MOS transistor Q2. One end is connected to the gate of the second MOS transistor Q2, and the other end is used to access the second power supply voltage VCC2.

[0112] Specifically, in the second oscillator circuit 232, the source of the second MOS transistor Q2 is connected to the second power supply voltage VCC2, the gate of the second MOS transistor Q2 is connected to the COM terminal of the second analog switch chip U2, and the drain of the second MOS transistor Q2 outputs a first pulse voltage. In this embodiment, the second MOS transistor Q2 can be a P-MOS transistor, and the same effect can also be achieved by using other types of components, such as replacing it with an ordinary bipolar transistor.

[0113] When the second control signal PA1 is received, the COM terminal and the NO terminal of the second analog switch chip U2 are connected, a voltage difference is formed between the gate and the source of the second MOS transistor Q2, and the second MOS transistor Q2 is turned on between the source and the drain to realize the output of the second pulse voltage (positive pulse voltage).

[0114] The first end of the third resistor R3 is grounded, and the second end is connected to the drain of the second MOS transistor Q2. The first end of the fourth resistor R4 is connected to the gate of the second MOS transistor Q2, and the second end is connected to the second power supply voltage VCC2. Through the third resistor R3 and the fourth resistor R4, oscillation is reduced to avoid causing circuit failures, and the drain-source of the second MOS transistor Q2 is protected from being broken down.

[0115] Through the second analog switch chip provided by the present utility model, on the one hand, the on-off of the second MOS transistor can be controlled, and on the other hand, the effect of level conversion can be achieved, so as to flexibly control the amplitude of the output first pulse voltage.

[0116] In the above embodiments, the descriptions of the various embodiments have their own focuses. For the parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0117] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this application.

[0118] The unit described as a separation component may or may not be physically separated, and the component displayed as a unit may or may not be a physical unit, that is, it may be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0119] In addition, each functional unit in various embodiments of the present application may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0120] It should be noted that the above embodiments can be freely combined according to needs. The above are only the preferred embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A pulse voltage generating device, characterized in that, Comprising: A main control unit, including a first control terminal and a second control terminal; the first control terminal sends a first control signal, and the second control terminal sends a second control signal; A first pulse voltage generation circuit, including a first input terminal, a first trigger terminal, and a first output terminal, the first input terminal is connected to a first power supply voltage, and the first trigger terminal is connected to the first control terminal; when the first trigger terminal receives the first control signal, the first output terminal outputs a first pulse voltage; A second pulse voltage generation circuit, including a second input terminal, a second trigger terminal, and a second output terminal, the second input terminal is connected to a second power supply voltage, and the second trigger terminal is connected to the second control terminal; When the second trigger terminal receives the second control signal, the second output terminal outputs a second pulse voltage.

2. The pulse voltage generating device according to claim 1, wherein The first pulse voltage generation circuit includes: A first trigger sub-circuit, including a third input terminal, the first input terminal, and the first trigger terminal; the first input terminal is connected to the first power supply voltage, and the third input terminal is connected to a third power supply voltage; when receiving the first power supply voltage and the third power supply voltage, under the action of the first control signal, the first trigger sub-circuit selectively outputs the third power supply voltage as the first trigger voltage; A first oscillation sub-circuit, including the first output terminal, when receiving the first trigger voltage, the first oscillation sub-circuit outputs the first pulse voltage.

3. The pulse voltage generating device according to claim 2, wherein: The first trigger sub-circuit is a first analog switch chip or a first level conversion circuit.

4. The pulse voltage generating device according to claim 2, characterized in that, The first oscillation sub-circuit includes: A first MOS transistor, the source electrode of the first MOS transistor is connected to the first power supply voltage; the drain electrode of the first MOS transistor forms the first output terminal; the gate electrode of the first MOS transistor is connected to the first trigger sub-circuit, when the first trigger voltage is received at the gate electrode of the first MOS transistor, the drain electrode of the first MOS transistor outputs the first pulse voltage; A first resistor, one end is grounded, and the other end is connected to the drain electrode of the first MOS transistor; A second resistor, used to generate a gate-source voltage to turn on the first MOS transistor, one end is connected to the gate electrode of the first MOS transistor, and the other end is connected to the first power supply voltage.

5. The pulse voltage generating device according to any one of claims 2 to 4, characterized in that, The second pulse voltage generation circuit includes: A second trigger sub-circuit, including a fourth input terminal, the second input terminal, and the second trigger terminal; the second input terminal is connected to the second power supply voltage, and the fourth input terminal is connected to the third power supply voltage; when receiving the second power supply voltage and the third power supply voltage, under the action of the second control signal, the second trigger sub-circuit selectively outputs the third power supply voltage as the second trigger voltage; A second oscillation sub-circuit, including the second output terminal, when receiving the second trigger voltage, the second oscillation sub-circuit outputs the second pulse voltage.

6. The pulse voltage generating device according to claim 5, wherein: The second trigger sub-circuit is a second analog switch chip or a second level conversion circuit.

7. The pulse voltage generating device according to claim 5, wherein The second oscillator circuit includes: A second MOS transistor, the source of the second MOS transistor is connected to the second power supply voltage; the drain of the second MOS transistor forms the second output terminal; the gate of the second MOS transistor is connected to the second trigger sub-circuit, and when the second trigger voltage is received at the gate of the second MOS transistor, the drain of the second MOS transistor outputs the second pulse voltage; A third resistor, one end grounded and the other end connected to the drain of the second MOS transistor; A fourth resistor for generating a gate-source voltage to turn on the second MOS transistor, one end connected to the gate of the second MOS transistor and the other end for connecting to the second power supply voltage.

8. The pulse voltage generating device according to claim 5, characterized in that, It further includes: A power supply voltage conversion circuit, connected to the second power supply voltage, and converting and outputting the first power supply voltage and the third power supply voltage from the second power supply voltage; The second power supply voltage is a positive voltage, the first power supply voltage is a negative voltage, and the third power supply voltage is the conduction voltage of the MOS transistor; The first pulse voltage is a negative pulse voltage and the second pulse voltage is a positive pulse voltage.

9. A pulse voltage test system, characterized in that, Including the pulse voltage generating device according to any one of claims 1 to 8, it further includes: A MCU to be tested, outputting the first pulse voltage or the second pulse voltage to the MCU to be tested through the pulse voltage generating device to test the voltage tolerance range of the MCU to be tested.

10. The pulse voltage test system according to claim 9, wherein It further includes: A power supply circuit, connected to the pulse voltage generating device, for providing the second power supply voltage to the pulse voltage generating device.

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