AI edge computing device based on rail transit

Abstract

The embodiment of the utility model provides AI edge computing equipment based on rail transit. The AI edge computing equipment based on the rail transit comprises a Xavier module, a power supply module, an MCU module and an interface module. The power supply end of the Xavier module is electrically connected with the output end of the power supply module; the control end of the Xavier module is electrically connected with the control end of the MCU module; the input and output end of the Xavier module is electrically connected with the interface module. Through cooperative work among the Xavier module, the power supply module, the MCU module and the interface module, AI and edge calculation can be combined and applied to rail transit, a Xavier high-performance core module can be supported, and performance and universality are improved.

Description

Technical Field

[0001] The embodiments of this specification relate to the field of artificial intelligence technology, and particularly to AI edge computing devices based on rail transit. Background Art

[0002] The development of AI edge computing devices benefits from advanced solutions such as the NVIDIA Jetson platform, which provides support for real-time data processing and AI algorithms in fields such as intelligent traffic management and autonomous robots. These technologies show strong application potential in reducing traffic congestion, improving traffic safety, and realizing precision agriculture.

[0003] The AI edge computing device based on rail transit is a device that combines artificial intelligence and edge computing technologies, aiming to improve the intelligent level and computing efficiency of the rail transit system. However, the current AI edge computing devices have fewer interfaces, insufficient integration and performance, and there is an urgent need for a better solution. Utility Model Content

[0004] In view of this, the embodiments of this specification provide an AI edge computing device based on rail transit to solve the technical defects existing in the prior art.

[0005] According to the first aspect of the embodiments of this specification, an AI edge computing device based on rail transit is provided, including: a Xavier module, a power supply module, an MCU module, and an interface module;

[0006] The power supply terminal of the Xavier module is electrically connected to the output terminal of the power supply module;

[0007] The control terminal of the Xavier module is electrically connected to the control terminal of the MCU module;

[0008] The input / output terminal of the Xavier module is electrically connected to the interface module.

[0009] In a possible implementation manner, the power supply module includes a 12V power supply unit and a 5V power supply unit;

[0010] The power supply terminal of the Xavier module includes a first power supply terminal and a second power supply terminal;

[0011] The first power supply terminal of the Xavier module is electrically connected to the 12V power supply unit;

[0012] The second power supply terminal of the Xavier module is electrically connected to the 5V power supply unit.

[0013] In a possible implementation manner, the MCU module includes a single-chip microcomputer unit;

[0014] The model of the single-chip microcomputer unit is HC32L170FAUA.

[0015] In a possible implementation, the interface module includes a storage interface, a network interface, a camera interface, a display interface, and a debugging interface.

[0016] In a possible implementation, the storage interface includes an M.2 M key interface and an SATA3.0 interface.

[0017] In a possible implementation, the network interface includes an Ethernet interface and a wireless network interface.

[0018] In a possible implementation, the camera interface includes a GMSL2 interface.

[0019] In a possible implementation, the display interface includes an HDMI interface.

[0020] In a possible implementation, the debugging interface includes a debugging serial port, a CAN interface, and a USB interface.

[0021] In a possible implementation, it further includes a fan interface and an indicator light interface.

[0022] The embodiments of this specification provide an AI edge computing device based on rail transit. The AI edge computing device based on rail transit includes an Xavier module, a power supply module, an MCU module, and an interface module; the power supply terminal of the Xavier module is electrically connected to the output terminal of the power supply module; the control terminal of the Xavier module is electrically connected to the control terminal of the MCU module; the input / output terminal of the Xavier module is electrically connected to the interface module. Through the collaborative work among the above-mentioned Xavier module, power supply module, MCU module, and interface module, the combination of AI and edge computing can be realized and applied to rail transit, and it can support the Xavier high-performance core module, improving performance and universality. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic structural diagram of an AI edge computing device based on rail transit provided by an embodiment of this specification;

[0024] Figure 2 is a 12V power supply circuit diagram of an AI edge computing device based on rail transit provided by an embodiment of this specification;

[0025] Figure 3 is a 5V power supply circuit diagram of an AI edge computing device based on rail transit provided by an embodiment of this specification;

[0026] Figure 4 is an MCU circuit diagram of an AI edge computing device based on rail transit provided by an embodiment of this specification. Detailed implementation manners

[0027] In the following description, numerous specific details are set forth in order to provide a thorough understanding of this specification. However, this specification can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the connotation of this specification. Therefore, this specification is not limited by the specific implementations disclosed below.

[0028] The terms used in one or more embodiments of this specification are for the purpose of describing specific embodiments only and are not intended to limit one or more embodiments of this specification. The singular forms "a" and "the" used in one or more embodiments of this specification and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used in one or more embodiments of this specification refers to and includes any or all possible combinations of one or more of the associated listed items.

[0029] It should be understood that although the terms first, second, etc. may be used in one or more embodiments of this specification to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of one or more embodiments of this specification, the first may also be referred to as the second, and similarly, the second may also be referred to as the first. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".

[0030] First, the noun terms related to one or more embodiments of this specification are explained.

[0031] A microcontroller unit (MCU), also known as a single-chip microcomputer or a microcontroller.

[0032] Artificial Intelligence, abbreviated as AI in English.

[0033] See Figure 1 , Figure 1 shows a structural diagram of an AI edge computing device based on rail transit provided according to an embodiment of this specification, specifically including a Xavier module, a power supply module, an MCU module, and an interface module. The power supply terminal of the Xavier module is electrically connected to the output terminal of the power supply module; the control terminal of the Xavier module is electrically connected to the control terminal of the MCU module; the input / output terminal of the Xavier module is electrically connected to the interface module.

[0034] In a possible implementation, the power supply module includes a 12V power supply unit and a 5V power supply unit; the power supply terminals of the Xavier module include a first power supply terminal and a second power supply terminal; the first power supply terminal of the Xavier module is electrically connected to the 12V power supply unit; the second power supply terminal of the Xavier module is electrically connected to the 5V power supply unit.

[0035] Specifically, the power input adopts a D-SUB interface form. To meet the requirements of the complex electromagnetic environment of rail transit, sub-miniature resistors, fuses, TVS, two-stage common-mode filtering, and reverse connection prevention designs are carried out for the input power supply part. Since the core of the Xavier module requires two groups of power supplies, namely MV_5V and HV_12V power supplies. See Figure 2 , for the 12V power supply of the core module, 1 DC / DC power chip (SIC438BED) is used to output DC_12V power; see Figure 3 , for the 5V power supply of the core module, 1 DC / DC power chip (SIC438BED) is used to output DC_12V power. After being controlled by a MOS tube, DC_12V outputs DC_12V_HV for the HV power supply of the module. After being controlled by a MOS tube, the DC_5V power supply outputs DV_5V_MV for the MV power supply of the module.

[0036] Furthermore, 1 DC / DC power chip, which can be SIC438BED, is used to output 5V power to supply power to each USB interface. 1 DC / DC power chip, which can be SiC437BED-T1-GE3, is used to output 3.3V power to supply power to the chips inside the carrier board. 1 LDO power chip, which can be BL8028CB5TR, is used to output 1.8V power to supply power to the chips inside the carrier board.

[0037] In a possible implementation, the MCU module includes a single-chip microcomputer unit; the model of the single-chip microcomputer unit is HC32L170FAUA.

[0038] Specifically, see Figure 4 , the model of the single-chip microcomputer can be HC32L170FAUA. Using the single-chip microcomputer and referring to the power domain timing of the NVIDIA Xavier module, the power-on and power-off timing control of the Xavier module is carried out. At the same time, the functions of the power button, reset button, and flashing button are also realized by using the programmable characteristics of the single-chip microcomputer.

[0039] Furthermore, the interface module includes a storage interface, a network interface, a camera interface, a display interface, and a debugging interface.

[0040] In a possible implementation, the storage interface includes an M.2 M key interface and a SATA3.0 interface.

[0041] Specifically, the hard disk interface converts the PCIe x 1 high-speed signal of the Xavier module into a standard SATA signal. The conversion chip uses 88SE9171A2 to implement the SATA expansion function. The SATA3.0 interface adopts a standard interface that combines power / signal lines, and the model is LD2122F-S04T3. To be compatible with different SATA hard disks, in addition to the SATA high-speed signal, the interface is also configured with 12VDC and 5VDC power supplies. Among them, the 12V power supply uses APL3548QBI for current limiting and output control, and the 5V power supply uses APL3553ABI-TRG for current limiting and output control.

[0042] Furthermore, the M.2 M key interface adopts a PCIe x 4 high-speed working mode, which can adapt to SSD hard disks with different rates and capacities, and can expand the hard disk storage space according to the size of the business software.

[0043] In a possible implementation, the network interface includes an Ethernet interface and a wireless network interface.

[0044] Specifically, due to the limited resources of the Xavier module, in order to expand 4 independent gigabit Ethernet ports, a PCIe bridge chip is used in the design to expand 1 PCIe x 4 bus signal into 4 independent PCIe x 1 signals, and then through a PCIe to Ethernet port chip, 4 independent gigabit Ethernet ports are realized. At the same time, the PCIe Ethernet port chip supports network PTP and gPTP synchronization functions.

[0045] Preferably, the expansion chip in the PCIe bridge chip expansion circuit uses PI7C9X2G608GPCNJEX. The conversion chip in the PCIe to Ethernet port circuit uses the KTI225IT chip of INTEL.

[0046] The wireless network interface includes a miniPCIe interface, which is used to expand a 4G module with GPS positioning function. The interface is standard with a high-speed PCIe signal of PCIe x 1 and a USB2.0 signal, and can be externally connected to a 4G module. The SIM card interface matched by this interface supports NANO SIM cards, and the interface signals are all protected against ESD.

[0047] The wireless network interface includes an M.2 B Key interface, which is used to expand a 5G module. The interface is standard with a PCIe x 1 signal and a USB3.0 signal, and supports connecting two 5G modules through the PCIe interface and the USB interface. The SIM card on this interface supports NANOSIM cards and is used to adapt to 5G modules.

[0048] In a possible implementation, the camera interface includes a GMSL2 interface.

[0049] Specifically, the GMSL2 interface uses the MIPI-CSI signal of the Xavier module and is externally connected to the camera by converting it into a GMSL2 high-speed signal through a chip. Preferably, the MAX96712GTB chip of Maxim Integrated can be used to support 4-channel GMSL2 inputs simultaneously and convert them into CSI signals for the Xavier module to collect camera images.

[0050] Furthermore, the GMSL2 interface adopts a standard interface form, and each interface can supply power to the GMSL camera externally at the same time, with the power supply range being 9 - 12VDC. The current limiting chip TCKE712BNL is used to limit the output current of the interface.

[0051] In a possible implementation, the display interface includes an HDMI interface.

[0052] The standard HDMI interface is used for system display, and the interface model is HDMI-019F. ESD protection is applied to the data, clock, DDC signal, power supply, etc. of the HDMI interface. At the same time, a common mode filter and impedance matching resistors are connected in series on the high-speed signal path to reduce the reflection of electromagnetic signals, minimize signal radiation as much as possible, and ensure that the radiation emission characteristics of the device meet the requirements of the EMC specification.

[0053] In a possible implementation, the debugging interface includes a debugging serial port, a CAN interface, and a USB interface.

[0054] Specifically, for the convenience of user debugging, the debugging serial port signal is converted into a USB2.0 signal in the design, and the standard Type-C interface form is used, which is convenient for users to use when debugging the module. The Type-C interface uses MC-142P, and ESD protection is applied to the signal on the interface.

[0055] Furthermore, by using the SPI bus signal of the Xavier module, after being converted by the SPI to CAN transceiver signal and adding a CAN protocol chip, the function of converting from the SPI signal to the CAN bus signal is realized. Preferably, the MCP2518FDT chip is used to realize the function of converting from SPI to CAN transceiver signals. The CAN bus PHY chip uses SIT1044T / 3, and bus matching resistors and related protection circuits are added to realize 2 independent CAN buses.

[0056] Furthermore, it may also include two USB3.0 interfaces: one standard Type-A with the interface model number U30-04D, which supports two-way standard USB2.0 / USB3.0 / USB3.1 signals. At the same time, the interface can use APL3553ABI-TRG to control the output of 5V power current. According to the 5V / 2A output standard required by the technical specifications, a current-limiting resistor is set for the output of this chip to meet the 2A output requirement.

[0057] Furthermore, it may also include a USB2.0 interface: The Micro USB interface uses the native USB2.0 signal of the Xavier module and is connected to the Type-C interface through a common-mode filter and ESD protection devices, facilitating users to perform the flashing operation. At the same time, a current-limiting chip (SY6280) is used to set the output current of the interface, and according to the USB2.0 standard output protocol, the output current threshold is set to 0.5A.

[0058] In a possible implementation, it also includes a fan interface and an indicator light interface.

[0059] Specifically, since the module consumes a large amount of power and generates a high temperature during the operation of the large model algorithm. If the module is not cooled down, CPU / GPU frequency reduction will occur, resulting in a problem of reduced computing performance. There are two modes of module heat dissipation. In addition to the passive heat dissipation method of the machine case itself, the module is actively cooled through the fan interface at the same time. The fan interface is equipped with a PWM control signal and a TACH feedback signal, and the interface signals are all subjected to ESD processing. When the fan works, according to the temperature of the module's CPU / GPU, the rotation speed of the fan is controlled through the PWM pulse width modulation signal, so as to achieve the maximum benefit of cooling the module in the minimum power consumption mode. The interface signals are all subjected to ESD protection processing.

[0060] Furthermore, this device supports six LED indicator lights, facilitating users to observe the status of the system. The indicator lights can all be controlled to be lit or extinguished through the GPIO of the Xavier module, thus representing different system statuses.

[0061] Furthermore, the device supports the functions of two buttons: power and flashing. Anti-jitter designs with ESD protection are designed for the button circuits.

[0062] An embodiment of this specification provides an AI edge computing device based on rail transit. The AI edge computing device based on rail transit includes a Xavier module, a power supply module, an MCU module, and an interface module. The power supply terminal of the Xavier module is electrically connected to the output terminal of the power supply module. The control terminal of the Xavier module is electrically connected to the control terminal of the MCU module. The input / output terminal of the Xavier module is electrically connected to the interface module. Through the collaborative work among the above-mentioned Xavier module, power supply module, MCU module, and interface module, the combination of AI and edge computing can be realized and applied to rail transit, and the high-performance core module of Xavier can be supported, improving the performance and universality.

[0063] It should be noted that for the foregoing method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the embodiments of this specification are not limited by the described action sequence, because according to the embodiments of this specification, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the embodiments of this specification.

[0064] In the above embodiments, the descriptions of the various embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0065] The preferred embodiments of this specification disclosed above are only used to help explain this specification. The alternative embodiments do not describe all the details in detail, nor do they limit the present invention to the specific embodiments described. Obviously, according to the content of the embodiments of this specification, many modifications and changes can be made. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the embodiments of this specification, so that those skilled in the art can well understand and utilize this specification. This specification is only limited by the claims and their full scope and equivalents.

Claims

1. An AI edge computing device based on rail transit, characterized in that It includes a Xavier module, a power supply module, an MCU module, and an interface module; The power supply terminal of the Xavier module is electrically connected to the output terminal of the power supply module; The control terminal of the Xavier module is electrically connected to the control terminal of the MCU module; The input / output terminal of the Xavier module is electrically connected to the interface module; The power supply module includes a 12V power supply unit and a 5V power supply unit; The power supply terminals of the Xavier module include a first power supply terminal and a second power supply terminal; The first power supply terminal of the Xavier module is electrically connected to the 12V power supply unit; The second power supply terminal of the Xavier module is electrically connected to the 5V power supply unit; The MCU module includes a single-chip microcomputer unit; The model of the single-chip microcomputer unit is HC32L170FAUA; The interface module includes a storage interface, a network interface, a camera interface, a display interface, and a debugging interface; The storage interface includes an M.2 M key interface and a SATA3.0 interface; The network interface includes an Ethernet interface and a wireless network interface; The camera interface includes a GMSL2 interface; The display interface includes an HDMI interface; The debugging interface includes a debugging serial port, a CAN interface, and a USB interface; It also includes a fan interface and an indicator light interface; Among them, the Ethernet interface includes a PCIe bridge chip, the PCIe bridge chip includes PCIe x 4 bus signals, the PCIe x 4 bus signals include 4 independent PCIe x 1 signals, and each of the independent signals is electrically connected to a PCIe to network port chip in one-to-one correspondence.

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