ESD protection circuit and driving chip

Abstract

The utility model discloses an ESD protection circuit and a driving chip, the ESD protection circuit is applied to the driving circuit, and the ESD protection circuit comprises a protection trigger unit which is connected between an input voltage and a reference potential and is used for generating a trigger signal based on the input voltage; the ESD current discharge unit is connected between the power supply voltage and the reference potential, the ESD current discharge unit is switched on when the trigger signal is at the first level, and the ESD current discharge unit is switched off when the trigger signal is at the second level. According to the utility model, based on the body diode of the MOS tube of the driving unit, and in combination with the ESD protection circuit provided by the utility model, when the discharge device releases the ESD current to the ground potential, an ESD current discharge path from the discharge device to the ground potential is established, and the control end voltage of the discharge device is clamped at the set voltage, so that the discharge device is prevented from being broken down and damaged, and the service life of the discharge device is prolonged. And the reliability of the chip is improved. The ESD protection circuit is suitable for a multi-channel driving circuit, the driving circuits of all channels share one group of ESD protection circuit, and the chip area is saved.

Description

Technical Field

[0001] The utility model belongs to the technical field of integrated circuits, and particularly relates to an ESD protection circuit and a driving chip. Background Art

[0002] Electrostatic discharge (ESD) is a process in which a large amount of static charges are transferred between objects with different electric potentials in a short time.

[0003] As Figure 1 shown, the driving circuit includes a driving Buffer and a discharge device NLDMOS transistor. When an electrostatic discharge occurs between the output port OUTX of the driving circuit and the ground potential AGND, the gate voltage of the discharge device NLDMOS transistor will be raised, which will cause the NLDMOS transistor to be broken down and burned out, thus leading to chip failure.

[0004] The prior art uses a Clamp circuit as shown in Figure 1 to pull down the gate voltage of the NLDMOS transistor to solve the problem that the gate voltage of the NLDMOS transistor is raised. However, for a multi-channel driving circuit, if each channel of the driving circuit uses a set of independent Clamp circuits to pull down and control the gate of the NLDMOS transistor, a large chip area will be occupied.

[0005] Therefore, in view of the above technical problems, it is necessary to provide an ESD protection circuit and a driving chip. Summary of the Utility Model

[0006] The purpose of the utility model is to provide an ESD protection circuit and a driving chip, which can solve the problem that the discharge device is broken down and damaged during the electrostatic discharge process with a smaller circuit area.

[0007] In order to achieve the above purpose, the technical solution provided by a specific embodiment of the utility model is as follows:

[0008] An ESD protection circuit is applied to a driving circuit, and the driving circuit includes a discharge device and a driving unit; wherein,

[0009] The first end of the discharge device is connected to a reference potential, the second end of the discharge device is connected to an output port, and the second end of the discharge device is directly or indirectly connected to an input voltage;

[0010] The driving unit is connected between a power supply voltage and a reference potential, and the driving unit is respectively connected to an input port and the control end of the discharge device;

[0011] The ESD protection circuit includes:

[0012] A protection trigger unit is connected between an input voltage and a reference potential and is used to generate a trigger signal based on the input voltage;

[0013] An ESD current discharge unit is connected between a power supply voltage and a reference potential. When the trigger signal is at a first level, the ESD current discharge unit is turned on, and when the trigger signal is at a second level, the ESD current discharge unit is turned off.

[0014] In one or more embodiments of the present invention, the driving unit includes an inverter, a first MOS transistor, and a second MOS transistor; wherein,

[0015] The input terminal of the inverter is connected to an input port, and the output terminal of the inverter is connected to the control terminals of the first MOS transistor and the second MOS transistor;

[0016] The first terminal of the first MOS transistor is connected to the reference potential, and the second terminal of the first MOS transistor is connected to the control terminal of the discharge device;

[0017] The first terminal of the second MOS transistor is connected to the power supply voltage, and the second terminal of the second MOS transistor is connected to the control terminal of the discharge device.

[0018] In one or more embodiments of the present invention, the second MOS transistor is a PMOS transistor, and a body diode is formed between the first terminal and the second terminal of the second MOS transistor;

[0019] The first terminal of the body diode is connected to the control terminal of the discharge device, and the second terminal of the body diode is connected to the power supply voltage.

[0020] In one or more embodiments of the present invention, the protection trigger unit includes a first capacitor and a first resistor; wherein,

[0021] The first terminal of the first capacitor is connected to the input voltage, the second terminal of the first capacitor is connected to the first terminal of the first resistor and generates a trigger signal, and the second terminal of the first resistor is connected to the reference potential.

[0022] In one or more embodiments of the present invention, the ESD current discharge unit includes a third MOS transistor;

[0023] The control terminal of the third MOS transistor is connected to the protection trigger unit and receives the trigger signal. The first terminal of the third MOS transistor is connected to the reference potential, and the second terminal of the third MOS transistor is connected to the power supply voltage.

[0024] In one or more embodiments of the present invention, the third MOS transistor is an NMOS transistor; the first level is a high level, and the third MOS transistor is turned on; the second level is a low level, and the third MOS transistor is turned off.

[0025] In one or more embodiments of the present utility model, the ESD protection circuit further includes a Zener diode, the first end of the Zener diode is connected to a reference potential, and the second end of the Zener diode is connected to an ESD current discharge unit.

[0026] In one or more embodiments of the present utility model, the discharge device includes an NLDMOS transistor;

[0027] The control end of the NLDMOS transistor is connected to a driving unit, the first end of the NLDMOS transistor is connected to a reference potential, the second end of the NLDMOS transistor is connected to an output port, and the second end of the NLDMOS transistor is directly or indirectly connected to an input voltage.

[0028] The technical solution provided by another specific embodiment of the present utility model is as follows:

[0029] A driving chip, the driving chip includes a driving circuit and the ESD protection circuit.

[0030] In one or more embodiments of the present utility model, the driving chip includes one or more groups of driving circuits, and the driving chip includes one group of ESD protection circuits.

[0031] Compared with the prior art, the ESD protection circuit and the driving chip of the present utility model, based on the body diode of the PMOS transistor of the driving unit, combined with the ESD protection circuit proposed by the present utility model, when the discharge device releases the ESD current to the ground potential, an ESD current discharge path from the control end of the discharge device to the ground potential is established, and the control end voltage of the discharge device is clamped at a set voltage, avoiding the discharge device from being broken down and damaged, and improving the reliability of the chip.

[0032] The circuit structure of the present utility model is simple, and the working state of the discharge device is detected through a protection trigger unit with a simple RC structure, realizing the state monitoring of the discharge device.

[0033] The present utility model is applicable to a multi-channel driving circuit, and the driving circuits of all channels share one group of ESD protection circuits, greatly saving the chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0035] Figure 1Schematic diagram of a driving circuit in the prior art;

[0036] Figure 2 Schematic diagram of the ESD protection circuit in Embodiment 1 of the present invention;

[0037] Figure 3 Schematic diagram of the driving chip in Embodiment 2 of the present invention. Detailed implementation manners

[0038] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0039] "Coupled", "connected", or "linked" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conduction medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include a connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as a connection through circuits or components such as switches and follower circuits. In addition, in the present invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity, or order between these technical features.

[0040] Embodiment 1:

[0041] As Figure 2 shown, the ESD protection circuit 20 in this embodiment is applied to the driving circuit 10, where the driving circuit 10 includes a discharger device 12 and a driving unit 11.

[0042] The first end of the discharger device 12 is connected to the reference potential AGND, the second end of the discharger device 12 is connected to the output port OUTX, and the second end of the discharger device 12 is directly or indirectly connected to the input voltage COM. The reference potential AGND in this embodiment may be a ground potential, and the input voltage COM is a high voltage, such as 50V.

[0043] The driving unit 11 is connected between the power supply voltage AVDD and the reference potential AGND. The driving unit 11 is respectively connected to the input port INX and the control end of the discharge device 12. It can be understood that the input port INX in this embodiment is the input port of the driving circuit, which receives the driving signal for controlling the driving circuit; the output port OUTX in this embodiment is the output port of the driving circuit. In this embodiment, electrostatic discharge is performed on the ground potential AGND through the output port OUTX of the driving circuit, and the ESD current is discharged to the ground potential AGND through the discharge device 12.

[0044] Further, the discharge device 12 in this embodiment includes an NLDMOS transistor (N-Lateral Double Diffused Metal Oxide Semiconductor), and the NLDMOS transistor is a high-voltage transistor. The control end of the NLDMOS transistor is connected to the driving unit 11, the first end of the NLDMOS transistor is connected to the reference potential AGND, the second end of the NLDMOS transistor is connected to the output port OUTX, and the second end of the NLDMOS transistor is directly or indirectly connected to the input voltage COM.

[0045] In this embodiment, the first end of the NLDMOS transistor is the source electrode, the second end is the drain electrode, and the control end is the gate electrode.

[0046] The driving unit 11 in this embodiment includes an inverter INV, a first MOS transistor M1, and a second MOS transistor M2.

[0047] The input end of the inverter INV is connected to the input port INX, and the output end of the inverter INV is connected to the control ends of the first MOS transistor M1 and the second MOS transistor M2.

[0048] The first end of the first MOS transistor M1 is connected to the reference potential AGND, and the second end of the first MOS transistor M1 is connected to the control end of the discharge device 12, that is, the control end of the NLDMOS transistor.

[0049] The first end of the second MOS transistor M2 is connected to the power supply voltage AVDD, and the second end of the second MOS transistor M2 is connected to the control end of the discharge device 12, that is, the control end of the NLDMOS transistor. The power supply voltage AVDD in this embodiment is 5V.

[0050] It can be understood that the first MOS transistor M1 and the second MOS transistor M2 in this embodiment form an inverter, and are cascaded with the previous-stage inverter INV to form a driving unit. In other embodiments, more inverter structures can also be cascaded between the inverter INV and the first MOS transistor M1 and the second MOS transistor M2 to improve the driving ability to meet the set driving ability requirements. In this embodiment, the first ends of the first MOS transistor M1 and the second MOS transistor M2 are source electrodes, the second ends are drain electrodes, and the control ends are gate electrodes.

[0051] Further, the first MOS transistor M1 in this embodiment is an NMOS transistor, and the second MOS transistor M2 is a PMOS transistor. A body diode D1 is formed between the first end and the second end of the second MOS transistor M2. The first end of the body diode D1 is connected to the control end of the discharge device 12, and the second end of the body diode D1 is connected to the power supply voltage AVDD. Among them, the power of the second MOS transistor M2 is relatively large, so the corresponding body diode D1 is relatively large.

[0052] Further, the driving circuit 10 in this embodiment further includes a freewheeling diode D2. The first end of the freewheeling diode D2 is connected to the second end of the discharge device 12, that is, the second end of the NLDMOS transistor, and the second end of the freewheeling diode D2 is connected to the input voltage COM. The freewheeling diode D2 can transfer this part of the energy to the input voltage COM node during ESD energy release, so that the protection trigger unit 21 can detect the energy change, and then identify whether the driving circuit 10 is in the normal working state or the electrostatic discharge state.

[0053] As Figure 2 shown, the ESD protection circuit 20 in this embodiment includes a protection trigger unit 21 and an ESD current discharge unit 22.

[0054] The protection trigger unit 21 is connected between the input voltage COM and the reference potential AGND, and is used to generate a trigger signal S1 based on the input voltage COM.

[0055] Specifically, the protection trigger unit 21 includes a first capacitor C1 and a first resistor R1. The first end of the first capacitor C1 is connected to the input voltage COM, the second end of the first capacitor C1 is connected to the first end of the first resistor R1 and generates a trigger signal S1, and the second end of the first resistor R1 is connected to the reference potential AGND.

[0056] The protection trigger unit 21 is used to detect the signal on the input voltage COM by relying on frequency detection, so as to identify whether the drive circuit is in a normal working state or an electrostatic discharge state. When the drive circuit 10 is in a normal working state, the input voltage COM is low-frequency, and the protection trigger unit 21 generates a trigger signal S1 with a low level. When the drive circuit 10 is in an electrostatic discharge state, the high-frequency and fast-power-on ESD signal will be transmitted to the input voltage COM, and then detected by the protection trigger unit 21. The protection trigger unit 21 generates a trigger signal S1 with a high level.

[0057] By reasonably selecting the values of the first capacitor C1 and the first resistor R1, the size of the RC time constant is determined, so as to ensure the conduction duration of the ESD current discharge unit 22 and ensure the safe operation of the discharge device 12.

[0058] As Figure 2 shown, the ESD current discharge unit 22 is connected between the power supply voltage AVDD and the reference potential AGND. When the trigger signal S1 is at the first level, the ESD current discharge unit 22 is turned on. When the trigger signal S1 is at the second level, the ESD current discharge unit 22 is turned off.

[0059] The ESD current discharge unit 22 in this embodiment includes a third MOS transistor M3. The control end of the third MOS transistor M3 is connected to the protection trigger unit 21 and receives the trigger signal S1. The first end of the third MOS transistor M3 is connected to the reference potential AGND, and the second end of the third MOS transistor M3 is connected to the power supply voltage AVDD.

[0060] The third MOS transistor M3 in this embodiment is an NMOS transistor. The first level is a high level, and the third MOS transistor M3 is turned on. The second level is a low level, and the third MOS transistor M3 is turned off.

[0061] The ESD protection circuit 20 further includes a Zener diode Z1. The first end of the Zener diode Z1 is connected to the reference potential AGND, and the second end of the Zener diode Z1 is connected to the control end of the third MOS transistor M3. The Zener diode Z1 can protect the third MOS transistor M3 from being broken down by high voltage.

[0062] When the drive circuit 10 is in an electrostatic discharge state, the output port OUTX of the drive circuit will release charges to the ground potential AGND through the NLDMOS transistor. The control end (gate) of the NLDMOS transistor will be pulled high, and the high-frequency and fast-power-on ESD signal will be transmitted to the input voltage COM via the freewheeling diode D2. The protection trigger unit 21 will detect the frequency change of the input voltage COM.

[0063] When the voltage across the first capacitor C1 rises to the conduction threshold voltage of the third MOS transistor M3 (i.e., a high-level trigger signal S1 is generated), the third MOS transistor M3 conducts. Combining with the body diode D1 of the second MOS transistor M2, an ESD current discharge path is formed from the control terminal of the NLDMOS transistor - the first end of the body diode D1 - the second end of the body diode D1 - the third MOS transistor M3 - the ground potential AGND. Therefore, the voltage at the control terminal of the NLDMOS transistor is clamped at VD1 + Ids * Rds(ON), where VD1 is the conduction voltage drop of the body diode D1, Ids is the drain-source current when the third MOS transistor M3 conducts, and Rds(ON) is the resistance value between the drain and source of the third MOS transistor M3 when the third MOS transistor M3 conducts. It can be understood that the sizes of the second MOS transistor M2 and the third MOS transistor M3 can be determined according to the voltage value at which the control terminal of the NLDMOS transistor needs to be clamped.

[0064] Therefore, based on the ESD protection circuit proposed by the utility model, when the driving circuit is in an electrostatic discharge state, an ESD current discharge path is provided, and the control terminal of the NLDMOS transistor will be clamped at VD1 + Ids * Rds(ON), avoiding the NLDMOS transistor from being broken down and damaged. Moreover, the circuit structure of the utility model is simple, and the body diode of the PMOS transistor inherent in the driving circuit itself is utilized, greatly saving the circuit area.

[0065] Embodiment 2:

[0066] As Figure 3 shown, the driving chip in this embodiment includes a driving circuit 10 and an ESD protection circuit 20.

[0067] Furthermore, the driving chip includes one or more groups of driving circuits 10, and the driving chip includes one group of ESD protection circuits 20.

[0068] As Figure 3 shown, the utility model is applicable to multi-channel driving circuits, and the driving circuits of multiple channels share one group of ESD protection circuits 20. There is no need to separately set a CLAMP circuit for the driving circuit of each channel, saving the chip area and improving the reliability when the output port OUTX of the multi-channel driving circuit conducts electrostatic discharge ESD to the ground.

[0069] From the above technical solutions, it can be seen that the utility model has the following beneficial effects:

[0070] The utility model utilizes the body diode of the PMOS tube of the driving unit, and combines the ESD protection circuit proposed by the utility model. When the discharge device releases the ESD current to the ground, an ESD current discharge path from the control end of the discharge device to the ground potential is established, so that the control end voltage of the discharge device is clamped at the set voltage, thereby avoiding the discharge device from being broken down and damaged, and improving the reliability of the chip.

[0071] The utility model has a simple circuit structure, detects the working state of the discharge device through a protection trigger unit with a simple RC structure, and utilizes the freewheeling diode in the driving circuit to realize the state monitoring of the discharge device.

[0072] The utility model is suitable for a multi-channel driving circuit, and the driving circuits of all channels share a group of ESD protection circuits, thereby greatly saving chip area.

[0073] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be regarded as exemplary and non-restrictive from any point of view, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present invention. Any reference numeral in a claim should not be regarded as limiting the claim to which it relates.

[0074] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. An ESD protection circuit is applied to a driving circuit, and is characterized in that, The driving circuit includes a discharge device and a driving unit; wherein, A first end of the discharge device is connected to a reference potential, a second end of the discharge device is connected to an output port, and the second end of the discharge device is directly or indirectly connected to an input voltage; The driving unit is connected between a power supply voltage and the reference potential, and the driving unit is respectively connected to an input port and a control end of the discharge device; The ESD protection circuit includes: A protection trigger unit, connected between the input voltage and the reference potential, for generating a trigger signal based on the input voltage; An ESD current discharge unit, connected between the power supply voltage and the reference potential. When the trigger signal is at a first level, the ESD current discharge unit is turned on. When the trigger signal is at a second level, the ESD current discharge unit is turned off.

2. The ESD protection circuit according to claim 1, wherein The driving unit includes an inverter, a first MOS transistor, and a second MOS transistor; wherein, An input end of the inverter is connected to the input port, and an output end of the inverter is connected to control ends of the first MOS transistor and the second MOS transistor; A first end of the first MOS transistor is connected to the reference potential, and a second end of the first MOS transistor is connected to the control end of the discharge device; A first end of the second MOS transistor is connected to the power supply voltage, and a second end of the second MOS transistor is connected to the control end of the discharge device.

3. The ESD protection circuit according to claim 2, wherein The second MOS transistor is a PMOS transistor, and a body diode is formed between a first end and a second end of the second MOS transistor; A first end of the body diode is connected to the control end of the discharge device, and a second end of the body diode is connected to the power supply voltage.

4. The ESD protection circuit according to claim 1, wherein The protection trigger unit includes a first capacitor and a first resistor; wherein, A first end of the first capacitor is connected to the input voltage, a second end of the first capacitor is connected to a first end of the first resistor and generates a trigger signal, and a second end of the first resistor is connected to the reference potential.

5. The ESD protection circuit according to claim 1, wherein The ESD current discharge unit includes a third MOS transistor; A control end of the third MOS transistor is connected to the protection trigger unit and receives the trigger signal. A first end of the third MOS transistor is connected to the reference potential, and a second end of the third MOS transistor is connected to the power supply voltage.

6. The ESD protection circuit according to claim 5, wherein, The third MOS transistor is an NMOS transistor; The first level is a high level, and the third MOS transistor is turned on; the second level is a low level, and the third MOS transistor is turned off.

7. The ESD protection circuit according to claim 1, wherein The ESD protection circuit further includes a Zener diode. A first end of the Zener diode is connected to the reference potential, and a second end of the Zener diode is connected to the ESD current discharge unit.

8. The ESD protection circuit according to claim 1, wherein The discharge device includes an NLDMOS transistor; A control end of the NLDMOS transistor is connected to the driving unit. A first end of the NLDMOS transistor is connected to the reference potential, a second end of the NLDMOS transistor is connected to the output port, and the second end of the NLDMOS transistor is directly or indirectly connected to the input voltage.

9. A driving chip, characterized in that, The driving chip includes the driving circuit and the ESD protection circuit according to any one of claims 1 to 8.

10. The driving chip according to claim 9, wherein, The driving chip includes one or more groups of driving circuits, and the driving chip includes one group of ESD protection circuits.

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