Aerospace motor driving device based on FPGA (Field Programmable Gate Array)

Abstract

The utility model relates to an FPGA-based aerospace motor driving device, and relates to the technical field of driving control, and the device comprises a driver and a permanent magnet synchronous motor. The driver comprises a main control board, a driving board and a power supply board; the main control board comprises an FPGA chip, a serial port circuit, a refresh circuit and a direct-current power converter; the driving board comprises a driver main module, a driver standby module and a main and standby switching relay; each of the driver main module and the driver standby module comprises a power supply and soft start circuit, a drive circuit, a current acquisition circuit, an AD acquisition circuit, a differential transmission circuit, an isolation circuit and a relay switching circuit. According to the invention, the FPGA chip is adopted to drive the permanent magnet synchronous motor, so that the processing speed and the operational capability of the aerospace motor driving device can be improved; the service life of the aerospace motor driving device can be prolonged; and the reliability of the aerospace motor driving device can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of drive control technologies, and particularly to a space motor drive device based on an FPGA. Background Art

[0002] With the rapid development of aerospace technology, humanity's desire to explore the cosmic space has been increasing day by day. From satellites in Earth's orbit to spacecraft for deep space exploration, every space journey is accompanied by endless curiosity and exploration of the unknown world. In this process, the drive device, as an indispensable component on spacecraft, plays a crucial role. The drive device realizes precise observation of the target area and data analysis by accurately controlling the rotation speed and operating angle of motors, radars, telescopes, or other scientific instruments.

[0003] In order to meet the high requirements for accurate control of direction and attitude in space exploration, the role of the driver in the space motor drive device has become increasingly prominent. It is not only the brain of the motor drive device but also the key to achieving high-precision and high-efficiency motion control. In multiple fields such as industrial automation, medical equipment, and aerospace, the application of drivers is becoming increasingly widespread, and the quality of their performance is directly related to the stability and reliability of the entire system.

[0004] However, in the design of the driver of traditional motor drive devices, the selection of the main control processor often tends to be low-cost single-chip microcomputer and other solutions. Although these solutions meet the basic functional requirements to a certain extent, they have obvious deficiencies in terms of processing speed, power consumption, volume, and reliability. In the aerospace field, high reliability, high precision, high efficiency, and low power consumption are the basic requirements for drive controllers. Due to the limited processing speed of traditional single-chip microcomputer processors, it is difficult to meet the requirements of fast response and complex control algorithms; at the same time, the low reliability also limits their application on spacecraft.

[0005] Therefore, how to improve the reliability of the space motor drive device has become one of the technical problems to be urgently solved at the present stage. Summary of the Utility Model

[0006] To solve the above technical problems, the present disclosure provides a space motor drive device based on an FPGA.

[0007] The present disclosure provides a space motor drive device based on an FPGA, including a driver and a permanent magnet synchronous motor, where the driver is connected to the permanent magnet synchronous motor, and the driver is used to drive the permanent magnet synchronous motor;

[0008] The driver includes a main control board, a drive board, and a power supply board;

[0009] The main control board is connected to the drive board and the power supply board. The main control board includes an FPGA chip, a serial port circuit, a refresh circuit, and a DC power converter. The FPGA chip is connected to the serial port circuit, the refresh circuit, and the DC power converter;

[0010] The drive board is also connected to the power supply board. The drive board includes a main drive module, a backup drive module, and a main / backup switching relay. The main drive module is connected to the main control board, the power supply board, and the main / backup switching relay. The backup drive module is connected to the main control board, the power supply board, and the main / backup switching relay;

[0011] The main drive module and the backup drive module have the same structure, and both include a power supply and soft start circuit, a drive circuit, a current acquisition circuit, an AD acquisition circuit, a differential transmission circuit, an isolation circuit, and a relay switching circuit;

[0012] The power supply and soft start circuit is connected to the drive circuit. The drive circuit is also connected to the isolation circuit, the differential transmission circuit, and the current acquisition circuit. The current acquisition circuit is also connected to the AD acquisition circuit and the main / backup switching relay. The AD acquisition circuit is also connected to the differential transmission circuit and the main / backup switching relay. The relay switching circuit is connected to the isolation circuit and the main / backup switching relay.

[0013] Optionally, among them:

[0014] The refresh circuit includes a refresh chip and a FLASH chip. The refresh chip is respectively connected to the FPGA chip and the FLASH chip.

[0015] Optionally, among them:

[0016] The power supply board includes a soft start circuit and a DC power converter. The soft start circuit is connected to the DC power converter.

[0017] Optionally, among them:

[0018] The FPGA chip is an aerospace-grade FPGA chip.

[0019] Optionally, among them:

[0020] The permanent magnet synchronous motor includes two encoders. Both encoders are connected to the FPGA chip. At the same time, only one of the encoders works.

[0021] Optionally, among them:

[0022] The main and standby switching relay includes a magnetic latching relay and a motor connector. The magnetic latching relay is connected to the main drive module, the standby drive module, and the motor connector.

[0023] Optionally, where:

[0024] The main drive module and the standby drive module further include signal connectors, and the signal connectors are connected to the differential transmission circuit.

[0025] The technical solution provided by the embodiments of the present disclosure has the following advantages compared with the prior art:

[0026] The present disclosure provides a space motor drive device based on an FPGA. The space motor drive device includes a drive and a permanent magnet synchronous motor. The drive is connected to the permanent magnet synchronous motor and is used to drive the permanent magnet synchronous motor. The drive includes a main control board, a drive board, and a power supply board. The main control board is connected to the drive board and the power supply board. The main control board includes an FPGA chip, a serial port circuit, a refresh circuit, and a DC power converter. The drive board includes a main drive module, a standby drive module, and a main and standby switching relay. The main drive module and the standby drive module have the same structure and both include a power supply and soft start circuit, a drive circuit, a current acquisition circuit, an AD acquisition circuit, a differential transmission circuit, an isolation circuit, and a relay switching circuit. The present disclosure uses an FPGA chip to drive the permanent magnet synchronous motor, which is beneficial to improving the processing speed and computing power of the space motor drive device, thus facilitating meeting the requirements of complex control algorithms, and further facilitating improving the synchronous concurrency problem of controlling the motor movement and processing other work tasks in space. At the same time, the low power consumption characteristic of the FPGA chip is also beneficial to reducing the overall energy consumption of the space motor drive device, thus facilitating extending the service life of the space motor drive device. In addition, the high reliability of the FPGA chip is beneficial to being applied in scenarios with limited space and harsh environments such as space scanning devices, thus facilitating improving the high reliability of space scanning devices. By setting a refresh circuit, it is beneficial to perform online reconfiguration, reloading, and refreshing operations on the FPGA chip, thus facilitating improving the reliability and configuration flexibility of the drive. Also, by setting two completely identical drive modules and forming a cross-backup relationship, it is more beneficial to improving the reliability of the space motor drive device. Description of the Drawings

[0027] The drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure.

[0028] To more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0029] Figure 1 The figure shows a schematic diagram of a space motor drive device based on FPGA provided by an embodiment of the present disclosure;

[0030] Figure 2 The figure shows a schematic diagram of a drive board provided by an embodiment of the present disclosure;

[0031] Figure 3 The figure shows a connection schematic diagram of a drive circuit provided by an embodiment of the present disclosure;

[0032] Figure 4 The figure shows a schematic diagram of the principle of a drive chip provided by an embodiment of the present disclosure;

[0033] Figure 5 The figure shows a schematic diagram of a driver control system of a space motor drive device based on FPGA provided by an embodiment of the present disclosure;

[0034] Figure 6 The figure shows a connection schematic diagram of a driver control system of a space motor drive device based on FPGA provided by an embodiment of the present disclosure;

[0035] Figure 7 The figure shows a schematic diagram of the process of encoder switching provided by an embodiment of the present disclosure;

[0036] Figure 8 The figure shows a control schematic diagram of an FOC control module provided by an embodiment of the present disclosure;

[0037] Figure 9 The figure shows a schematic diagram of the process of a driver control method of a space motor drive device based on FPGA provided by an embodiment of the present disclosure;

[0038] Figure 10 The figure shows a control flowchart of a permanent magnet synchronous motor provided by an embodiment of the present disclosure. Detailed implementation manners

[0039] In order to more clearly understand the above objects, features and advantages of the present disclosure, the following will further describe the solutions of the present disclosure. It should be noted that, without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other.

[0040] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0041] The inventors found in their research that traditional drivers are often used in ground equipment, and the main control processors mainly use DSP (Digital Signal Processing), MCU (Micro Control Unit) and single-chip microcomputers, or use a system architecture that integrates DSP and CPLD (Complex Programmable Logic Device).

[0042] DSP, MCU and single-chip microcomputer collect motor speed and position information through encoders, and process current loop, speed loop and position loop at the same time. This architecture is affected by its peripherals and performance, and the control accuracy is limited and the power consumption is high. In addition, once the DSP and MCU are designed, it is difficult to change their functions and they cannot be updated in orbit.

[0043] DSP and CPLD integrated architecture, CPLD collects information such as the position and speed of the motor and transmits the data to DSP, DSP processes the current loop, speed loop and position loop according to the received data and control commands. However, the accuracy of this architecture is also limited, which is not conducive to the reliability of aerospace motor drive devices.

[0044] When the drive is used in aerospace motor drive devices, its working environment is relatively extreme and requires high-performance computing and processing capabilities, as well as relatively precise control capabilities, which requires the aerospace motor drive devices to have higher reliability.

[0045] Therefore, how to improve the reliability of aerospace motor drive devices has become one of the technical problems that need to be solved urgently at this stage.

[0046] Figure 1 FIG. 1 is a schematic diagram of an aerospace motor drive device based on FPGA provided in an embodiment of the present disclosure. Figure 2 FIG. 1 is a schematic diagram of a driving board provided in an embodiment of the present disclosure, please refer to FIG. Figure 1 and Figure 2 , the present disclosure provides an aerospace motor driving device 100 based on FPGA, including a driver 01 and a permanent magnet synchronous motor M, the driver 01 is connected to the permanent magnet synchronous motor M, and the driver 01 is used to drive the permanent magnet synchronous motor M;

[0047] The driver 01 includes a main control board 10, a driving board 20 and a power board 30;

[0048] The main control board 10 is connected to the drive board 20 and the power supply board 30. The main control board 10 includes an FPGA chip 11, a serial port circuit 12, a refresh circuit 13, and a DC power converter 14. The FPGA chip 11 is connected to the serial port circuit 12, the refresh circuit 13, and the DC power converter 14;

[0049] The drive board 20 is also connected to the power supply board 30. The drive board 20 includes a main drive module 21, a backup drive module 22, and a main / backup switching relay 23. The main drive module 21 is connected to the main control board 10, the power supply board 30, and the main / backup switching relay 23. The backup drive module 22 is connected to the main control board 10, the power supply board 30, and the main / backup switching relay 23;

[0050] The main drive module 21 and the backup drive module 22 have the same structure, and both include a power supply and soft start circuit 211, a drive circuit 212, a current acquisition circuit 213, an AD acquisition circuit 214, a differential transmission circuit 215, an isolation circuit 216, and a relay switching circuit 217;

[0051] The power supply and soft start circuit 211 is connected to the drive circuit 212. The drive circuit 212 is also connected to the isolation circuit 216, the differential transmission circuit 215, and the current acquisition circuit 213. The current acquisition circuit 213 is also connected to the AD acquisition circuit 214 and the main / backup switching relay 23. The AD acquisition circuit 214 is also connected to the differential transmission circuit 215 and the main / backup switching relay 23. The relay switching circuit 217 is connected to the isolation circuit 216 and the main / backup switching relay 23.

[0052] It should be noted that the attached drawings of the present disclosure are only schematic and do not represent its actual structure, nor are they limited thereto.

[0053] Specifically, the present disclosure provides a space motor drive device 100 based on an FPGA. The device includes a driver 01 and a permanent magnet synchronous motor M. The driver 01 is connected to the permanent magnet synchronous motor M. The driver 01 is used to drive the permanent magnet synchronous motor M. It should be noted that the permanent magnet synchronous motor M includes an encoder A and an encoder B. The FPGA chip 11 supplies power to the encoder A and the encoder B. The encoder A and the encoder B feed back position data to the driver 01, which is beneficial to the precise control of the permanent magnet synchronous motor M by the driver 01. At the same time, setting two encoders is beneficial to improving the reliability of the space motor drive device.

[0054] The driver 01 includes a main control board 10, a drive board 20, and a power supply board 30. Among them, the main control board 10 includes an FPGA chip 11, a serial port circuit 12, a refresh circuit 13, and a DC power converter 14.

[0055] The main control board 10 includes an FPGA chip 11. The FPGA chip 11 is the core control processor in the driver 01. The FPGA (Field-Programmable Gate Array) chip is a high-performance, programmable digital logic device, which has the advantages of fast processing speed, low power consumption, small size, and high reliability. In this disclosure, the FPGA chip 11 is used to control the permanent magnet synchronous motor M, which is beneficial to improving the processing speed and computing power of the aerospace motor drive device, and thus beneficial to meeting the requirements of complex control algorithms. At the same time, the low power consumption characteristic of the FPGA chip 11 is also beneficial to reducing the overall energy consumption of the aerospace motor drive device, thereby beneficial to extending the service life of the aerospace motor drive device. In addition, the small size and high reliability of the FPGA chip 11 are beneficial to being applied in scenarios with limited space and harsh environments such as aerospace scanning devices, thus beneficial to improving the high reliability of aerospace scanning devices. An optional implementation provided by this disclosure is that the FPGA chip 11 is an aerospace-grade FPGA chip 11. It should be noted that aerospace-grade FPGA chips refer to field-programmable gate array (FPGA) chips used in the aerospace field, which need to meet special requirements such as high reliability, high performance, and radiation resistance to ensure stable operation in the space environment. Aerospace-grade FPGA chips need to be able to withstand extreme conditions in the space environment, such as high vacuum, large temperature difference, and strong radiation. Therefore, aerospace-grade FPGA chips usually adopt special packaging materials and designs, which are more beneficial to improving the reliability of the aerospace motor drive mechanism. Aerospace missions usually need to process a large amount of data and complex algorithms. Therefore, aerospace-grade FPGA chips need to have high-performance computing and data processing capabilities. Aerospace-grade FPGA chips usually adopt advanced manufacturing processes and architecture designs to improve their performance and efficiency. The radiation in the space environment will affect electronic devices, resulting in chip failure or performance degradation. Aerospace-grade FPGA chips need to have radiation resistance to ensure stable operation in the radiation environment. Optionally, the FPGA chip 11 is selected as the aerospace-grade FPGA JFM7K325T-C EM. This disclosure is only illustrative with this example and is not limited thereto.

[0056] The main control board 10 further includes a serial port circuit 12. The serial port circuit 12 is a circuit for the main control board 10 to interact with mechanisms outside the main control board 10. An optional implementation provided by this disclosure is that the driver 01 needs to interact with the control platform. For example, if the FPGA chip 11 needs to receive control information sent by the control platform, it receives the control information through the serial port circuit 12. If the FPGA chip 11 needs to feedback information to the control platform, it gives feedback through the serial port circuit 12.

[0057] The main control board 10 further includes a refresh circuit 13, which is a circuit for online, reloading, and refreshing the FPGA chip 11. An optional implementation provided by the present disclosure is that the refresh circuit 13 includes a refresh chip 131 and a FLASH chip 132. The refresh chip 131 is respectively connected to the FPGA chip 11 and the FLASH chip 132. Optionally, the refresh chip 131 is selected as the refresh chip JFMRS01RH of Fudan Microelectronics Company, and the FLASH chip 132 is selected as the norflash chip JFM29LV641RH. The refresh chip 131 communicates with the FPGA chip 11 through the serial port of the refresh chip 131 and the SelectMAP interface of the FPGA chip 11. The FLASH chip 132 is used to store the uploaded code, startup-related information, and parameters that need to be saved during power-off. It should be noted that the present disclosure is only illustrated by this example and is not limited thereto. It can be understood that by setting the refresh circuit 13, it is beneficial to perform online reconstruction, reloading, and refreshing operations on the FPGA chip 11, thereby improving the reliability and configuration flexibility of the driver 01. In particular, when the aerospace motor drive device needs to update functions or solve vulnerabilities, the on-orbit program can be updated through reconstruction. If the FPGA chip 11 undergoes single-event upsets due to space radiation, the refresh function is also beneficial to periodically eliminate the impact of single-event upsets on the FPGA chip 11.

[0058] The main control board 10 further includes a DC power converter 14. The DC power converter, also known as a DC-DC (Direct Current - Direct Current) converter, is a converter that converts a DC power supply into a DC power supply with a different voltage. The DC power converter 14 is connected to the power supply board 30 and the FPGA chip 11. After converting the power supply input from the power supply board 30 to the main control board 10, it is output to the FPGA chip 11 for power supply, which is beneficial to provide a suitable power supply for the FPGA chip 11, thereby improving the stability and reliability of the FPGA chip 11.

[0059] The drive board 20 includes a main drive module 21, a backup drive module 22, and a main / backup switching relay 23. In this disclosure, two completely identical drive modules are provided in the drive board 20, namely the main drive module 21 and the backup drive module 22. The main drive module 21 and the backup drive module 22 are connected to the main / backup switching relay 23 by jump wires, and they jointly form a cross-backup in a cold backup form. Only the main drive module 21 or only the backup drive module 22 works at the same time. Meanwhile, the main drive module 21, the backup drive module 22, the power supply board 30, and the main control board 10 are all in a cold main / backup relationship and can achieve cross-control. The main drive module 21 and the backup drive module 22 output three-phase U / V / W control signals through the main / backup switching relay 23 to control the rotation of the same permanent magnet synchronous motor M. In this disclosure, setting two completely identical drive modules and forming a cross-backup relationship is beneficial to improving the reliability of the aerospace motor drive device. An optional implementation provided by this disclosure is that the main / backup switching relay 23 includes a magnetic latching relay 231 and a motor connector 232. The magnetic latching relay 231 is connected to the main drive module 21, the backup drive module 22, and the motor connector 232. The magnetic latching relay 231 is used to switch between the main drive module 21 and the backup drive module 22, and the control signal is output to the permanent magnet synchronous motor M through the motor connector 232. This disclosure is only illustrated by this example and is not limited thereto.

[0060] The structures of the main drive module 21 and the backup drive module 22 are completely the same, and both include a power supply and soft start circuit 211, a drive circuit 212, a current acquisition circuit 213, an AD acquisition circuit 214, a differential transmission circuit 215, an isolation circuit 216, and a relay switching circuit 217. Among them:

[0061] The power supply and soft start circuit 211 is connected to the drive circuit 212. It should be noted that the soft start circuit is a circuit used to limit the rising rate of current and voltage during the startup or start process of an electronic device, so as to reduce the impact on the circuit and device. Its main functions include: preventing inrush current: When the power supply is turned on instantaneously, due to the charging of the capacitors in the circuit, a large instantaneous current may be generated. The soft start circuit can limit the peak value of this current and protect the power supply and other components from being damaged by excessive current; reducing voltage overshoot: It helps to avoid excessive voltage spikes at the output during startup and protects the load device; improving system stability: enabling the system to enter the normal working state more smoothly and reducing possible interference and faults. Therefore, setting the soft start circuit 31 in the main drive module 21 and the backup drive module 22 in this disclosure is beneficial to reducing the impact on the aerospace motor drive device, thereby helping to improve the service life and reliability of the aerospace motor drive device.

[0062] The drive circuit 212 is connected to the differential transmission circuit 215, the isolation circuit 216, and the current acquisition circuit 213. The drive circuit 212 is used to output the SVPWM (Sinusoidal Pulse Width Modulation) with variable duty cycles of three phases U / V / W to control the voltage of the permanent magnet synchronous motor M, and further control the rotation speed of the permanent magnet synchronous motor M. An optional implementation provided by the present disclosure is that the drive circuit 212 includes a three-phase bridge drive chip IR2136S and six MOS transistors. The drive chip IR2136S receives three PWM waveforms PWM1-3 and one PWM enable PWM_EN sent by the main control board 10, and controls the voltage of the permanent magnet synchronous motor M by outputting the SVPWM with variable duty cycles of three phases U / V / W, and further controls the motor rotation speed. Figure 3 The following is a schematic connection diagram of a drive circuit provided by an embodiment of the present disclosure. Figure 4 The following is a schematic diagram of a drive chip provided by an embodiment of the present disclosure. Please refer to Figure 3 and Figure 4 , the present disclosure provides a connection method for MOS transistors and a drive chip, where the signals of UHO_B, ULO_B, VHO_B, VLO_B, WHO_B, WLO_B, VSU_B, VSV_B, and VSW_B are all provided by the drive chip IR2136S. It should be noted that the present disclosure is only illustrated by this example and is not limited thereto.

[0063] The current acquisition circuit 213 is connected to the drive circuit 212 and the AD acquisition circuit 214. The current acquisition circuit 213 is used to acquire the current value of each phase of the three-phase permanent magnet synchronous motor M. An optional implementation provided by the present disclosure is that the current acquisition circuit 213 includes a sampling resistor and three operational amplifier chips. The three-phase currents respectively pass through the sampling resistor and the operational amplifier chips. The current value of each phase of the three-phase permanent magnet synchronous motor M can be obtained through resistance sampling. In this way, it is beneficial to improve the sampling accuracy, and further beneficial to improve the reliability of the aerospace motor drive device.

[0064] The AD acquisition circuit 214 is connected to the differential transmission circuit 215 and the current acquisition circuit 213. In order to improve the reliability of the acquisition part of the driver 01, the main and backup acquisition channels are set for the three-phase currents of the permanent magnet synchronous motor M. An implementation of the AD acquisition circuit 214 provided by the present disclosure is that the AD acquisition circuit 214 selects a high-precision synchronous sampling ADC acquisition chip with 8 channels and 16 bits and 1MSPS. The U-phase current is input into channels 1 and 2 of the AD acquisition chip, the V-phase current is input into channels 3 and 4 of the AD acquisition chip, and the W-phase current is input into channels 5 and 6 of the AD acquisition chip. Channels 1-6 are all acquisition channels of the AD acquisition chip. The present disclosure is only illustrated by this example and is not limited thereto.

[0065] The differential transmission circuit 215 is connected to the isolation circuit 216, the drive circuit 212, and the AD acquisition circuit 214. The control signal is transmitted to the drive circuit 212 through differential transmission. The drive circuit 212 performs state feedback. With such a setting, it is beneficial to improve the anti-interference ability, thereby enhancing the reliability and stability of the driver 01. An optional implementation provided by the present disclosure is that the differential transmission circuit 215 includes an LVDS transmitter chip and a receiver chip (not shown in the figure). The present disclosure is only described by taking this as an example and is not limited thereto.

[0066] The isolation circuit 216 is connected to the differential transmission circuit 215, the drive circuit 212, and the relay switching circuit 217. The setting of the isolation circuit 216 is beneficial for isolating voltage and protecting the circuit. The control signal is transmitted from the differential transmission circuit 215 to the isolation circuit for voltage isolation and then transmitted to the drive circuit 212. For example, a BUFFER chip can be used. The setting of the isolation circuit 216 is beneficial for improving the reliability of the aerospace motor drive device.

[0067] The relay switching circuit 217 is connected to the isolation circuit 216 and is used to switch between the main drive module 21 and the backup drive module 22. An optional implementation provided by the present disclosure is that the relay switching circuit 217 is controlled by an 80ms OC low pulse switching instruction output by the FPGA chip 11. The power supplies for the two coils of the relay for switching to the main and switching to the backup are separated. The main supply powers the coil for switching to the main, and the backup supply powers the coil for switching to the backup. When the main supply is powered, the instruction for switching to the main is automatically executed. When the instruction for switching to the backup is received, since the backup is not powered, no action is taken. Similarly, when the backup is powered, the instruction for switching to the backup is automatically executed.

[0068] It should be noted that the main drive module 21 and the backup drive module 22 may further include a signal connector 218. The signal connector 218 is connected to the differential transmission circuit 215 and is used to receive the signal transmitted by the main control board 10. The main / backup switching relay 23 may further include a motor connector 232 for transmitting the control signal to the permanent magnet synchronous motor M.

[0069] The power supply board 30 is used to supply power to the main control board 10 and the drive board 20. The power supply board 30 and the main control board 10 are connected through a connector, and the power supply board 30 and the drive board 20 are connected through a connector. An optional implementation provided by the present disclosure is that the power supply board 30 includes a soft start circuit 31 and a DC power converter 32, and the soft start circuit 31 is connected to the DC power converter 32. The DC power converter 32 is used to convert the power into a power suitable for the main control board 10 and the drive board 20 to supply power to the main control board 10 and the drive board 20. The soft start circuit is a circuit that limits the rising rate of current and voltage during startup or start-up to reduce the impact on the circuit and equipment. Setting the soft start circuit 31 in the power supply board 30 is beneficial to reducing the impact on the aerospace motor drive device, thereby being beneficial to improving the service life and reliability of the aerospace motor drive device.

[0070] It can be understood that the aerospace motor drive device 100 based on FPGA provided by the present disclosure uses the FPGA chip 11 to achieve the control of the permanent magnet synchronous motor M, which is beneficial to improving the processing speed and computing power of the aerospace motor drive device, thereby being beneficial to meeting the requirements of complex control algorithms, and further being beneficial to improving the synchronous concurrency problem of controlling the motor movement and processing other work tasks in aerospace; at the same time, the low-power consumption characteristic of the FPGA chip 11 is also beneficial to reducing the overall energy consumption of the aerospace motor drive device, thereby being beneficial to extending the service life of the aerospace motor drive device; in addition, the FPGA chip 11 has high reliability, which is beneficial to being applied in scenarios with limited space and harsh environment such as aerospace scanning devices, thereby being beneficial to improving the high reliability of aerospace scanning devices; by setting the refresh circuit 13, it is beneficial to perform online reconfiguration, reloading and refreshing operations on the FPGA chip 11, thereby being beneficial to improving the reliability and configuration flexibility of the driver 01; also by setting two completely identical drive modules and forming a cross-backup relationship, it is more beneficial to improve the reliability of the aerospace motor drive device.

[0071] In order to more clearly illustrate the aerospace motor drive device based on FPGA, the present disclosure provides a driver control system for the aerospace motor drive device based on FPGA. Figure 5 The figure shows a schematic diagram of a driver control system for an aerospace motor drive device based on FPGA provided by an embodiment of the present disclosure. Figure 6 The figure shows a connection schematic diagram of a driver control system for an aerospace motor drive device based on FPGA provided by an embodiment of the present disclosure. Please refer to Figures 1 to 6 , the driver control system 200 for the aerospace motor drive device based on FPGA includes:

[0072] Serial communication module 201, working mode distribution module 202, relay switching module 203, encoder control module 204, AD acquisition module 205, FOC control module 206, driver chip control module 207, alarm control module 208, and refresh module 209;

[0073] The serial communication module 201 is used to receive control information; it is also used to periodically feedback actual operation information;

[0074] The working mode distribution module 202 is used to set the working mode according to the control information; it is also used to perform encoder switching of the permanent magnet synchronous motor M according to the control information; among them, the working modes include a constant speed mode, a fixed point mode, and a variable speed mode;

[0075] The relay switching module 203 is used to switch the relay;

[0076] The encoder control module 204 is used to send a clock to the encoder; it is also used to receive the feedback information of the encoder;

[0077] The AD acquisition module 205 is used for three-phase current acquisition, supply voltage telemetry acquisition, and main backup switching relay state acquisition; it is also used to send the average current to the FOC control module 206;

[0078] The driver chip control module 207 is used to generate a driver chip control signal; it is also used to receive a driver chip alarm signal;

[0079] The alarm control module 208 is used to monitor the actual current, actual speed, and actual acceleration; it is also used to receive the encoder alarm information sent by the encoder control module 204 and the driver chip alarm information sent by the driver chip control module 207, and generate an alarm code;

[0080] The refresh module 209 is used to refresh or reconstruct the driver control system 200 of the aerospace motor drive device based on FPGA;

[0081] The FOC control module 206 is used to control the current loop, speed loop, and position loop using the FOC algorithm.

[0082] Specifically, the present disclosure also provides a driver control system 200 of an aerospace motor drive device based on FPGA, and this driver control system includes: a serial communication module 201, a working mode distribution module 202, a relay switching module 203, an encoder control module 204, an AD acquisition module 205, an FOC control module 206, a driver chip control module 207, an alarm control module 208, and a refresh module 209.

[0083] The serial communication module 201 is used to receive control information and periodically feedback actual operation information. An optional implementation provided by the present disclosure is that the serial communication module 201 is connected to the serial circuit 12, and receives the control information sent by the control platform through the serial circuit 12. The control information includes working mode setting, target speed, target position, PID control parameters, current acquisition channel, and encoder power-on / off information. At the same time, the actual operation information is fed back to the control platform every 500 ms (the present disclosure only takes this as an example for illustration, and is not limited thereto, and can be set according to actual situations). The actual operation information includes actual speed, actual position, target speed, target position, PID control parameters, real-time voltage and current data, relay status information, encoder power-on status, and alarm information. Receiving control information and feeding back actual operation information through the serial communication module 201 is beneficial to timely adjust the drive control parameters, thereby facilitating precise control.

[0084] The working mode distribution module 202 is used to set the working mode according to the control information, and perform encoder switching of the permanent magnet synchronous motor M according to the control information. An optional implementation provided by the present disclosure is that the working mode distribution module 202 is connected to the serial communication module 201 and the FOC control module 206. The working mode distribution module 202 realizes the setting of the working mode (including constant speed mode, fixed point mode, and variable speed mode), as well as the setting of the target position and target speed according to the control information received by the serial communication module 201, and switches the encoder M-1 in the permanent magnet synchronous motor M according to the instruction. The encoder M-1 includes encoder A and encoder B. The working mode distribution module 202 performs power-on switching of encoder A and encoder B according to the control information, or realizes power-on self-switching of encoder A and encoder B after receiving the encoder alarm signal. Figure 7 The following is a schematic flowchart of an encoder switching provided by an embodiment of the present disclosure. Please refer to Figure 7 The present disclosure provides a flowchart for power-on switching of encoder A and encoder B.

[0085] The relay switching module 203 is used to switch the relay. An optional implementation provided by the present disclosure is that the relay switching module 203 is connected to the serial communication module 201 and the relay switching circuit 217. After the device is powered on or reset, the relay switching module 203 automatically sends a low pulse of 80 ms to execute relay switching, ensuring that the current relay state is correct and the control platform can view the relay status information through the serial communication module 201.

[0086] The encoder control module 204 is used to send a clock to the encoder and receive the feedback information of the encoder. An optional implementation provided by the present disclosure is that the encoder control module 204 is connected to the FOC control module 206, the alarm control module 208, and the encoder M-1. The encoder control module 204 sends a clock to the encoder M4-1, and the sent clock notifies the grating end to start collecting position data. The encoder M4-1 feeds back the feedback information to the encoder control module 204 according to the clock. The feedback information includes angular position information, encoder alarm information, and a check value. The encoder control module 204 receives the angular position information, encoder alarm information (the grating should be cleaned, the position data is unreliable), and the check value fed back by the encoder according to the encoder protocol. A check alarm is generated for the position information that fails to pass the check continuously for 6 times. The above three kinds of alarm information are all transmitted to the alarm control module 208 in real time.

[0087] The AD acquisition module 205 is used for three-phase current acquisition, supply voltage telemetry acquisition, and main backup switching relay state acquisition; it is also used to send the average current to the FOC control module 206. An optional implementation provided by the present disclosure is that the AD acquisition module 205 is connected to the FOC control module 206, the alarm control module 208, and the AD acquisition circuit 214. The U / V / W three-phase current acquisition, supply voltage telemetry acquisition, and main backup switching relay state acquisition are performed through the AD acquisition circuit 214. The current value is averaged by multiple acquisitions and sent to the FOC control module 206. Taking the average value by multiple acquisitions is beneficial to improving the accuracy of the acquired data, and thus beneficial to improving the accuracy of the control of the permanent magnet synchronous motor M.

[0088] The drive chip control module 207 is connected to the FOC control module 206, the alarm control module 208, and the drive circuit 212, and is used to generate drive chip control signals and receive drive chip alarm signals. For example, when the drive chip has overcurrent or undervoltage, it sends a drive chip alarm signal to the drive chip control module 207.

[0089] The alarm control module 208 is connected to the serial communication module 201, the encoder control module 204, the drive chip control module 207, and the AD acquisition module 205, and is used to monitor whether the actual current exceeds the current limit value, whether the actual speed exceeds the speed limit value, and whether the actual acceleration exceeds the acceleration limit value. At the same time, it receives the alarm information of the encoder control module 204 and the drive chip control module 207, generates corresponding alarm codes, and can also perform cyclic display.

[0090] The refresh module 209 is used to refresh, reload, and reconstruct the driver control system 200 of the space motor drive device based on FPGA, which is beneficial for the space motor drive device to adapt to the harsh space environment, and further beneficial for improving the high reliability of the space motor drive device. An optional implementation provided by the present disclosure is that the refresh module 209 is connected to the serial communication module 201 and the refresh circuit 13. When the refresh module 209 refreshes the driver control system 200 of the space motor drive device based on FPGA, it first performs SEFI (single event functional interrupt) detection on the FPGA chip 11. If the detection fails, it performs reloading; if the detection passes, it sequentially sends new bitstreams of the refresh file to the FPGA chip 11 through the SelsectMAP interface of the FPGA chip 11. The bitstream data includes a command header, register operations, configuration data, a command tail, etc. When the refresh module 209 reloads the driver control system 200 of the space motor drive device based on FPGA, it sends a 1us low pulse reset signal to the FPGA chip 11, waits for the flag signal of the FPGA chip 11 to be pulled high, and provides control signals and data to the FPGA chip 11 according to the SelsectMAP interface. When the refresh module 209 reconstructs the driver control system 200 of the space motor drive device based on FPGA, it first sends a NOR FLASH full erase instruction through the serial port of the refresh chip 131 in the refresh circuit 13. After waiting for the return of the erase success instruction and the correct reconstruction CRC check, it sends a NOR FLASH programming instruction until all bitstreams are sent. It uses the FLASH verification command to ensure the correctness of the downloaded bitstream data, and the reconstruction is completed.

[0091] The FOC control module 206 is connected to the working mode distribution module 202, the encoder control module 204, the driver chip control module 207, and the AD acquisition module 205. Figure 8 The following shows a control schematic diagram of an FOC control module provided by an embodiment of the present disclosure. Please refer to Figure 8, the FOC control module is used to control the current loop, speed loop and position loop using the FOC (Field-Oriented Control) algorithm. It receives the U / V / W three-phase currents collected by the AD acquisition module 205 in real time, and takes the average value of multiple acquisitions as the actual current value. It also receives the encoder feedback information received by the encoder control module 204 in real time, and calculates the actual operating speed and acceleration. An optional implementation provided by the present disclosure is that for the current loop, by comparing the actual current and the target current and using the PI regulation method, rapid torque control can be achieved; for the speed loop, by comparing the actual speed and the target speed and using the PID regulation method, rapid speed control can be achieved; for the position loop, by comparing the actual position and the target position and using the PID regulation method, rapid angle control can be achieved. Among them, the PID controller uses a positional PID control with integral limiting and output limiting. After multi-loop control, the synthesized voltage space vectors Vα and Vβ are finally output and input to the SVPWM module in the FOC control module 206 for modulation. The SVPWM can output three-phase PWM in the form of a look-up table, and finally controls the drive chip to drive the MOS transistor switch and commutation.

[0092] It should be noted that PID (Proportional-Integral-Derivative) control, that is, proportional-integral-derivative control, is a common and classical control algorithm. The proportional (P) control action adjusts the control quantity proportionally according to the magnitude of the deviation, which can quickly reduce the deviation but cannot eliminate the steady-state error. The integral (I) control action can eliminate the steady-state error of the system, but too strong integral action may increase the overshoot of the system and even make the system unstable. The derivative (D) control action adjusts the control quantity according to the change speed of the deviation, can predict the change trend of the deviation, and gives a large adjustment action in advance, so as to reduce the overshoot and increase the stability of the system. The PID controller combines the advantages of these three control actions. By adjusting the proportional coefficient, integral time constant and derivative time constant, it can adapt to different control objects and control requirements. The inventor found in the research that for the control of the current loop, the derivative (D) control action has no obvious effect and significance on the current. Therefore, the current loop uses PI regulation, and the speed loop and position loop use PID regulation.

[0093] It can be understood that the driver control system 200 of the space motor drive device based on FPGA is installed in the FPGA chip 11, which is beneficial to improving the reliability of the space motor drive device; a refresh module 209 is provided, and through the control of the refresh module 209 and the refresh circuit 13, it is beneficial to realize the on-orbit update of the driver 01 control system; at the same time, it is also beneficial to improve the synchronous concurrency problem of controlling the motor movement and processing other tasks; and, the present disclosure uses the FOC algorithm for control, which is beneficial to improving the running smoothness and response efficiency.

[0094] An optional implementation manner provided by the present disclosure is that the driver control system 200 of the space motor drive device based on FPGA adopts a triple modular redundancy design.

[0095] Specifically, in this implementation manner, the driver control system 200 of the space motor drive device based on FPGA adopts a triple modular redundancy design. Triple Modular Redundancy (abbreviated as TMR) is a fault-tolerant design technology that improves the reliability of the system by adding redundant modules. The three modules execute the same operation simultaneously, and then the outputs of the three modules are majority-voted by a voter to determine the final output result. As long as two or three module errors do not occur simultaneously, the errors of the faulty module can be masked to ensure the correct output of the system. The present disclosure adopts a triple modular redundancy design, which is beneficial to improving the fault tolerance of the system, reducing the risk of system failure caused by a single module failure, and thus beneficial to improving the reliability of the space motor drive device.

[0096] To more clearly illustrate the space motor drive device based on FPGA, the present disclosure provides a driver control method for the space motor drive device based on FPGA. Figure 9 The following shows a schematic flowchart of a driver control method for a space motor drive device based on FPGA provided by an embodiment of the present disclosure. Figure 10 The following shows a control flowchart of a permanent magnet synchronous motor provided by an embodiment of the present disclosure. Please refer to Figures 1 to 6 and Figure 9 and Figure 10 , the driver control method for the space motor drive device based on FPGA includes:

[0097] Step S01, power on and initialize the permanent magnet synchronous motor M;

[0098] Step S02, the permanent magnet synchronous motor M receives the control information sent by the driver 01;

[0099] Step S03, the driver 01 collects three-phase current signals;

[0100] Step S04: Power on the encoder of the permanent magnet synchronous motor M;

[0101] Step S05: After the encoder sends feedback information and there is no alarm signal, adjust the current loop, speed loop, and position loop according to the PID control parameters;

[0102] Step S06: Select the working mode. When the working mode is the constant speed mode, the current loop and speed loop work; when the working mode is the fixed point mode, the current loop, speed loop, and position loop work; when the working mode is the variable speed mode, the current loop and speed loop work, and set the variable speed scanning motion planning look-up table. The variable speed scanning motion planning look-up table is used to complete the planned speed curve and actual speed curve of one rotation cycle within a specific time, and scan and observe in a cycle.

[0103] Specifically, the present disclosure provides a drive control method for an aerospace motor drive device based on FPGA. The drive control system 200 of the aerospace motor drive device based on FPGA provided by the present disclosure is used to control the permanent magnet synchronous motor M, including but not limited to steps S01 to S06. In step S01, the permanent magnet synchronous motor M is powered on and initialized; in step S02, the permanent magnet synchronous motor M receives the control information sent by the driver 01; in step S03, the driver 01 collects three-phase current signals through the AD acquisition circuit 214, and multiple acquisitions are averaged as the actual current value. In this way, it is beneficial to improve the accuracy of acquisition; in step S04, the permanent magnet synchronous motor M performs encoder power-on. It should be noted that the permanent magnet synchronous motor M includes encoder A and encoder B. At the same time, only one encoder works. If it is detected that the current encoder alarms, the current encoder is powered off, and automatically switched to the other encoder for power-on; in step S05, the encoder sends feedback information, and the feedback information includes angular position information, encoder alarm information, and check value. When there is no alarm signal in the feedback information, the current loop, speed loop, and position loop are adjusted according to the received P, I, D control parameters; in step S06, a working mode is selected. An optional implementation provided by the present disclosure is that the working mode is a constant speed mode. At this time, the current loop and speed loop work. Within 10 s after the permanent magnet synchronous motor M starts, it slowly increases from rest to the target speed, and then according to the current and speed feedback, the PID parameters are received in real time to adjust the motor rotation, and the motor can be controlled to rotate forward, reverse, and adjusted to the target rotation speed according to the instruction; another optional implementation provided by the present disclosure is that the working mode is a fixed point mode. At this time, the current loop, speed loop, and position loop work, and the motor can be controlled to rotate forward, reverse, and stop at a fixed point according to the instruction. After the motor stops, it waits for the next regulation to continue rotating; yet another optional implementation provided by the present disclosure is that the working mode is a variable speed mode. At this time, only the speed loop and current loop work, and a variable speed scanning motion planning lookup table is set up to achieve the planned speed curve and actual speed curve of a transfer cycle within a specific time, and the scanning observation is repeated.

[0104] It can be understood that the drive control method for the aerospace motor drive device based on FPGA provided by the present disclosure controls the permanent magnet synchronous motor M by receiving the control information of the driver 01, and feeds back the position data through the encoder in the permanent magnet synchronous motor M, so as to further adjust the operation of the permanent magnet synchronous motor M, which is beneficial to realizing the precise control of the permanent magnet synchronous motor M; at the same time, the present disclosure is also beneficial to realizing the requirements of slow start and deceleration stop of the permanent magnet synchronous motor M, and is also beneficial to realizing the constant speed motion control, fixed point stop control, and variable speed motion control of the permanent magnet synchronous motor M.

[0105] It should be noted that, for the purpose of clearly describing the space motor drive device based on FPGA provided by the present disclosure, a driver control system and method of the space motor drive device based on FPGA are provided for description, but it is not limited thereto, and other driver control systems and methods can also be used.

[0106] It should be noted that, in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0107] The above are only specific embodiments of the present disclosure, enabling those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to these embodiments described herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An aerospace motor drive device based on FPGA, characterized in that, It includes a driver and a permanent magnet synchronous motor. The driver is connected to the permanent magnet synchronous motor, and the driver is used to drive the permanent magnet synchronous motor. The driver includes a main control board, a drive board, and a power supply board. The main control board is connected to the drive board and the power supply board. The main control board includes an FPGA chip, a serial port circuit, a refresh circuit, and a DC power converter. The FPGA chip is connected to the serial port circuit, the refresh circuit, and the DC power converter. The drive board is also connected to the power supply board. The drive board includes a main drive module, a backup drive module, and a main / backup switching relay. The main drive module is connected to the main control board, the power supply board, and the main / backup switching relay. The backup drive module is connected to the main control board, the power supply board, and the main / backup switching relay. The main drive module and the backup drive module have the same structure, and both include a power supply and soft start circuit, a drive circuit, a current acquisition circuit, an AD acquisition circuit, a differential transmission circuit, an isolation circuit, and a relay switching circuit. The power supply and soft start circuit is connected to the drive circuit. The drive circuit is also connected to the isolation circuit, the differential transmission circuit, and the current acquisition circuit. The current acquisition circuit is also connected to the AD acquisition circuit and the main / backup switching relay. The AD acquisition circuit is also connected to the differential transmission circuit and the main / backup switching relay. The relay switching circuit is connected to the isolation circuit and the main / backup switching relay.

2. The FPGA-based aerospace motor drive device according to claim 1, characterized in that The refresh circuit includes a refresh chip and a FLASH chip. The refresh chip is respectively connected to the FPGA chip and the FLASH chip.

3. The aerospace motor drive device based on FPGA according to claim 1, characterized in that The power supply board includes a soft start circuit and a DC power converter. The soft start circuit is connected to the DC power converter.

4. The FPGA-based aerospace motor drive device according to claim 1, characterized in that The FPGA chip is an aerospace-grade FPGA chip.

5. The space motor drive device based on FPGA according to claim 1, characterized in that, The permanent magnet synchronous motor includes two encoders. The encoders are both connected to the FPGA chip. At the same time, only one of the encoders works.

6. The FPGA-based aerospace motor drive device according to claim 1, characterized in that, The main / backup switching relay includes a magnetic latching relay and a motor connector. The magnetic latching relay is connected to the main drive module, the backup drive module, and the motor connector.

7. The space motor drive device based on FPGA according to claim 1, wherein The main drive module and the backup drive module also include a signal connector. The signal connector is connected to the differential transmission circuit.

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