Discrete level test equipment
By integrating the XC7A35T master control chip and related components in discrete level testing equipment, the problem of positioning difficulties in custom interface testing is solved, efficient interface testing and problem positioning is achieved, and the operability and accuracy of the test equipment are improved.
Patent Information
- Application Number
- CN202422082143.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-27
- Publication Date
- 2025-07-22
- Estimated Expiration
- 2034-08-27
AI Technical Summary
The prior art is difficult to effectively locate implicit defects of custom interfaces in testing equipment, resulting in system failure and delayed testing progress, and unskilled equipment operation and limited testing scope.
A discrete level testing device is designed to integrate FPGA software on the XC7A35T main control chip, and communicate with the tool to be tested through the interface slot line to realize signal generation and acquisition, and integrate LED lights, knobs, display screens and other components to support the adjustment of level values, signal frequency and output times.
It realizes direct interface testing of the tooling under test, can accurately locate problems quickly, supports the duration statistics and status parameter configuration of discrete signals, and improves testing efficiency and accuracy.
Smart Images
Figure CN223139698U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of interface testing, and specifically relates to a discrete level testing device. Background Technique
[0002] In all walks of modern industry, the development of various equipment systems has advanced by leaps and bounds. The system architecture has become increasingly complex, and the components involved internally have also become more and more numerous. Embedded software systems are quite widely used in the system. However, the current quality situation is not optimistic. Model systems frequently experience system failures and task failures due to implicit defects in interface design, resulting in a large waste of resources. Therefore, higher requirements are put forward for the reliability of data cross-linking between subsystems.
[0003] In the previous tests of equipment containing embedded software, for common interface protocols, interface testing tools (such as serial port assistants) can be used. When data is exchanged between devices through unconventional, custom interfaces or discrete control signals, only test equipment such as oscilloscopes and logic analyzers can be used to read the received data, but the sending of data is relatively limited. Usually, only interface coverage can be achieved through system testing. After problems occur, they cannot be accurately and quickly located, delaying the testing progress. Based on this, the research team published the "Research on a High-Degree-of-Freedom Discrete Level Testing Tool Based on FPGA". In the above article
[0004] For the above reasons, a high-degree-of-freedom discrete level testing tool based on FPGA was designed to solve problems such as insufficient testing equipment, unfamiliar operation of equipment, limited testing range of equipment, and difficulty in problem location. In 2021, the article "Research on a High-Degree-of-Freedom Discrete Level Testing Tool Based on FPGA" was published. The designed high-degree-of-freedom discrete level testing tool consists of a host computer module and an FPGA module. The two are connected through a serial port for data interaction. Among them, the host computer module mainly completes issuing commands and receiving and displaying status information. The FPGA module mainly generates and collects discrete levels according to the received commands, and reports the corresponding status to the host computer. The core of its previous research lies in the design of the command issuing software of the host computer and the execution software of the FPGA module. The FPGA chip is connected to the computer through a Usb Cable2.0 hardware, but the detection equipment integrating the FPGA module has not been formed. Summary of the Invention
[0005] The purpose of the utility model is to provide a discrete level testing device, integrate the FPGA software on the XC7A35T main control chip, and place the XC7A35T main control chip inside the high-degree-of-freedom discrete level testing device body, and generate and collect discrete levels according to the commands sent by the received host computer.
[0006] To achieve the above object, the present utility model provides the following technical solutions:
[0007] A discrete level testing device. The discrete level testing device establishes communication with the tooling under test through an interface slot line and realizes signal generation. The discrete level testing device includes a housing. A hardware circuit board is arranged inside the housing. An XC7A35T main control chip is integrated on the hardware circuit board. The XC7A35T main control chip executes the generation and acquisition of discrete levels according to the commands received from the host computer.
[0008] In the above technical solution, further, an LED lamp is also integrated on the hardware circuit board. The LED lamp is connected to the XC7A35T main control chip for status display, and the body of the LED lamp protrudes outside the housing.
[0009] In the above technical solution, furthermore, an adjustable knob is arranged on the housing. A rotary potentiometer is also integrated on the hardware circuit board. The rotary potentiometer is respectively connected to the XC7A35T main control chip and the adjustable knob, and is used to adjust the level value, signal frequency, output times, and output interval.
[0010] In the above technical solution, furthermore, a display screen is arranged on the housing. The back of the display screen is connected to the display screen interface slot on the hardware circuit board, and is used to display the configured signals and waveforms.
[0011] In the above technical solution, furthermore, a key switch is also arranged on the housing. The back of the key switch is integrated on the hardware circuit board and is connected to the XC7A35T main control chip.
[0012] In the above technical solution, furthermore, an interface slot is also integrated on the hardware circuit board. The interface slot is respectively connected to the XC7A35T main control chip, and the interface slot is used to connect the interface plug wire.
[0013] In the above technical solution, furthermore, a clock source, an IO expansion port, a USB interface, a JTAG download port, and a FLASH storage module are also integrated on the hardware circuit board. The clock source is used to provide the system input clock. The IO expansion port is used for expanding the functional IO pin resources. The USB interface can be connected to the test computer and is controlled by the host computer. The JTAG download port provides online upgrade. The FLASH storage module is used for storing the basic configuration data.
[0014] In the above technical solution, furthermore, a power socket is integrated on the hardware circuit board. A power supply port matching the power socket is arranged on the housing. The power socket is connected to the XC7A35T main control chip, and the XC7A35T main control chip is powered through the power supply port.
[0015] In the above technical solution, further, a probe interface slot is integrated on the hardware circuit board, and an interface probe is plugged into the probe interface slot for collecting discrete signals of the IO expansion port and sending them to the XC7A35T main control chip.
[0016] Compared with the prior art, the beneficial effects of the present utility model are as follows:
[0017] A high-degree-of-freedom discrete level test device designed by the present utility model can achieve the purpose of directly performing interface tests with the workpieces to be measured. At the same time, it can count the duration of the discrete signals maintained by the workpieces to be measured, and perform acquisition and generate status parameter configuration through the XC7A35T main control chip; in the acquisition state, the acquisition format and level value can be configured, and in the generation state, the level value, signal frequency, output times, and output interval can be configured. Through the configuration of the level value, signal frequency, output times, and output interval, data interaction with the workpieces to be measured can be achieved. Description of the Drawings
[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following will briefly introduce the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present utility model, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.
[0019] Figure 1 It is a schematic diagram of the discrete level test device according to the embodiment of the present utility model.
[0020] Figure 2 It is an exploded view of the discrete level test device.
[0021] Figure 3 It is a circuit connection block diagram inside the discrete level test device.
[0022] Figure 4 It is a circuit diagram of the XC7A35T main control chip.
[0023] Figure 5 For Figure 3 The enlarged view at position A in
[0024] Figure 6 For Figure 3 The enlarged view at position B in
[0025] Figure 7 For Figure 3 The enlarged view at position C in
[0026] 1. Housing; 2. Display screen; 3. Adjustable knob; 4. LED lamp; 5. Interface slot; 6. Interface slot wire; 7. Interface probe; 8. Push-button switch; 9. Power socket; 10. Probe interface slot; 11. Knob potentiometer; 12. Hardware circuit board; 13. Display screen interface slot. Detailed implementation
[0027] To make the objectives, technical solutions and advantages of the embodiments of the present utility model clearer, the technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are some, but not all, of the embodiments of the present utility model. Components of the embodiments of the present utility model usually described and illustrated in the drawings here can be arranged and designed in various different configurations.
[0028] Therefore, the following detailed description of the embodiments of the present utility model provided in the drawings is not intended to limit the scope of the claimed present utility model, but merely represents selected embodiments of the present utility model. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts fall within the scope of protection of the present utility model.
[0029] Embodiment 1
[0030] This embodiment provides a discrete level testing device, including a host computer and a discrete level testing device main body. The host computer is used to issue commands and receive and display status information. The functions of the host computer have been disclosed in "Research on High-Degree-of-Freedom Discrete Level Testing Tools Based on FPGA". It is used to send level signal output instructions, PWM waveform generation instructions, and signal maintenance time measurement instructions. This technology belongs to mature technology. This application does not improve the host computer and directly applies the previously disclosed technology in the research to this application. Moreover, the improvement of this application is not in the software part, and its core lies in the design of the structure of the discrete level testing device.
[0031] As Figure 1-3 shown, a discrete level testing device includes a housing. An interface slot is provided on the housing, and an interface slot wire can be plugged into the interface slot. The discrete level testing device establishes communication with the device under test through the interface slot wire and realizes signal generation.
[0032] A hardware circuit board is arranged inside the housing. An XC7A35T main control chip is integrated on the hardware circuit board. The XC7A35T main control chip generates and collects discrete levels according to the commands received from the host computer.
[0033] The hardware circuit board is also integrated with a clock source, an IO expansion port, a USB interface, a JTAG download port, and a FLASH storage module. The clock source, the IO expansion port, the USB interface, the JTAG download port, and the FLASH storage module are all connected to the XC7A35T main control chip. After the host computer configures the instruction parameters and waveform parameters, different encoded waveform displays are performed, and the configuration instructions are sent to the XC7A35T main control chip, which then analyzes the quality and reports the status information. Among them, discrete signals are output at the corresponding IO ports. The functions of this part have not been improved in this application, and the technical idea of "Research on High-Degree-of-Freedom Discrete Level Testing Tools Based on FPGA" is directly used.
[0034] Among them, the IO expansion port is used for the generation and transmission of discrete signals (supporting the generation of differential signals, and can select the corresponding level mode for 3.3V or 5V output).
[0035] The USB interface realizes the communication and debugging between the discrete level testing device and the host computer.
[0036] The JTAG download port is used for the firmware update and upgrade of the discrete level testing device.
[0037] The XC7A35T main control chip uses the XC7A35TFGG484 type FPGA chip of Xilinx Corporation, with 33,280 logic resources and 250 available I / O pins.
[0038] A key switch, an LED light, a display screen, and an adjustable knob are respectively arranged on the shell. The internal hardware circuit board is integrated with a display screen interface slot, a power supply socket, a probe interface slot, a knob potentiometer, and an interface slot. The back of the key switch is located inside the shell and is connected to the XC7A35T main control chip for device startup. The back of the LED light is connected to the XC7A35T main control chip for status display, and the method is: flashing at a time interval of 1s. The back of the display screen is located inside the shell and is set on the display screen interface slot and is connected to the XC7A35T main control chip for displaying the configured signals and waveforms. The back of the adjustable knob is connected to the knob potentiometer, and the knob potentiometer is connected to the XC7A35T main control chip for adjusting the level value, signal frequency, output times, and output interval parameters. Interface probes can be inserted into the probe interface slot for signal acquisition. The power supply socket is connected to the XC7A35T main control chip and is connected to the power supply through the power supply port on the shell to supply power to the entire device.
[0039] The circuit diagram of the XC7A35T main control chip is as Figure 4-7As shown in the figure, the U_serlia_bytes module performs serial-to-parallel conversion on the collected discrete data and the discrete quantities sent by the host computer. The XC7A35T main control chip collects the discrete signals of the IO ports, performs serial-to-parallel conversion on them, and uploads the bytes to the host computer. The XC7A35T main control chip receives the discrete quantity bytes from the host computer and converts them into discrete quantities for output at the IO ports.
[0040] After the firmware of the XC7A35T main control chip is loaded, the U_tongbu module divides the frequency of the local crystal oscillator clock (50 MHz) through the parameter setting command sent by the host computer to generate a synchronization signal and a double-frequency signal.
[0041] The U_sel_dianping_in module receives the sending instruction from the host computer, sets the level of the discrete signal, selectively inputs and outputs the discrete signal levels of the IO ports (including 5V, 3V, etc.), and sends the read-back result of the corresponding instruction to the host computer.
[0042] The U_signal_check module counts the duration of the high-level signal input to the IO port. After the FPGA receives the command from the host computer to count the high-level duration signal, it detects the signal LED flashing, counts the duration of the first high-level signal appearing at the IO port, and sends the time count value to the host computer, and the LED indicator light goes out.
[0043] The U_wave_cj module collects and counts the discrete information of the IO ports according to the discrete signal characteristics (encoding method, level parameters, synchronization signal, discrete signal frame header, frame tail, and corresponding length, etc.) sent by the host computer, and sends the result back to the host computer; generates the corresponding PWM waveform for the frequency, duty cycle, and number of pulses in the command and outputs it. At the same time, when it detects that the frequency or duty cycle of the PWM waveform changes, it automatically reports the frequency and duty cycle to the host computer.
[0044] The U_wave_cs module outputs discrete signals at the corresponding IO ports according to the discrete signal characteristics (encoding method, level parameters, synchronization signal, mode, discrete signal frame header, frame tail, and corresponding length, etc.) sent by the host computer.
[0045] The U_xintiao module displays the LED indicator light for the normal operation of the XC7A35T main control chip. After the initialization is completed, the FPGA generates a clock frequency division output of 2 Hz to the LED indicator light. When the XC7A35T main control chip operates normally, the LED indicator light flashes at a time interval of 1 s.
[0046] After the XC7A35T main control chip is initialized, the U_zijian module performs self-check on the serial communication function. The FPGA sends a serial self-check request to the host computer through the serial port. When the host computer's returned self-check response is received normally, the LED indicator lights up; otherwise, it goes out.
[0047] After receiving the host computer's level parameter setting command, the U_sel_dianping_out module selectively inputs and outputs the discrete signal levels of the IO ports (including 3.3V, 5V, etc.).
[0048] The working principle is as follows:
[0049] During interface testing, the discrete level testing device is connected to the host computer through the USB interface and to the tested tooling through the interface slot line. The discrete level testing device and the tested tooling are powered on. The XC7A35T main control chip generates a synchronization signal as the minimum waveform segment of the discrete signal, and at the same time, according to the waveform instruction frame sent by the host computer, customizes the waveform generation or acquisition for the external interface protocol format of the tested tooling.
[0050] In the waveform generation mode, the XC7A35T main control chip outputs discrete signals on the corresponding IO ports according to the discrete signal characteristics (encoding method, level parameter, synchronization signal, output mode, PWM parameter, discrete signal frame header, frame tail, and corresponding length, etc.) sent by the host computer. The discrete signals are transmitted to the tested tooling through the interface slot line;
[0051] In the signal acquisition mode, the discrete level testing device is connected to the tested tooling through the interface probe. The XC7A35T main control chip realizes the acquisition of discrete level signals with any frequency and length of the tested tooling according to the discrete signal acquisition parameters sent by the host computer and reports the corresponding status of the tested tooling to the host computer.
[0052] The above is only a preferred embodiment of the present invention and does not impose any limitation on the present invention. Any simple modification, change, and equivalent change made to the above embodiments according to the technical essence of the invention still fall within the protection scope of the technical solution of the present invention.
Claims
1. A discrete level testing device, characterized in that, The discrete level test device establishes communication with the tooling under test through the interface slot line and realizes signal generation. The discrete level test device includes a housing, and a hardware circuit board is arranged inside the housing. An XC7A35T main control chip is integrated on the hardware circuit board. The XC7A35T main control chip generates and collects discrete levels according to the commands received from the host computer.
2. The discrete level testing device according to claim 1, wherein, An LED lamp is also integrated on the hardware circuit board. The LED lamp is connected to the XC7A35T main control chip for status display, and the body of the LED lamp protrudes outside the housing.
3. The discrete level testing device according to claim 2, wherein An adjustable knob is arranged on the housing. A rotary potentiometer is also integrated on the hardware circuit board. The rotary potentiometer is respectively connected to the XC7A35T main control chip and the adjustable knob, and is used to adjust the level value, signal frequency, output times, and output interval.
4. The discrete level testing device according to claim 3, characterized in that, A display screen is arranged on the housing. The back of the display screen is connected to the display screen interface slot on the hardware circuit board, and is used to display the configured signals and waveforms.
5. A discrete level testing device according to claim 4, characterized in that, A key switch is also arranged on the housing. The back of the key switch is integrated on the hardware circuit board and is connected to the XC7A35T main control chip.
6. A discrete level testing device according to claim 5, characterized in that, An interface slot is also integrated on the hardware circuit board. The interface slot is respectively connected to the XC7A35T main control chip, and the interface slot is used to connect the interface plug wire.
7. A discrete level testing device according to claim 6, characterized in that, A clock source, an IO expansion port, a USB interface, a JTAG download port, and a FLASH storage module are also integrated on the hardware circuit board.
8. A discrete level testing device according to claim 7, characterized in that, A power supply socket is integrated on the hardware circuit board. A power supply port matching the power supply socket is arranged on the housing. The power supply socket is connected to the XC7A35T main control chip to provide power to the XC7A35T main control chip through the power supply port.
9. A discrete level testing device according to claim 8, wherein A probe interface slot is integrated on the hardware circuit board. An interface probe is plugged on the probe interface slot, and is used to collect the discrete signals of the IO expansion port and send them to the XC7A35T main control chip.