Scan chain circuit

Abstract

A scan chain circuit includes a scan chain including a cell structure, where the cell structure includes N stages, where N is a complex number, and each stage is configured to store a bit. The circuit further includes S multiplexers operably coupled to the scan chain, where S is a complex number, and S is determined by N / M, where M represents a diagnostic resolution. The multiplexers are each configured to receive a respective one of the S control signals to selectively bypass a respective subset of the stages.

Description

Technical Field

[0001] This creation relates to a scan chain circuit, and more particularly to a scan chain circuit with multi-bit cells. Background Art

[0002] Integrated circuits (ICs) typically achieve densities of millions of gates per wafer, which presents particularly difficult test challenges. ICs are typically designed by combining predefined standard functional blocks called core cells from various sources with discrete logic to perform the required functions or groups of functions. Although the core cells may come with standard test vectors or test strategies, their internal connections to each other within the IC are typically not accessible from the pins of the IC, resulting in the inapplicability of standard tests and complicating the test process. Summary of the Utility Model

[0003] Embodiments of the present disclosure provide a scan chain circuit, including: a scan chain including a cell structure, where the cell structure includes N stages, where N is a complex number, and each stage is configured to store one bit; S multiplexers operatively coupled to the scan chain, where S is a complex number, and S is determined by N / M, where M represents the diagnostic resolution; wherein each of the multiplexers is configured to receive a corresponding one of the S control signals to selectively bypass a corresponding subset of these stages.

[0004] In some embodiments, M is a complex number.

[0005] In some embodiments, the number of the subset of the N stages to be bypassed is equal to M.

[0006] In some embodiments, the number of combinations of the S control signals is equal to S + 1.

[0007] In some embodiments, a first multiplexer among the multiplexers has: a first input terminal connected to an output terminal of a second multiplexer among the multiplexers; a second input terminal connected to an output terminal of the corresponding subset of the N stages; and an output terminal connected to a first input terminal of a third multiplexer among the multiplexers; wherein the second multiplexer, the first multiplexer, and the third multiplexer are sequentially connected in a direction from a scan input terminal of the scan chain to a scan output terminal of the scan chain; when the control signal received by the first multiplexer is in a first logic state, the first multiplexer is configured to couple the output terminal of the corresponding subset of the N stages to the first input terminal of the third multiplexer; when the control signal received by the first multiplexer is in a second logic state, the first multiplexer is configured to couple the output terminal of the second multiplexer to the first input terminal of the third multiplexer; the corresponding subset of the N stages is bypassed.

[0008] In some embodiments, it is determined that a defect is located at any position in the subset of the N levels based at least on comparing a first data pattern and a second data pattern, wherein the first data pattern and the second data pattern are unloaded via the scan chain based on a first combination of the control signals and a second combination of the control signals, respectively; and only one bit differs between the first combination of the control signals and the second combination of the control signals.

[0009] Another embodiment of the present disclosure provides a scan chain circuit, including: a scan chain including cell structures, wherein each cell structure includes N levels, where N is a complex number, and each level is configured to store one bit; S multiplexers operatively coupled to the N levels, where S is a complex number and S is a factor of N; and wherein each of the multiplexers is configured to receive a corresponding control signal to selectively bypass a subset of the corresponding levels.

[0010] In some embodiments, S is determined by N / M, where M represents diagnostic resolution.

[0011] In some embodiments, a first multiplexer, a second multiplexer, and a third multiplexer among the multiplexers are sequentially connected in a direction from a scan input end of the scan chain to a scan output end of the scan chain; each of the plurality of multiplexers has: a first input end, a second input end, and an output end; wherein the first input end of the first multiplexer is coupled to the scan input end, the second input end of the first multiplexer is connected to an output end of a first subset of the N levels, and the output end of the first multiplexer is connected to the first input end of the second multiplexer; wherein the second input end of the second multiplexer is connected to an output end of a second subset of the N levels, and the output end of the second multiplexer is connected to the first input end of the third multiplexer; and wherein the second input end of the third multiplexer is connected to an output end of a third subset of the N levels, and the output end of the third multiplexer is coupled to the scan output end.

[0012] In some embodiments, the number of combinations of the S control signals received by the multiplexers is equal to S + 1. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The following detailed description is presented in conjunction with the accompanying drawings to provide a complete disclosure. It should be noted that, in accordance with the general practice in the industry, the drawings are not necessarily drawn to scale. In fact, the dimensions of the elements may be arbitrarily enlarged or reduced for clarity of illustration.

[0014] Figure 1 A block diagram of an example integrated circuit including a circuit under test and a scan chain is shown in accordance with some embodiments.

[0015] Figure 2 Schematic diagram of an example scan chain according to some embodiments is shown.

[0016] Figure 3 is according to some embodiments Figure 2 Schematic diagram of various operating states of the scan chain of

[0017] Figure 4 is according to some embodiments Figure 2 Schematic diagram of various operating states of the scan chain of

[0018] Figure 5 Shows a flowchart of an example method for testing Figure 2 the scan chain according to some embodiments.

[0019] Figure 6 Schematic diagram of another example scan chain according to some embodiments is shown.

[0020] Figure 7 is according to some embodiments Figure 6 Schematic diagram of various operating states of the scan chain of

[0021] Figure 8 Shows a flowchart of an example method for testing Figure 6 the scan chain according to some embodiments.

[0022] Figure 9 Schematic diagram of yet another example scan chain according to some embodiments is shown.

[0023] Figure 10 Schematic diagram of yet another example scan chain according to some embodiments is shown.

[0024] Figure 11 Schematic diagram of an example computer system according to some embodiments is shown.

[0025] Wherein, the reference numerals are explained as follows:

[0026] 100: Circuit

[0027] 102: Circuit to be tested

[0028] 104: Scan chain test circuit (scan chain)

[0029] 105: Input signal

[0030] 107: Output signal

[0031] 109: Data signal

[0032] 111: Scan input signal

[0033] 121: Scan output signal

[0034] 400, 700: Table

[0035] 1100: Computer device

[0036] 1103: Computing unit

[0037] 1105: Processing unit

[0038] 1107: System memory

[0039] 1109: Read-only memory

[0040] 1111: Random access memory

[0041] 1113: Bus

[0042] 1115: Disk drive

[0043] 1117: Removable disk drive

[0044] 1119: Optical disc drive

[0045] 1121: Flash memory card

[0046] 1123: Input device

[0047] 1125: Output device

[0048] 1127: Network interface

[0049] 500, 800: Method

[0050] 501, 503, 515: Column

[0051] 602, 902, 1002: Shadow scan chain

[0052] 200, 600, 900, 1000: Scan chain

[0053] 1004-1, 1004-2,..., 1004-10: Scan flip-flop circuit

[0054] 1010-1 to 1010-4: Multiplexer

[0055] 1020-1 to 1020-4: Functional circuit

[0056] 104-1, 104-2, 104-3: Scan flip-flop circuit

[0057] 204-1, 204-2, 204-3, 204-4: Scan flip-flop circuit

[0058] 210-0 to 210-3: Multiplexer

[0059] 401, 403, …, 409: Columns

[0060] 502~514: Operations

[0061] 505, 507, 509, 511, 513: Arrows

[0062] 604-1, 604-2, …, 604-7: Scan flip-flop circuits

[0063] 610-1~610-4: Multiplexers

[0064] 904-1, 904-2, ..., 904-10: Scan flip-flop circuits

[0065] 910-1~910-4: Multiplexers

[0066] A, B1~B8, C, D: Stages

[0067] Mode_Cntl: Control signal

[0068] P0~P4: Chain test mode

[0069] S0~S3: Control signals

[0070] SI: Input signal Detailed implementation manners

[0071] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. The following disclosure describes specific examples of each component and its configuration manner to simplify the description. Of course, these specific examples are not used for limitation. For example, if the present disclosure describes that a first feature is formed on or above a second feature, that is, it may include an embodiment in which the above first feature and the above second feature are in direct contact, and may also include an embodiment in which additional features are formed between the above first feature and the above second feature, so that the above first feature and the second feature may not be in direct contact. In addition, the following different examples may reuse the same reference symbols and / or marks. These repetitions are for the purpose of simplification and clarity, and are not used to limit a specific relationship between the different embodiments and / or structures discussed.

[0072] In addition, there are terms related to space. For example, "below", "under", "lower", "above", "higher" and similar terms are used to facilitate the description of the relationship between one element or feature and another element or feature in the drawing. These space-related terms are intended to cover different orientations of the device in use or operation, in addition to the orientation shown in the drawing. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the space-related terms used here can be interpreted in the same way accordingly.

[0073] According to Moore's Law, the number of transistors on an integrated circuit doubles every two years. Although such a high packaging density allows for more functions to be integrated per unit area of the integrated circuit, as the packaging density continues to increase, it becomes increasingly difficult for foundries to manufacture defect-free integrated circuits. This dilemma highlights the importance of Design-for-Testability (DFT) in integrated circuit design. A scan chain is one of various DFT techniques and can be used to test part or all of an integrated circuit. A scan chain typically includes multiple flip-flops that are shifted to set the integrated circuit in a given state and determine whether each part of the integrated circuit is operating correctly. However, the scan chain is effective only when the scan chain itself is operational and does not contain defects. Defects in the scan chain may prevent the correct testing of the integrated circuit because it may prevent the circuit from being set in a given state.

[0074] Recently, the multi-bit flip-flop (MBFF) technology has been introduced as a method to reduce power consumption and wafer area during the physical implementation phase of the integrated circuit development process. This technology combines multiple single-bit flip-flops into a single multi-bit flip-flop, sometimes referred to as a multi-bit cell structure or multi-bit cell. A scan chain including multi-bit cells can be tested by existing bidirectional scan techniques that typically treat each multi-bit cell as a single unit. In this way, the diagnostic resolution will be adversely affected because if a multi-bit cell is suspect, the existing bidirectional scan techniques are required to report all bits of the multi-bit cell as suspect. In other words, the diagnostic resolution is essentially limited by the number of bits in the multi-bit cell (e.g., has a lower limit). Therefore, existing scan techniques are not entirely satisfactory in some aspects.

[0075] The present disclosure provides various embodiments of a scan chain having one or more multi-bit cells and a method for testing the same. In one embodiment, a scan chain as disclosed in the present disclosure includes at least one multi-bit cell, which can be implemented as any of various multi-bit flip-flops. A multi-bit cell generally consists of multiple flip-flops. In addition to a clock (CLK), a scan input (SI), and a scan enable (SE) pin, a multi-bit cell can have multiple input (D) pins and the same number of output (Q) pins. A multi-bit cell has multiple (N) cell stages, and each cell stage can store one (data) bit. Further, the disclosed scan chain includes multiple (S) multiplexers, the number of which can be flexibly adjusted according to a diagnostic resolution (M). For example, the parameter S can be determined as N / M. In one embodiment, the parameter M can be any factor of the parameter N. Each multiplexer can be controlled by a corresponding control signal to bypass a corresponding subset (number) of cell stages equal to the diagnostic resolution (M).

[0076] By controlling the multiplexers through multiple (P) chain test modes, defects in any cell stage can be accurately detected or otherwise determined, and each chain test mode represents a corresponding combination of control signals. Thus, each chain test mode can be configured to bypass a corresponding subset (number) of cell stages that can be an integer multiple of the parameter M. In some embodiments, the parameter P is equal to S + 1. Thus, based on the data pattern that is first recognized as passing later (unloaded by the scan chain based on a corresponding one of the P chain test modes), the defect location can be precisely determined to a flexible diagnostic resolution (e.g., a certain cell stage). Observe one or more failing data patterns (unloaded by the scan chain according to one or more corresponding patterns among the P chain test modes). Thus, even if there are defective stages or bits, the multi-bit cell as a whole will not be excluded as a defective cell. Instead, the defective stage of the multi-bit cell on the disclosed scan chain can be accurately identified. Further, the diagnostic resolution of the scan chain can be flexibly adjusted and is not limited by the (stage) size of the included multi-bit cells.

[0077] Figure 1 A block diagram of an example circuit (scan chain circuit) 100 according to one embodiment is shown. The circuit 100 includes a circuit under test 102 and a scan chain test circuit (sometimes referred to as a scan chain) 104. Figure 1 It is shown that the circuit under test 102 and the scan chain 104 are two different and independent modules. In some embodiments, the circuit under test 102 and the scan chain test circuit 104 can be integrated together.

[0078] In various embodiments, the circuit under test 102 includes a combinational logic circuit of a plurality of interconnected logic gates, and the scan chain 104 includes one or more scan flip-flop circuits, such as scan flip-flop circuits 104-1, 104-2, 104-3, etc., coupled to each other in a chain. According to some embodiments of the present disclosure, at least one of the flip-flop circuits in the scan chain 104 is configured to store a plurality of bits, which is a multi-bit flip-flop. In the following description, such a multi-bit flip-flop is also referred to as a multi-bit (MB) unit, and a flip-flop configured to store a single bit is also referred to as a single-bit (SB) unit.

[0079] More specifically, in Figure 1 each scan flip-flop circuit (104-1, 104-2, 104-3, etc.) is coupled to a corresponding subset of the logic gates of the circuit under test 102. The scan chain 104 is configured to switch between at least two modes: a normal operation mode and a scan test mode. When the scan chain 104 operates in the normal operation mode, the scan chain 104 receives a data signal 109, and the circuit under test 102 normally generates its output signal 107 in response to the input signal 105. When the scan chain 104 operates in the scan test mode, the scan chain 104 receives a scan input (SI) signal 111 and generates a scan output (SO) signal 121. Generally, a defect in one or more of the scan flip-flop circuits (i.e., one or more scan flip-flop circuits) can be detected by comparing one or more differences between the SI signal 111 and the SO signal 121 to identify a faulty flip-flop circuit in the scan chain 104. And such a flip-flop circuit can be used to identify which corresponding subset of the logic gates has a fault. In addition, if the defect is presented by at least one scan flip-flop circuit (i.e., an MB unit), the more accurate location of the defect can also be detected based on the present disclosure. Details will be described later.

[0080] Figure 2 FIG. shows a schematic diagram of an exemplary scan chain 200 according to an embodiment. The scan chain 200 can be Figure 1 the implementation of the scan chain 104 shown. For example, the scan chain 200 is operatively coupled to a circuit under test not depicted in Figure 2 for the sake of simplicity. In an embodiment of the present disclosure, the scan chain 200 includes at least one MB unit, which includes a plurality of stages to store a plurality of data bits.

[0081] As shown in the figure, the scan chain 200 includes scan flip-flop circuits 204-1, 204-2, 204-3, and 204-4 connected in series. The scan chain 200 itself can be tested in a scan test mode, in which the scan input (SI) signal received by the scan chain 200 is compared with the scan output (SO) signal generated by the scan chain 200. Such SI and SO signals can also be referred to as a loaded data pattern and an unloaded data pattern, respectively. In Figure 2 the example shown, the scan flip-flop circuits 204-1, 204-3, and 204-4 are all SB units, while the scan flip-flop circuit 204-2 is an MB unit. Further in Figure 2 the example of, the multi-bit scan flip-flop circuit 204-2 includes a plurality of (cell) stages, which are respectively denoted as "B1", "B2", "B3", "B4", "B5", "B6", "B7", and "B8". Each stage is configured to store one data bit. For consistency, the single-bit scan flip-flop circuits 204-1, 204-3, and 204-4 are respectively denoted as stages "A", "C", and "D".

[0082] A plurality of (S) multiplexers operatively coupled to the multi-bit scan flip-flop circuit 204-2. Each multiplexer corresponds to a respective subset of the stages included in the multi-bit scan flip-flop circuit 204-2. Specifically, when the scan chain 200 operates in a scan test mode, each multiplexer can selectively bypass a respective subset of the stages. The parameter S is determined based on the number (N) of stages included in the multi-bit scan flip-flop circuit 204-2 and the diagnostic resolution (M). The diagnostic resolution (M) can be flexibly adjusted according to various operating parameters (such as power consumption, performance orientation, etc.) of the scan chain 200 (or the circuit under test operatively coupled). According to an embodiment of the present disclosure, the parameter S can be determined as

[0083] In Figure 2In the illustrated embodiment, the multi-bit scan flip-flop circuit 204-2 has 8 stages (N = 8). When the diagnostic resolution (M) is configured to 2, the scan chain 200 can thus include 4 (S = 8 / 2) multiplexers coupled to the multi-bit scan flip-flop circuit 204-2, such as multiplexers 210-0, 210-1, 210-2, and 210-3. Each of the multiplexers 210-0 to 210-3 can correspond to (e.g., bypass) a respective subset of stages. For example, multiplexer 210-0 can correspond to (e.g., bypass) stages B1 and B2; multiplexer 210-1 can correspond to (e.g., bypass) stages B3 and B4; multiplexer 210-2 can correspond to (e.g., bypass) stages B5 and B6; multiplexer 210-3 can correspond to (e.g., bypass) stages B7 and B8.

[0084] In addition, each of the multiplexers 210-0 to 210-3 has two inputs and one output, and each of the multiplexers 210-0 to 210-3 is controlled by a respective control signal to selectively output one of the received input signals. For example, multiplexer 210-0 has a first input configured to receive a first signal output from stage A, a second input configured to receive a second signal output from stage B2, and an output configured to selectively output one of the following based on control signal S0: the first signal or the second signal. In one aspect of the present disclosure, when control signal S0 is provided as logic 1, multiplexer 210-0 outputs the first signal; when control signal S0 is provided as logic 0, multiplexer 210-0 outputs the second signal, as Figure 2 shown. In other words, multiplexer 210-0 is configured to bypass the corresponding stages B1 and B2 in response to the corresponding control signal S0 being pulled high. Similarly, multiplexer 210-1 is configured to bypass the corresponding stages B3 and B4 in response to the corresponding control signal S1 being pulled high. Multiplexer 210-2 is configured to bypass the corresponding stages B5 and B6 in response to the corresponding control signal S2 being pulled high. Multiplexer 210-3 is configured to bypass the corresponding stages B7 and B8 in response to the corresponding control signal S3 being pulled high.

[0085] In various embodiments of the present disclosure, the number (P) of combinations and configurations of control signals S0 to S3 (which may also be referred to as a chain test pattern) is determined to be S + 1. In addition, the chain test patterns may be incrementally changed from each other in a certain order, and the chain test patterns may be applied to multiplexers 210-0 to 210-3 in the same order. For example, a first chain test pattern (P0) having four bits for control signals S0, S1, S2, S3 respectively may be provided as "0000"; a second chain test pattern (P1) having four bits for control signals S0, S1, S2, S3 respectively may be provided as "0001"; a third chain test pattern (P2) having four bits for control signals S0, S1, S2, S3 respectively may be provided as "0011"; a fourth chain test pattern (P3) having four bits for control signals S0, S1, S2, S3 respectively may be provided as "0111"; a fifth chain test pattern (P4) having four bits for control signals S0, S1, S2, S3 respectively may be provided as "1111".

[0086] As shown in the figure, the second chain test pattern P1 is incrementally changed by one bit from the first chain test pattern P0. The third chain test pattern P2 is incrementally changed by one bit from the second chain test pattern P1. The fourth chain test pattern P3 is incrementally changed by one bit from the third chain test pattern P2. The fifth chain test pattern P4 is incrementally changed by one bit from the fourth chain test pattern P3. Following this increasing order, the chain test patterns P0 to P4 are sequentially applied to multiplexers 210-0 to 210-3.

[0087] Figure 3A schematic diagram showing the respective states of the scan chain 200 when the chain test patterns P0 to P4 are sequentially applied to the multiplexers 210-0 to 210-3 (which are coupled to the multi-bit scan flip-flop circuit 204-2). According to an embodiment. As shown, when the chain test pattern P0 (0000) is applied to the multiplexers 210-0 to 210-3, no stage inside the multi-bit scan flip-flop circuit 204-2 is bypassed. Therefore, all stages AB1B2B3B4B5B6B7B8CD are observable (e.g., shifted data bits). Next, when the chain test pattern P1 (0001) is applied to the multiplexers 210-0 to 210-3, stages B7 and B8 inside the multi-bit scan flip-flop circuit 204-2 are bypassed. Therefore, only stages AB1B2B3B4B5B6__CD are observable (e.g., shifted data bits). Next, when the chain test pattern P2 (0011) is applied to the multiplexers 210-0 to 210-3, stages B5, B6, B7, B8 inside the multi-bit scan flip-flop circuit 204-2 are bypassed. Therefore, only stages AB1B2B3B4____CD are observable (e.g., shifted data bits). Next, when the chain test pattern P3 (01111) is applied to the multiplexers 210-0 to 210-3, stages B3, B4, B5, B6, B7, stage B8 inside the multi-bit scan flip-flop circuit 204-2 are bypassed. Therefore, only stages AB1B2____CD are observable (e.g., shifted data bits). Next, when the chain test pattern P4 (11111) is applied to the multiplexers 210-0 to 210-3, stages B1, B2, B3, B4, B5, B6, B7, B8 inside the multi-bit scan flip-flop circuit 204-2 are bypassed. Therefore, only stage A____CD is observable (e.g., shifted data bits).

[0088] In one embodiment, defects in any subset of stages or any grouped stages (e.g., B1B2, B3B4, B5B6, B7B8) can be precisely located by sequentially applying the chain test patterns P0 to P4 to the multiplexers 210-0 to 210-3. Refer to Figure 4 and in conjunction with Figure 3 , an example table 400 with multiple rows is depicted to illustrate the data patterns loaded into the scan chain 200 (SI signal) or unloaded from the scan chain 200 (SO signal). As Figure 4 shown, stage B3 has a defect stuck at 1. The term "stuck at 1" means that there is a defect in the inverter or cell stage where the cell stage can only output logic 1 regardless of the received input logic state. Figure 4The table provides a representative example. Therefore, it should be noted that the disclosed methods and structures allow for the detection of any various other defects on the scan chain (e.g., stuck-at-0, transition defects, etc.), and these situations are also within the scope of the present disclosure.

[0089] As Figure 4 shown, the SI signal (00000000000) is loaded into the scan chain 200. Assuming there are no defects in any stage AB1B2B3B4B5B6B7B8CD, the SO signal unloaded by the scan chain 200 should also appear as (00000000000). However, since stage B3 has a stuck-at-1 defect, this may not be the case. For example, in column 401, the chain test pattern P0 (0000) is first applied to multiplexers 210-0 to 210-3, where the SI signal remains (00000000000). Due to the stuck-at-1 defect in stage B3, each stage after stage B3 shows logic 1. Therefore, in column 403, the SO signal unloaded from the scan chain shows (11111111111), which means that if no stage is bypassed, the scan chain 200 fails the scan test (as Figure 3 shown). Next, the chain test pattern P1 (0001) is applied to multiplexers 210-0 to 210-3, where the SI signal remains (00000000000). Similarly, the SO signal is not (0000000--00), which means that even if stages B7 and B8 are bypassed, the scan chain 200 still fails the scan test (as Figure 3 shown). Next, the chain test pattern P2 (0011) is applied to multiplexers 210-0 to 210-3, where the SI signal remains (00000000000). Similarly, the SO signal is still not (00000----00), as shown in column 405, which means that even if stages B5 to B8 are bypassed, the scan chain 200 still fails the scan test (as Figure 3 shown).

[0090] Next, the chain test pattern P3 (0111) is applied to multiplexers 210-0 to 210-3, where the SI signal remains (00000000000). Different from the previously applied chain test patterns, the SO signal is now (000------00), as shown in column 407, which means that in the case where stages B3 to B8 are bypassed, the scan chain 200 passes the scan test (as Figure 3As shown. In one embodiment, once the chain test mode first generates a passing SO signal, the location of the defect can be determined. Specifically, it can be determined that the location of the defect exists in the packet level bypassed by such a chain test mode. In the above example, until P3 is applied, the chain test modes P0 to P2 have not generated any passing SO signals. Therefore, it can be determined that the defect exists in any one of stages B3 or B4 and is bypassed by the chain test mode P3. In some embodiments, the chain test mode P4 (1111) can still be applied to multiplexers 210-0 to 210-3, where the SI signal is still (00000000000), and the defect is even identified. As shown in column 409, the SO signal is now (0--------00) because the defective stage B3 or B4 has been bypassed and there are no defects in stages B1 or B2 (which are also bypassed).

[0091] Figure 5 FIG. 4 shows a flowchart of an example method 500 for testing a scan chain including at least one MB cell according to one embodiment. Method 500 can be used to test Figure 2 scan chain 200. Thus, the discussion of the operations of method 500 can refer to one or more components discussed above in Figures 2 - 4 . It should be noted that method 500 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that additional operations can be provided before, during, and after Figure 5 method 500. Some other operations are briefly described herein only.

[0092] According to some embodiments of the present disclosure, method 500 begins at operation 502, where a scan chain including at least one MB cell is provided. By way of example with scan chain 200, scan chain 200 includes a plurality of serially connected flip-flop circuits 204-1, 204-2, 204-3, 204-4, where flip-flop circuits 204-1, 204-3, 204-4 are each SB cells (one-bit flip-flops) including a single stage, and flip-flop circuit 204-2 is an MB cell (multi-bit flip-flop) including a plurality of stages.

[0093] In accordance with some embodiments of the present disclosure, method 500 proceeds to operation 504, where failing cells in the provided scan chain are identified. Various chain diagnostic techniques known in the art can be applied to identify such failing cells, such as software-based techniques, bidirectional (reversible) scan chain techniques, and the like. It should be noted that under this chain diagnostic operation, each flip-flop circuit is regarded as a unit, regardless of the number of bits it has. In other words, even if the flip-flop circuit 204-2 is an MB unit, the flip-flop circuit 204-2 is regarded as a scan unit unit, just like any one of the other flip-flop circuits 204-1, 204-3, 204-4 in the above example.

[0094] In accordance with some embodiments of the present disclosure, method 500 proceeds to operation 506 to determine whether the failing cell is an MB unit. If not (e.g., the failing cell is one of the SB units 204-1, 204-3, or 204-4), then method 500 can proceed to an end operation, where a defect on the scan chain has been identified and no further testing is required. However, if the failing cell is an MB unit (e.g., the failing cell is the MB unit 204-2), then method 500 can proceed to the following operations to identify which stage in the MB unit has a defect.

[0095] For example, in accordance with some embodiments of the present disclosure, method 500 can proceed to operation 508, where the failing MB unit is divided into several grouped stages. Continuing with the above example, the MB unit 204-2 has eight (N) single stages B1, B2, B3, B4, B5, B6, B7, B8, and each single stage can store a single data bit. Based on the diagnostic resolution (M), the MB unit 204-2 can be divided into a plurality (S) of grouped stages. For example, S = N / M = 4. When the MB unit 204-2 is divided into four grouped stages B1B2, B3B4, B5B6, B7B8, a corresponding number of multiplexers, such as multiplexers 210-0, 210-1, 210-2, 210-3, can be added to the scan chain 200. Each of the multiplexers 210-0 to 210-3 can correspond to (e.g., bypass) a corresponding grouped stage. For example, multiplexer 210-0 can bypass the grouped stage B1B2; multiplexer 210-1 can bypass the grouped stage B3B4; multiplexer 210-2 can bypass the grouped stage B5B6; multiplexer 210-3 can bypass the grouped stage B7B8.

[0096] Next, according to some embodiments of the present disclosure, method 500 may proceed to operation 510, where a plurality of chain test patterns are generated to control the added multiplexer. The number (P) of chain test patterns is equal to the number of multiplexers (or the number of grouping levels) plus one, i.e., S + 1. Further, according to some embodiments, each of the P chain test patterns has a plurality of bits corresponding to the number of multiplexers, i.e., each chain test pattern has S bits. The order of the bits of each chain test pattern may correspond to the relative positions of the multiplexers. For example, the bits (of each chain test pattern) are arranged in the order of the positions of the mapped multiplexers. Further still, the P chain test patterns may be assigned to change incrementally in order, e.g., changing one bit of the next chain test pattern from right to left.

[0097] In the above example, each of the P chain test patterns has four bits. The leftmost bit corresponds to multiplexer 210-0, the next bit from the left corresponds to multiplexer 210-1, the next bit from the right corresponds to multiplexer 210-2, and the rightmost bit corresponds to multiplexer 210-3. The first (or starting) P chain test pattern may be represented as (0000); the second P chain test pattern may be represented as (0001), which changes the rightmost bit in the first chain test pattern from 0 to 1; the third P chain test pattern may be represented as (0011), which changes the second bit from the right in the second chain test pattern from 0 to 1; the fourth P chain test pattern may be represented as (0111), which changes the third bit from the right in the third chain test pattern from 0 to 1; the fifth P chain test pattern may be represented as (1111), which changes the fourth bit from the right in the fourth chain test pattern from 0 to 1. In some embodiments, a logical 0 of the chain test pattern may indicate the corresponding multiplexer to not bypass the corresponding grouping level, and a logical 1 of the chain test pattern may indicate the corresponding multiplexer to bypass the corresponding grouping level.

[0098] In some embodiments, the order of operations 502 to 510 may be changed. For example, operations 508 and 510 may be performed after operation 502 and before operation 504. Thus, method 500 may have operations 502, 508, 510, 504, 506, 512, 514 executed in such an order. In another example, operation 508 may be performed after operation 502 and before operation 504. Thus, method 500 may have operations 502, 508, 504, 506, 510, 512, 514 executed in such an order.

[0099] Next, according to some embodiments of the present disclosure, method 500 may proceed to operation 512, in which the chain test modes are sequentially applied to the multiplexers of the scan chain. Still using the same example as above, the first to fifth chain test modes are sequentially applied to multiplexers 210-0 to 210-3. For example, during the load cycle of the SI signal into the scan chain 200, the first chain test mode (0000) is first applied to all four multiplexers 210-0 to 210-3. When the first chain test mode is applied, no stage of the scan chain 200 is bypassed. Therefore, the scan chain 200 has a total of 11 stages (AB1B2B3B4B5B6B7B8CD), and a total of 11 load cycles can be performed. After the load cycle, the data stored in each stage of the scan chain is unloaded as the SO signal. Based on the unloaded SO signal, it can be determined whether the scan chain 200 passes the scan test. In this case, the scan chain 200 fails the test. Next, the second chain test mode (0001) is applied to all four multiplexers 210-0 to 210-3. When the second chain test mode is applied, stages B7 and B8 are bypassed. Therefore, the scan chain 200 has a total of 9 stages (AB1B2B3B4B5B6__CD), and a total of 9 load cycles can be performed. Similarly, after the load cycle, the SO signal is checked relative to the SI signal to determine whether the scan chain 200 passes the test. In this example, the scan chain 200 still fails the test.

[0100] Following the same principle, the remaining chain test modes (the third, fourth, and fifth chain test modes) are sequentially applied to all four multiplexers 210-0 to 210-3, and after applying the mode during the time period of each chain test mode, the corresponding number of load cycles are performed to generate the corresponding SO signals. For example, when the third chain test mode (0011) is applied, a total of 7 load cycles are performed; when the fourth chain test mode (0111) is applied, a total of 5 load cycles are performed; when the fifth chain test mode (1111) is applied, a total of 3 load cycles are performed.

[0101] Next, according to an embodiment of the present disclosure, method 500 may proceed to operation 514, in which the faulty grouped stages of the MB cells are identified. In an embodiment of the present disclosure, the faulty grouped stages may be identified based on comparing the first unloaded data pattern and the second unloaded data pattern respectively generated by the first chain test mode and the second chain test mode. After applying the first chain test mode, the second chain test mode immediately following is applied to the scan chain. Specifically, when it is determined that the second unloaded data pattern (SO signal) passes the corresponding scan test for the first time (i.e., the first unloaded data pattern and all previous unloaded data patterns have failed), the grouped stages bypassed by the second chain test mode are determined to be defective.

[0102] In the example where there are defects in the previous group levels B3B4, the SO signals generated based on the first chain test mode (no group level bypassed), the second chain test mode (group levels B7B8 bypassed), and the third chain test mode (group levels B5B6 bypassed) do not pass the corresponding scan tests. However, when applying the next chain test mode immediately following (i.e., the fourth chain test mode), the group levels B3B4 are bypassed. As a result, the corresponding SO signals pass the scan tests. Therefore, it can be determined that the defect exists at the group levels B3B4.

[0103] Figure 6 A schematic diagram of an example scan chain 600 according to an embodiment is shown. The scan chain 600 is Figure 1 an embodiment of the scan chain 104 shown. For example, the scan chain 600 can be operatively coupled to a circuit under test (not shown in Figure 6 for the sake of brevity). In an embodiment of the present disclosure, the scan chain 600 includes at least one MB unit, and the MB unit includes multiple levels for storing multiple data bits.

[0104] As shown, the scan chain 600 includes serially connected scan flip-flop circuits 604-1, 604-2. The scan chain 600 itself can be tested in a scan test mode, in which the scan input (SI) signal received by the scan chain 600 is compared with the scan output (SO) signal generated by the scan chain 600. Such SI and SO signals are sometimes referred to as the load data mode and the unload data mode, respectively. In Figure 6 the example shown, the scan flip-flop circuit 604-1 is an SB unit, and the scan flip-flop circuit 604-2 is an MB unit. Further in Figure 6 the example, the multi-bit scan flip-flop circuit 604-2 includes multiple (unit) levels, respectively denoted as "B1", "B2", "B3", "B4". Each level is configured to store one data bit. For consistency, the single-bit scan flip-flop circuit 604-1 is denoted as level "A".

[0105] In one embodiment, the scan chain 600 may further include a shadow scan chain 602 connected in series to the scan flip-flop circuits 604-1, 604-2. In other words, the original scan chain (formed by the scan flip-flop circuits 604-1, 604-2) and the newly added shadow scan chain 602 may be combined into a single scan chain, such as the new scan chain 600. The shadow scan chain 602 is configured to observe (e.g., identify) defects that may exist at any stage of the multi-bit scan flip-flop circuit 604-2. The shadow scan chain 602 may include scan flip-flop circuits 604-3, 604-4, 604-5, 604-6, 604-7. Each of the scan flip-flop circuits 604-3 to 604-7 in the (shadow scan chain) may be a single-bit scan flip-flop circuit or an SB cell. Specifically, the scan flip-flop circuits 604-3, 604-4, 604-5, 604-6, 604-7 are respectively configured as shadow units / stages of stage B4, B3, B2, B1, A.

[0106] In other words, the scan flip-flop circuit 604-3 may repeat or otherwise replicate the data bits stored in stage B4. The scan flip-flop circuit 604-4 may repeat or otherwise replicate the data bits stored in stage B3. The scan flip-flop circuit 604-5 may repeat or otherwise replicate the data bits stored in stage B2. The scan flip-flop circuit 604-6 may repeat or otherwise replicate the data bits stored in stage B1. And the scan flip-flop circuit 604-7 may repeat or otherwise replicate the data bits stored in stage A. Thus, the data bits stored in stage B4 of the multi-bit scan flip-flop circuit 604-2 can be observed on the scan flip-flop circuit 604-3; the data bits stored in stage B3 of the multi-bit scan flip-flop circuit 604-2 can be observed on the scan flip-flop circuit 604-4; the data bits stored in stage B2 of the multi-bit scan flip-flop circuit 604-2 can be observed on the scan flip-flop circuit 604-5; the data bits stored in stage B1 of the multi-bit scan flip-flop circuit 604-2 can be observed on the scan flip-flop circuit 604-6; and the data bits stored in stage A (i.e., the single-bit scan flip-flop circuit 604-1) can be observed on the scan flip-flop circuit 604-7. Therefore, in Figure 6 (and the following discussion), the flip-flop circuits 604-3, 604-4, 604-5, 604-6, 604-7 are respectively denoted as stages "SB4", "SB3", "SB2", "SB1", "SA".

[0107] In one embodiment, the scan chain 600 (or the shadow scan chain 602) may further include multiplexers 610-1, 610-2, 610-3, 610-4. Each of the multiplexers 610-1 to 610-4 is configured to selectively output one of the first input signal or the second input signal received by it based on a common control signal (Mode_Cntl) received by all four multiplexers 610-1 to 610-4. The first input signal may be an output signal generated by a corresponding replicated stage of the original scan chain, and the second input signal may be an output signal generated by the previous stage of the shadow scan chain 602. When the control signal (Mode_Cntl) is configured as logic 1, the multiplexer may select the first input signal as its output signal; when the control signal is configured as logic 0, the multiplexer may select the second input signal as its output signal.

[0108] For example, in Figure 6 , the output of stage B3 and the output of the previous replicated stage SB4 (scan flip-flop circuit 604-3) are respectively connected to the two inputs of multiplexer 610-1. The output of stage B2 and the output of the previous replicated stage SB3 (scan flip-flop circuit 604-4) are respectively connected to the two inputs of multiplexer 610-2. The output of stage B1 and the output of the previous replicated stage SB2 (scan flip-flop circuit 604-5) are respectively connected to the two inputs of multiplexer 610-3. The output of stage A and the output of the previous replicated stage SB1 (scan flip-flop circuit 604-6) are respectively connected to the two inputs of multiplexer 610-4.

[0109] Referring to Figure 7 , an example table 700 with multiple columns is depicted to illustrate the data patterns loaded into the scan chain 600 (SI signal) or unloaded from the scan chain 600 (SO signal). As Figure 7 shown, stage B1 has a stuck-at-1 defect. The term "stuck-at-1" means that there is a defect in an inverter or a cell level, and the cell level can only output logic 1 regardless of the received input logic state. Figure 7 The table of

[0110] As shown in the figure, the SI signal (00000000000) is loaded into the scan chain 600. Assuming that there are no defects in any of the stages AB1B2B3B4SB4SB3SB2SB1SA, the SO signal unloaded from the scan chain 600 should present (00000000000). However, since stage B1 has a stuck-at-1 defect, this may not be the case. For example, in column 501 (Mode_Cntl is set to logic 0), the SI signal (00000000000) is loaded into the scan chain 600. Due to the stuck-at-1 defect in stage B1, each stage after stage B1 shows logic 1. Therefore, in column 503 (Mode_Cntl is set to logic 0), the SO signal unloaded from the scan chain shows (11111111111), which means that the scan chain 600 fails the scan test, but it is currently impossible to determine which stage has the defect.

[0111] Next, the control signal Mode_Cntl can be set to logic 1 to identify which stage has the defect. In some embodiments, when the control signal Mode_Cntl is set to logic 1, each of the multiplexers 610-1 to 610-4 is configured to select the input signal received directly from the corresponding stage inside the multi-bit scan flip-flop circuit 604-2 as its output signal, which allows the data bits stored in stage A of the (single-bit scan flip-flop circuit 604-1) and stages B1, B2, B3, B4 of the (multi-bit scan flip-flop circuit 604-2) to be copied to stages SA, SB1, SB2, SB3, SB4 respectively.

[0112] For example, in Figure 7 during the loading cycle 1 of the SI signal, the data bits stored in stage A and stage B1 are copied to stages SA and SB1 respectively, as shown by arrows 505 and 507. During the loading cycle 2 of the SI signal, the data bit stored in stage B2 is copied to stage SB2, as shown by arrow 509. During the loading cycle 3 of the SI signal, the data bit stored in stage B3 is copied to stage SB3, as shown by arrow 511. During the loading cycle 4 of the SI signal, the data bit stored in stage B4 is copied to stage SB4, as shown by arrow 513. After loading all the bits into stages A to B4 (e.g., 5 loading cycles), the data bits stored in the scan chain 600 (including the shaded scan chain 602) are unloaded as the SO signal, as shown in column 515.

[0113] In some embodiments, a first fault bit that is inconsistent with the SI signal (when counting in a direction opposite to the direction of loading the SI signal, i.e., from right to left) can be used to determine the location of a defect in the multi-bit scan flip-flop circuit 604-2. More specifically, the defect can be determined to be present in the replica stage (of the multi-bit scan flip-flop circuit 604-2) whose corresponding shadow scan chain replica stage presents the first fault bit. In Figure 7 the example of, the first fault bit is presented by the stage SB1 that replicates the data bit of stage B1. Thus, it can be determined that the defect is present in stage B1 within the multi-bit scan flip-flop circuit 604-2.

[0114] Figure 8 FIG. shows a flowchart of an example method 800 for testing a scan chain including at least one MB cell according to an embodiment. Method 800 can be used to test Figure 6 the scan chain 600. Thus, the discussion of the operations of method 800 can refer to one or more components discussed above in Figures 6 - 7 . It should be noted that method 800 is merely an example and is not intended to limit the present disclosure. Thus, it should be understood that additional operations can be provided before, during, and after Figure 8 the method 800, and some other operations are simply described herein.

[0115] According to some embodiments of the present disclosure, method 800 begins at operation 802, where a scan chain including at least one MB cell is provided. By way of example with scan chain 600, scan chain 600 includes a plurality of serially connected scan flip-flop circuits 604-1, 604-2, where scan flip-flop circuit 604-1 is an SB cell (single-bit flip-flop) including a single stage (e.g., stage A), and scan flip-flop circuit 604-2 is an MB cell (multi-bit flip-flop) including a plurality of stages (e.g., stages B1, B2, B3, B4).

[0116] According to some embodiments of the present disclosure, method 800 proceeds to operation 804, where a shadow scan chain is added to the original scan chain. The shadow scan chain is added (e.g., connected) to the original scan chain when it is recognized that the original scan chain has at least one MB cell. In some embodiments, the shadow scan chain may have a plurality of SB cells corresponding to the plurality of stages of the original scan chain. Continuing with the above example, the shadow scan chain 602 including flip-flop circuits 604-3 to 604-7 is connected to stage B4 of the original scan chain. The shadow scan chain also includes multiplexers 610-1 to 610-4, which are configured to copy the data bits stored by stages B3, B2, B1, A to flip-flop circuits 604-4, 604-5, 604-6, 604-7 respectively when activated. The flip-flop circuits 604-3, 604-4, 604-5, 604-6, 604-7 are thus referred to as stages SB4, SB3, SB2, SB1, SA respectively.

[0117] According to some embodiments of the present disclosure, method 800 proceeds to operation 806, where the multiplexers of the shadow scan chain are activated. Still with the same example here, multiplexers 610-1 to 610-4 are activated to copy the data bits stored by stages B3, B2, B1, A to stages SB3, SB2, SB1, SA respectively. For example, within the first load cycle of the SI signal, as long as multiplexer 610-4 is activated, the data stored by stage A can be copied to stage SA; during the second load cycle of the SI signal, as long as multiplexer 610-3 is activated, the data stored by stage B1 can be copied to stage SB1. During the third load cycle of the SI signal, as long as multiplexer 610-2 is activated, the data stored by stage B2 can be copied to stage SB2. During the fourth load cycle of the SI signal, as long as multiplexer 610-1 is activated, the data stored by stage B3 can be copied to stage SB3. Additionally, since stage SB4 is directly connected to stage B4, the data bit stored in stage B4 can be copied to stage SB4.

[0118] According to some embodiments of the present disclosure, method 800 proceeds to operation 808, where the faulty stage inside the MB cell can be identified. Referring to the same example above, after the SI signal has been loaded into all stages within the MB cell, the data bits stored by the scan chain 600 (along with the shadow scan chain 602) are unloaded as the SO signal. In some embodiments, when there is a defect in any stage within the MB cell, the defect can be identified based on the corresponding copy stage of the shadow scan chain that presents the first faulty bit on the SO signal. For example in Figure 7 , the first faulty bit is presented by stage SB1 that copies the data bit of stage B1. Thus, it can be determined that the defect exists in stage B1 within the MB cell 604-2.

[0119] Figure 9 FIG. shows a schematic diagram of an example scan chain 900 according to an embodiment. The scan chain 900 can be Figure 1 an embodiment of the scan chain 104 shown. For example, the scan chain 900 is operatively coupled to a circuit under test not shown for simplicity in Figure 9 . In one embodiment of the present disclosure, the scan chain 900 includes at least one MB cell, which includes multiple stages for storing multiple data bits.

[0120] As shown, the scan chain 900 includes scan flip-flop circuits 904-1, 904-2, 904-3, 904-4 connected in series. In Figure 9 the example shown, the scan flip-flop circuits 904-1, 904-3, 904-4 are all SB cells, while the scan flip-flop circuit 904-2 is an MB cell. Further in the example of the figure. Referring to Figure 9 , the multi-bit scan flip-flop circuit 904-2 includes multiple (cell) stages, respectively denoted as "B1", "B2", "B3", "B4". Each stage is configured to store one data bit. For consistency, the single-bit scan flip-flop circuits 904-1, 904-3, 904-4 are respectively denoted as stages "A", "C", and "D".

[0121] In one embodiment, the scan chain 900 may further include a shadow scan chain 902 to be coupled to the original scan chain formed by the scan flip-flop circuits 904-1 to 904-4. The original scan chain (formed by the scan flip-flop circuits 904-1 to 904-4) and the shadow scan chain 902, although having their respective scan input signals and scan output signals, can be coupled to each other to form a new scan chain 900. In other words, the original scan chain and the shadow scan chain are two independent scan chains. The shadow scan chain 902 is configured to observe (e.g., identify) defects present at any stage of the multi-bit scan flip-flop circuit 904-2. The shadow scan chain 902 may include scan flip-flop circuits 904-5, 904-5, 904-6, 904-7, 904-8, 904-9, 904-10. Each of the scan flip-flop circuits 904-5 to 904-10 in the (shadow scan chain) can be a one-bit flip-flop circuit or an SB cell. Specifically, the scan flip-flop circuits 904-7, 904-8, 904-9, 904-10 are respectively configured as shadow cells / stages of stages B1, B2, B3, B4.

[0122] In other words, the scan flip-flop circuits 904-7 can repeat or otherwise replicate the data bits stored in stage B1. The scan flip-flop circuits 904-8 can repeat or otherwise replicate the data bits stored in stage B2. The scan flip-flop circuits 904-9 can repeat or otherwise replicate the data bits stored in stage B3. The scan flip-flop circuits 904-10 can repeat or otherwise replicate the data bits stored in stage B4. Thus, in Figure 9 (and the discussion below), the flip-flop circuits 904-7, 904-8, 904-9, and 904-10 are respectively represented as stages "SB1", "SB2", "SB3", "SB4".

[0123] In one embodiment, the scan chain 900 (or the shadow scan chain 902) may further include multiplexers 910-1, 910-2, 910-3, 910-4. Each of the multiplexers 910-1 to 910-4 is configured to selectively output a signal as one of the first input signal or the second input signal received by it based on a common control signal (Mode_Cntl) received by all four multiplexers 910-1 to 910-4. The first input signal may be an output signal generated by a corresponding replication stage within the multi-bit scan flip-flop circuit 904-2, and the second input signal may be an output signal generated by the previous stage of the shadow scan chain 902. When the control signal (Mode_Cntl) is configured to logic 1, the multiplexer selects the first input signal as its output signal; when the control signal (Mode_Cntl) is configured to logic 0, the multiplexer selects the second input signal as its output signal.

[0124] For example, in Figure 9 , the output of stage B1 and the output of the previous stage (scan flip-flop circuit 904-6) are respectively connected to the two inputs of multiplexer 910-1. The output of stage B2 and the output of the previous stage SB1 (scan flip-flop circuit 904-7) are respectively connected to the two inputs of multiplexer 910-2. The output of stage B3 and the output of the previous stage SB2 (scan flip-flop circuit 904-8) are respectively connected to the two inputs of multiplexer 910-3. The output of stage B4 and the output of the previous stage SB3 (scan flip-flop circuit 904-9) are respectively connected to the two inputs of multiplexer 910-4.

[0125] In such a configuration, defects occurring in the MB unit (multi-bit scan flip-flop circuit 904-2) can be identified by identifying the faulty bits that appear on the scan output signal (SO') unloaded from the shadow scan chain 902. For example, when a faulty bit on the SO' signal is identified, it can be determined that the replicated stage in the MB unit corresponding to the replication stage (e.g., SB1, SB2, SB3, and / or SB4) presenting the faulty bit is the faulty bit in the MB unit.

[0126] Figure 10 Shows a schematic diagram of an example scan chain 1000 according to an embodiment. The scan chain 1000 may be Figure 1 An embodiment of the scan chain 104 shown. For example, the scan chain 1000 is operatively coupled to a circuit under test not shown for the sake of brevity in Figure 10 In an embodiment of the present disclosure, the scan chain 1000 includes at least one MB cell, which includes a plurality of stages to store a plurality of data bits.

[0127] As shown, the scan chain 1000 includes scan flip-flop circuits 1004-1, 1004-2, 1004-3, 1004-4 connected in series. In Figure 10 The example shown, the scan flip-flop circuits 1004-1, 1004-3, 1004-4 are all SB cells, while the scan flip-flop circuit 1004-2 is an MB cell. Further in the example of the figure. Referring to Figure 10 , the multi-bit scan flip-flop circuit 1004-2 includes a plurality of (cell) stages, respectively denoted as "B1", "B2", "B3", "B4". Each stage is configured to store a data bit. For consistency, the single-bit scan flip-flop circuits 1004-1, 1004-3, and 1004-4 are respectively denoted as stages "A", "C", "D".

[0128] In an embodiment, the scan chain 1000 may further include a shadow scan chain 1002 to be coupled to the original scan chain formed by the scan flip-flop circuits 1004-1 to 1004-4. The original scan chain (formed by the scan flip-flop circuits 1004-1 to 1004-4) and the newly added shadow scan chain 1002 can be coupled to each other as the new scan chain 1000 while having their respective scan input signals and scan output signals. In other words, the original scan chain and the shadow scan chain are two independent scan chains. The shadow scan chain 1002 is configured to observe (e.g., identify) defects present at any stage of the multi-bit scan flip-flop circuit 1004-2. The shadow scan chain 1002 may include scan flip-flop circuits 1004-5, 1004-6, 1004-7, 1004-8, 1004-9, 1004-10. Each of the scan flip-flop circuits 1004-5 to 1004-10 in the (shadow scan chain) may be a single-bit scan flip-flop circuit or an SB cell. Specifically, the scan flip-flop circuits 1004-7, 1004-8, 1004-9, 1004-10 are respectively configured as shadow cells / stages of stages B1, B2, B3, B4.

[0129] In other words, the scan flip-flop circuit 1004-7 can repeat or otherwise copy the data bits stored in stage B1. The scan flip-flop circuit 1004-8 can repeat or otherwise copy the data bits stored in stage B2. The scan flip-flop circuit 1004-9 can repeat or otherwise copy the data bits stored in stage B3. The scan flip-flop circuit 1004-10 can repeat or otherwise copy the data bits stored in stage B4. Thus, in Figure 10 (and the discussion below), the flip-flop circuits 1004-7, 1004-8, 1004-9, 1004-10 are respectively represented as stages "SB1", "SB2", "SB3", "SB4".

[0130] In one embodiment, the scan chain 1000 (or the shadow scan chain 1002) may further include multiplexers 1010-1, 1010-2, 1010-3, 1010-4. Each of the multiplexers 1010-1 to 1010-4 is configured to selectively output a signal as one of the first input signal or the second input signal it receives based on a common control signal (Mode_Cntl) received by all four multiplexers 1010-1 to 1010-4. The first input signal may be an output signal generated by a corresponding replication stage within the multi-bit scan flip-flop circuit 1004-2, and the second input signal may be a signal captured from a corresponding functional circuit (or logic). When the control signal (Mode_Cntl) is configured as logic 1, the multiplexer may select the first input signal as its output signal; when the control signal (Mode_Cntl) is configured as logic 0, the multiplexer may select the second input signal as its output signal.

[0131] For example, in Figure 10 , the output of stage B1 and the output of the corresponding functional circuit 1020-1 are respectively connected to the two inputs of multiplexer 1010-1. Multiplexer 1010-1 has an output connected to the data input (D) of stage SB1. The output of stage B2 and the output of the corresponding functional circuit 1020-2 are respectively connected to the two inputs of multiplexer 1010-2. Multiplexer 1010-2 has an output connected to the data input (D) of stage SB2. The output of stage B3 and the output of the corresponding functional circuit 1020-3 are respectively connected to the two inputs of multiplexer 1010-3. Multiplexer 1010-3 has an output connected to the data input (D) of stage SB3. The output of stage B4 and the output of the corresponding functional circuit 1020-4 are respectively connected to the two inputs of multiplexer 1010-4. Multiplexer 1010-4 has an output connected to the data input (D) of stage SB4.

[0132] In such a configuration, defects in the MB cells (multi-bit scan flip-flop circuits 1004-2) can be identified by recognizing faulty bits that appear on the scan output signal (SO') unloaded from the shadow scan chain 1002. For example, when a faulty bit on the SO' signal is recognized, it can be determined that the replicated stage in the MB cell corresponding to the replicated stage (e.g., SB1, SB2, SB3, and / or SB4) presenting the faulty bit is the faulty bit in the MB cell. Additionally, in some embodiments, when the control signal (Mode_Cntl) is configured to logic 1, bits from the MB cell can be replicated to the shadow scan chain 1002.

[0133] Various examples of the techniques of the present disclosure (e.g., method 500, method 800) can be implemented by a computer device, such as a programmable computer, executing software instructions. For example, a computer device can be made to execute a method for creating a test circuit in a circuit design to test a wafer manufactured according to the circuit design. Figure 11 An illustrative example of a computer device 1100 is shown. As shown, the computer device 1100 includes a computing unit 1103 having at least one processing unit (or processor) 1105 and a system memory 1107. The processing unit 1105 can be any type of programmable electronic device for executing software instructions. The system memory 1107 can include a read-only memory (ROM) 1109 and a random access memory (RAM) 1111. As will be understood by those of ordinary skill in the art, the read-only memory (ROM) 1109 and the random access memory (RAM) 1111 can store software instructions for execution by the processing unit 1105.

[0134] The processing unit 1105 and the system memory 1107 are directly or indirectly connected to one or more peripheral devices via a bus 1113 or an alternative communication structure. For example, the processing unit 1105 or the system memory 1107 can be directly or indirectly connected to one or more additional memory storage devices, such as "hard disk" disk drives 1115, removable disk drives 1117, optical disk drives 1119, and flash memory cards 1121, which belong to peripheral devices. The processing unit 1105 and the system memory 1107 can also be directly or indirectly connected to one or more input devices 1123 and one or more output devices 1125. The input devices 1123 can include, for example, a keyboard, a pointing device (such as a mouse, a touchpad, a stylus, a trackball, or a joystick), a scanner, a camera, and a microphone. The output devices 1125 can include, for example, a monitor / display, a photocopier, and a speaker. For various examples of the computer 1100, one or more of these components 1115 - 1125 that belong to peripheral devices can be housed internally with the computing unit 1103. Alternatively, one or more of these components 1115 - 1125 that belong to peripheral devices can be external to the housing of the computing unit 1103 and connected to the bus 1113 via, for example, a Universal Serial Bus (USB).

[0135] In some embodiments, the computing unit 1103 can be directly or indirectly connected to one or more network interfaces 1127 for communicating with other devices that make up a network. The network interface 1127 converts data and control signals from the computing unit 1103 into network messages according to one or more communication protocols, such as the Transmission Control Protocol (TCP) and the Internet Protocol (IP). Moreover, the interface 1127 can employ any suitable connection agent (or combination of agents) to connect to the network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art and are not discussed in more detail here.

[0136] It should be understood that the depicted computer 1100 is only an example and is not intended to limit the present disclosure. Embodiments of the techniques of the present disclosure can be implemented using one or more computer devices that include Figure 11 the components of the computer 1100 shown in, which include not only Figure 11 a subset of the components shown in,[ Figure 11 the embodiments or alternative combinations of components shown in, but also include Figure 11Components not shown in the figure. For example, embodiments of the technology of the present disclosure may be implemented using a multi-processor computer, multiple single-processor and / or multi-processor computers arranged in a network, or some combination of both.

[0137] In one embodiment, the scan chain circuit of the present disclosure includes: a scan chain including a cell structure, where the cell structure includes N stages, where N is a complex number, and each stage is configured to store one bit; S multiplexers operatively coupled to the scan chain, where S is a complex number and S is determined by N / M, where M represents the diagnostic resolution; wherein each of the multiplexers is configured to receive a corresponding one of the S control signals to selectively bypass a corresponding subset of these stages.

[0138] In another embodiment, in the scan chain circuit of the present disclosure, M is a complex number.

[0139] In another embodiment, in the scan chain circuit of the present disclosure, the number of this subset of the stages to be bypassed is equal to M.

[0140] In another embodiment, in the scan chain circuit of the present disclosure, the number of combinations of the S control signals is equal to S + 1.

[0141] In another embodiment, in the scan chain circuit of the present disclosure, the first multiplexer among these multiplexers has: a first input terminal connected to the output terminal of the second multiplexer among these multiplexers; a second input terminal connected to the output terminal of this corresponding subset of these stages; and an output terminal connected to the first input terminal of the third multiplexer among these multiplexers.

[0142] In another embodiment, in the scan chain circuit of the present disclosure, the second multiplexer, the first multiplexer, and the third multiplexer are connected in sequence along the direction from the scan input terminal of this scan chain to the scan output terminal of this scan chain.

[0143] In another embodiment, in the scan chain circuit of the present disclosure, when the control signal received by the first multiplexer is in the first logic state, the first multiplexer is configured to couple the output of this corresponding subset of these stages to the first input terminal of the third multiplexer.

[0144] In another embodiment, in the scan chain circuit of the present disclosure, when the control signal received by the first multiplexer is in the second logic state, the first multiplexer is configured to couple the output terminal of the second multiplexer to the first input terminal of the third multiplexer.

[0145] In another embodiment, in the scan chain circuit of the present disclosure, this corresponding subset of these stages is bypassed.

[0146] In another embodiment, the scan chain circuit of the present disclosure determines that a defect is located at any position in any of these subsets of these stages based at least on comparing a first data pattern and a second data pattern, wherein the first data pattern and the second data pattern are unloaded through the scan chain based on a first combination of these control signals and a second combination of these control signals, respectively.

[0147] In another embodiment, the scan chain circuit of the present disclosure, wherein the first combination of these control signals and the second combination of these control signals differ from each other by only one bit.

[0148] In one embodiment, the scan chain circuit of the present disclosure includes: a scan chain including cell structures, wherein the cell structure includes N stages, where N is a complex number, and each stage is configured to store one bit; S multiplexers operatively coupled to the N stages, where S is a complex number and S is a factor of N; wherein each of the multiplexers is configured to receive a corresponding control signal to selectively bypass a corresponding subset of the stages.

[0149] In another embodiment, the scan chain circuit of the present disclosure, wherein S is determined by N / M, where M represents diagnostic resolution.

[0150] In another embodiment, the scan chain circuit of the present disclosure, wherein the first multiplexer, the second multiplexer, and the third multiplexer among the multiplexers are sequentially connected in a direction from the scan input end of the scan chain to the scan output end of the scan chain.

[0151] In another embodiment, the scan chain circuit of the present disclosure, wherein each of the multiplexers has: a first input end, a second input end, and an output end; wherein the first input end of the first multiplexer is coupled to the scan input end, the second input end of the first multiplexer is connected to the output end of the first subset of the stages, and the output end of the first multiplexer is connected to the first input end of the second multiplexer; wherein the second input end of the second multiplexer is connected to the output end of the second subset of the stages, and the output end of the second multiplexer is connected to the first input end of the third multiplexer; and wherein the second input end of the third multiplexer is connected to the output end of the third subset of the stages, and the output end of the third multiplexer is coupled to the scan output end.

[0152] In another embodiment, the scan chain circuit of the present disclosure, wherein the number of combinations of the S control signals received by the multiplexers is equal to S + 1.

[0153] In another embodiment, the scan chain circuit of the present disclosure determines that a defect is located at any position in this subset of this stage based at least on comparing a first data pattern and a second data pattern, wherein the first data pattern and the second data pattern are unloaded through this scan chain based on a first combination of this control signal and a second combination of this control signal, respectively.

[0154] In another embodiment, the scan chain circuit of the present disclosure, wherein the first combination of these control signals and the second combination of these control signals differ from each other by only one bit.

[0155] In one embodiment, a method for testing a scan chain of the present disclosure includes: providing a scan chain including cell structures, wherein the cell structures include N stages, where N is a plural number, and each stage is configured to store one bit; determining a diagnostic resolution M; generating P chain test patterns, where P is a plural number, and each chain test pattern is configured to bypass one or more subsets of these stages; and determining that a defect is located at a position in any of these subsets of these stages based at least on comparing a first unloaded data pattern and a second unloaded data pattern, wherein the first unloaded data pattern and the second unloaded data pattern are generated by a first chain test pattern and a second chain test pattern among these chain test patterns, respectively; where P is determined by S + 1, and S is determined by N / M.

[0156] In another embodiment, the method for testing a scan chain of the present disclosure, wherein the first chain test pattern and the second chain test pattern differ from each other by only one bit.

[0157] As used in the present disclosure, the terms "about" and "approximately" generally mean plus or minus 10% of the stated value. For example, about 0.5 will include 0.45 and 0.55, about 10 will include 9 to 11, and about 1000 will include 900 to 1100.

[0158] The foregoing text outlines the features of many embodiments, enabling those of ordinary skill in the art to better understand the present disclosure from various aspects. Those of ordinary skill in the art should understand and can easily design or modify other processes and structures based on the present disclosure to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also understand that these equivalent structures do not depart from the creative spirit and scope of the present disclosure. Various changes, permutations, or modifications can be made to the present disclosure without departing from the creative spirit and scope of the present disclosure.

Claims

1. A scan chain circuit, characterized in that, Comprising: A scan chain including a cell structure, where the cell structure includes N stages, where N is a complex number, and each stage is configured to store one bit; S multiplexers operatively coupled to the scan chain, where S is a complex number, and S is determined by N / M, where M represents diagnostic resolution; Wherein each of the multiplexers is configured to receive a respective one of the S control signals to selectively bypass a respective subset of the N stages.

2. The scan chain circuit according to claim 1, wherein M is a complex number.

3. The scan chain circuit according to claim 1, characterized in that The number of the subset of the N stages that are bypassed is equal to M.

4. The scan chain circuit according to claim 1, wherein The number of combinations of the S control signals is equal to S + 1.

5. The scan chain circuit according to claim 1, wherein The first multiplexer among the multiplexers has: A first input terminal connected to the output terminal of the second multiplexer among the multiplexers; A second input terminal connected to the output terminal of the respective subset of the N stages; And An output terminal connected to the first input terminal of the third multiplexer among the multiplexers; The second multiplexer, the first multiplexer, and the third multiplexer are sequentially connected in a direction from the scan input terminal of the scan chain to the scan output terminal of the scan chain; When the control signal received by the first multiplexer is in a first logic state, the first multiplexer is configured to couple the output terminal of the respective subset of the N stages to the first input terminal of the third multiplexer; When the control signal received by the first multiplexer is in a second logic state, the first multiplexer is configured to couple the output terminal of the second multiplexer to the first input terminal of the third multiplexer; The respective subset of the N stages is bypassed.

6. The scan chain circuit according to claim 1, wherein Determining that a defect is located at any position in the subset of the N stages based at least on comparing a first data pattern and a second data pattern, where the first data pattern and the second data pattern are unloaded through the scan chain based on a first combination of the control signals and a second combination of the control signals, respectively; The first combination of the control signals and the second combination of the control signals differ from each other by only one bit.

7. A scan chain circuit, characterized in that, Comprising: A scan chain including a cell structure, where the cell structure includes N stages, where N is a complex number, and each stage is configured to store one bit; S multiplexers operatively coupled to the N stages, where S is a complex number, and S is a factor of N; Wherein each of the multiplexers is configured to receive a respective one of a plurality of control signals to selectively bypass a respective subset of the N stages.

8. The scan chain circuit according to claim 7, wherein S is determined by N / M, where M represents diagnostic resolution.

9. The scan chain circuit according to claim 7, wherein The first multiplexer, the second multiplexer, and the third multiplexer among the multiplexers are sequentially connected in a direction from the scan input terminal of the scan chain to the scan output terminal of the scan chain; Each of the plurality of multiplexers has: a first input terminal, a second input terminal, and an output terminal; Wherein the first input terminal of the first multiplexer is coupled to the scan input terminal, the second input terminal of the first multiplexer is connected to the output terminal of the first subset of the N stages, and the output terminal of the first multiplexer is connected to the first input terminal of the second multiplexer; wherein the second input terminal of the second multiplexer is connected to the output terminals of a second subset of the N stages, and the output terminal of the second multiplexer is connected to the first input terminal of the third multiplexer; and wherein the second input terminal of the third multiplexer is connected to the output terminals of a third subset of the N stages, and the output terminal of the third multiplexer is coupled to the scan output terminal.

10. The circuit according to claim 7, characterized in that, The number of combinations of the S control signals received by the multiplexer is equal to S + 1.

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