Array circuit, CF substrate and liquid crystal display device

Abstract

The utility model discloses an array circuit, a CF substrate and a liquid crystal display device. The array circuit comprises a plurality of data lines, a plurality of gate lines, a plurality of RGB pixel units and a plurality of GIP modules. The plurality of data lines are longitudinally arranged to form column lines of the array circuit; the plurality of gate lines are transversely arranged to form row lines of the array circuit; the plurality of GIP modules are electrically connected with the plurality of gate lines respectively. Different pixels in the same RGB pixel unit are longitudinally arranged and are electrically connected with the same data line respectively; and the same type of pixels of different RGB pixel units are transversely arranged and are electrically connected with the same gate line respectively. The GIP technology is adopted, and different pixels of the RGB pixel units are longitudinally arranged and electrically connected with the same data line, so that the number of the longitudinally arranged data lines can be greatly reduced, the narrow frame design of the liquid crystal display device is facilitated, and the problems that the output channels of an existing liquid crystal display and a driving IC are increased, and the cost is low are solved. And the frame area of the liquid crystal display is increased.

Description

Technical Field

[0001] The utility model relates to the technical field of array circuits of liquid crystal displays, and particularly relates to an array circuit, a CF substrate and a liquid crystal display device. Background Art

[0002] With the development of liquid crystal display technology, narrow-bezel display screens have become the main trend in the development of high-quality display screens due to their advantages such as simplicity, beauty, and large visible area for the same size. A liquid crystal display, also known as a thin film transistor liquid crystal display (abbreviated as TFT-LCD in English), mainly includes an array substrate, a color filter substrate, and liquid crystal disposed between the array substrate and the color filter substrate. The array substrate is provided with a plurality of TFTs. The basic structure of a TFT is successively a substrate, a gate electrode, a gate insulating layer, an active layer, source / drain (abbreviated as S / D) electrodes, and an insulating protective layer.

[0003] A liquid crystal display mainly drives liquid crystal molecules to deflect by forming a voltage difference between a pixel electrode and a common electrode on the array substrate, so as to emit light of different brightnesses for image display.

[0004] In current liquid crystal displays, the number of output channels of the driving IC is also increasing. However, this multi-channel IC increases the area and cost of the IC, resulting in an increase in the bezel area of the liquid crystal display, which is inconsistent with the concept of narrow bezels and high resolution for liquid crystal displays, thus reducing the display quality. Summary of the Utility Model

[0005] In existing liquid crystal displays, the increase in the output channels of the driving IC leads to an increase in the bezel area of the liquid crystal display and a reduction in the display quality.

[0006] In view of the above problems, an array circuit, a CF substrate and a liquid crystal display device are proposed. By adopting the GIP technology and longitudinally arranging different pixels of RGB pixel units and respectively electrically connecting them to the same data line, the number of longitudinally arranged data lines can be greatly reduced, which is beneficial to the narrow-bezel design of the liquid crystal display device, and solves the problem that in existing liquid crystal displays, the increase in the output channels of the driving IC leads to an increase in the bezel area of the liquid crystal display.

[0007] In a first aspect, an array circuit includes:

[0008] A plurality of data lines;

[0009] A plurality of gate lines;

[0010] A plurality of RGB pixel units;

[0011] A plurality of GIP modules;

[0012] The multiple data lines are arranged longitudinally to form the column lines of the array circuit;

[0013] The multiple gate lines are arranged horizontally to form the row lines of the array circuit;

[0014] The multiple GIP modules are respectively electrically connected to the multiple gate lines.

[0015] The different pixels in the same RGB pixel unit are arranged longitudinally and are respectively electrically connected to the same data line;

[0016] The same - type pixels of different RGB pixel units are arranged horizontally and are respectively electrically connected to the same gate line.

[0017] Combined with the array circuit of the present utility model, in the first possible implementation manner, multiple RGB pixel units are arranged longitudinally to form multiple columns of RGB pixel units;

[0018] The drains of each pixel in each column of RGB pixel units are respectively electrically connected to the same data line, and the gates of each pixel in each column of RGB pixel units are electrically connected to the gate line at intervals.

[0019] Combined with the present utility model, in the second possible implementation manner of the first possible implementation manner, the R pixels in all columns of RGB pixel units are arranged horizontally to form an R pixel row, and the gates of each R pixel in the R pixel row are respectively electrically connected to the gate lines on both sides at intervals.

[0020] Combined with the array circuit of the present utility model, in the third possible implementation manner, the G pixels in all columns of RGB pixel units are arranged horizontally to form a G pixel row, and the gates of each G pixel in the G pixel row are respectively electrically connected to the gate lines on both sides at intervals.

[0021] Combined with the array circuit of the present utility model, in the fourth possible implementation manner, the B pixels in all columns of RGB pixel units are arranged horizontally to form a B pixel row, and the gates of each R pixel in the B pixel row are respectively electrically connected to the gate lines on both sides at intervals.

[0022] In a second aspect, a CF substrate includes the array circuit described in the first aspect.

[0023] In a third aspect, a liquid - crystal display device includes the CF substrate described in the second aspect.

[0024] Implementing the array circuit, CF substrate, and liquid crystal display device of the present utility model. By adopting the GIP technology and arranging different pixels of the RGB pixel units vertically and electrically connecting them to the same data line respectively, the number of vertically arranged data lines can be greatly reduced, which is beneficial to the narrow bezel design of the liquid crystal display device, and solves the problem that in the existing liquid crystal display, the output channels of the driving IC increase, resulting in an increase in the bezel area of the liquid crystal display. Brief Description of the Drawings

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0026] Figure 1 Schematic diagram of the array circuit structure of the array substrate in the prior art;

[0027] Figure 2 Schematic diagram of the array circuit structure of the array substrate in the present utility model.

[0028] Each component and its serial number:

[0029] 100 - RGB pixel unit, 200 - RGB pixel column, 300 - R pixel row, 400 - G pixel row, 500 - B pixel row, 600 - GIP module. Detailed Embodiments

[0030] The following will clearly and completely describe the technical solutions in the present utility model in conjunction with the drawings in the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, rather than all embodiments. Based on the embodiments in the present utility model, other embodiments obtained by those of ordinary skill in the art without creative efforts all fall within the protection scope of the present utility model.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present utility model belongs. The terms used in the description of the present utility model in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present utility model. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0032] It should be noted that when an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0033] It should be understood that the orientation or positional relationship indicated by terms such as "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0034] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0035] In the existing liquid crystal display, the increase in the output channels of the driving IC leads to an increase in the border area of the liquid crystal display, reducing the display quality, as Figure 1 , Figure 1 is a schematic diagram of the array circuit structure of the array substrate in the prior art.

[0036] In view of the above problems, an array circuit, a CF substrate and a liquid crystal display device are proposed.

[0037] In a first aspect, an array circuit includes a plurality of data lines, a plurality of gate lines, a plurality of RGB pixel units 100, and a plurality of GIP modules 600; the plurality of data lines are arranged longitudinally to form the column lines of the array circuit; the plurality of gate lines are arranged horizontally to form the row lines of the array circuit; the plurality of GIP modules 600 are respectively electrically connected to the plurality of gate lines. Different pixels in the same RGB pixel unit 100 are arranged longitudinally and are respectively electrically connected to the same data line; the same type of pixels in different RGB pixel units 100 are arranged horizontally and are respectively electrically connected to the same gate line. By adopting the GIP technology and arranging different pixels of the RGB pixel unit longitudinally and respectively electrically connecting them to the same data line, the number of longitudinally arranged data lines can be greatly reduced, which is beneficial to the narrow border design of the liquid crystal display device, and solves the problem that in the existing liquid crystal display, the increase in the output channels of the driving IC leads to an increase in the border area of the liquid crystal display.

[0038] In this embodiment, multiple data lines are arranged longitudinally, including data line S1, data line S2, and data line S3, and multiple gate lines are arranged horizontally, including gate lines G1 - G10.

[0039] Multiple GIP modules 600 are respectively electrically connected to corresponding gate lines.

[0040] In this embodiment, different from the traditional technology, the different pixels in the same RGB pixel unit 100 are arranged longitudinally and are respectively electrically connected to the same data line.

[0041] Such as Figure 2 , Figure 2 is a schematic diagram of the array circuit structure of the array substrate in the present utility model. The drains of the transistors of the R pixel, G pixel, and B pixel in the RGB pixel unit 100 are all electrically connected to the same data line S1 / data line S2 / data line S3.

[0042] In this embodiment, multiple RGB pixel units 100 are arranged longitudinally to form multiple RGB pixel unit columns 200; the drain of each pixel in each RGB pixel unit column 200 is respectively electrically connected to the same data line, and the gate of each pixel in each RGB pixel unit column 200 is spaced and electrically connected to the gate line.

[0043] Such as Figure 2 , the gates of the transistors of the R pixel, G pixel, and B pixel of the same RGB pixel unit 100 on the left are electrically connected to gate lines G1, G3, and G5, and the gates of the transistors of the R pixel, G pixel, and B pixel of the same RGB pixel unit 100 on the right are electrically connected to gate lines G2, G4, and G6.

[0044] In this embodiment, the R pixels in all RGB pixel unit columns 200 are arranged horizontally to form an R pixel row 300, and the gate of each R pixel in the R pixel row 300 is respectively electrically connected to the gate lines at both sides at intervals.

[0045] Such as Figure 2 , the first R pixel, the third R pixel, and the fifth R pixel in the first R pixel row 300 are electrically connected to gate line G1, and the second R pixel, the fourth R pixel, and the sixth R pixel in the first R pixel row 300 are electrically connected to gate line G2.

[0046] In the embodiment of the present application, a dual - gate driving technology is adopted, that is, each row of pixels is driven and scanned by two gate lines.

[0047] In this embodiment, the G pixels in all RGB pixel unit columns 200 are arranged horizontally to form a G pixel row 400, and the gate of each G pixel in the G pixel row 400 is respectively electrically connected to the gate lines at both sides at intervals.

[0048] As shown in Figure 2 , the first G pixel, the third G pixel, and the fifth G pixel in the first G pixel row 400 are electrically connected to the gate line G3, and the second G pixel, the fourth G pixel, and the sixth G pixel in the first G pixel row 400 are electrically connected to the gate line G4.

[0049] In the embodiment of the present application, a dual-gate driving technology is adopted, that is, each row of pixels is driven and scanned by two gate lines.

[0050] In this embodiment, the B pixels in all the RGB pixel unit columns 200 are arranged horizontally to form a B pixel row 500, and the gates of each R pixel in the B pixel row 500 are electrically connected to the gate lines on both sides at intervals.

[0051] As shown in Figure 2 , the first B pixel, the third B pixel, and the fifth B pixel in the first B pixel row 500 are electrically connected to the gate line G5, and the second B pixel, the fourth B pixel, and the sixth B pixel in the first B pixel row 500 are electrically connected to the gate line G6.

[0052] In a second aspect, a CF substrate includes the array circuit of the first aspect.

[0053] In a third aspect, a liquid crystal display device includes the CF substrate of the second aspect.

[0054] By implementing the array circuit, the CF substrate, and the liquid crystal display device of the present utility model, by adopting the GIP technology and arranging different pixels of the RGB pixel unit 100 vertically and electrically connecting them to the same data line respectively, the number of vertically arranged data lines can be greatly reduced, which is beneficial to the narrow bezel design of the liquid crystal display device, and solves the problem that in the existing liquid crystal display, the output channels of the driving IC increase, resulting in an increase in the bezel area of the liquid crystal display.

[0055] The above are only the preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present utility model shall be included in the protection scope of the present utility model.

Claims

1. An array circuit, characterized in that it includes: Multiple data lines; Multiple gate lines; Multiple RGB pixel units; Multiple GIP modules; The multiple data lines are arranged longitudinally to form the column lines of the array circuit; The multiple gate lines are arranged horizontally to form the row lines of the array circuit; The multiple GIP modules are respectively electrically connected to the multiple gate lines; The different pixels in the same RGB pixel unit are arranged longitudinally and are respectively electrically connected to the same data line; The same-type pixels of different RGB pixel units are arranged horizontally and are respectively electrically connected to the same gate line.

2. The array circuit according to claim 1, wherein Multiple RGB pixel units are arranged longitudinally to form multiple columns of RGB pixel units; The drain of each pixel in each column of RGB pixel units is respectively electrically connected to the same data line, and the gate of each pixel in each column of RGB pixel units is electrically connected to the gate line at intervals.

3. The array circuit according to claim 2, wherein The R pixels in all columns of RGB pixel units are arranged horizontally to form an R pixel row, and the gate of each R pixel in the R pixel row is respectively electrically connected to the gate lines on both sides at intervals.

4. The array circuit according to claim 1, wherein The G pixels in all columns of RGB pixel units are arranged horizontally to form a G pixel row, and the gate of each G pixel in the G pixel row is respectively electrically connected to the gate lines on both sides at intervals.

5. The array circuit according to claim 1, wherein The B pixels in all columns of RGB pixel units are arranged horizontally to form a B pixel row, and the gate of each R pixel in the B pixel row is respectively electrically connected to the gate lines on both sides at intervals.

6. A CF substrate, characterized in that, Including the array circuit according to any one of claims 1-5.

7. A liquid crystal display device, characterized in that, Including the CF substrate according to claim 6.

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