Packaging structure of high-heat-dissipation chip
By using sponge structure instead of the dispensing process in semiconductor chip packaging, the problem of uncontrollable glue thickness is solved, and the simplification and reliability of the high-heat dissipation packaging structure is achieved.
Patent Information
- Application Number
- CN202422019643.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-20
- Publication Date
- 2025-07-22
- Estimated Expiration
- 2034-08-20
AI Technical Summary
During the packaging process of existing semiconductor chips, the dispensing process has problems such as high processing difficulty and uncontrollable glue thickness, which affects the difficulty of the packaging process and device performance.
The sponge structure is used instead of the dispensing process. Through the connection between the sponge and the substrate and the heat dissipation cover, the compressibility and breathability of the sponge are used, and the thickness of the thermal interface material is determined by combining the physical properties and pressure of the thermal interface material, thus eliminating the dispensing process.
It reduces the difficulty of packaging processing, ensures controllable thickness of the thermal interface material layer, and improves packaging reliability and heat dissipation effect.
Smart Images
Figure CN223140768U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor packaging, in particular to a packaging structure of a chip with high heat dissipation performance. Background Art
[0002] Semiconductor packaging refers to the process of processing tested wafers into independent chips according to product models and functional requirements.
[0003] The traditional packaging process is as follows: the wafer from the front-end process is cut into small chips through a thinning and dicing process, and then the cut chips are mounted on the corresponding substrate (lead frame) frame, and then the wire bonding technology is used to connect the ultra-fine metal wires (commonly used gold, copper, alloys, etc.) through high temperature, pressure, and ultrasonic conditions to connect the bonding pads of the chip to the corresponding pins of the substrate to form the required circuit; then it is packaged and protected with a plastic shell, and after the plastic sealing, it undergoes a series of operations such as cutting. After the packaging is completed, the finished product is tested, usually after inspection, testing, and packaging, and finally put into storage for shipment.
[0004] The chip pads of wire bonding technology are all around the chip, so the number of I / O cannot be too large. As the demand for semiconductor performance increases, the chip is flipped (Flip chip), and the entire chip area is used to interconnect with the substrate through bumps (Bump), which greatly increases the number of I / O. However, as the performance per unit area increases, the heat dissipation demand also increases accordingly. Therefore, a heat dissipation cover is installed to achieve the purpose of heat dissipation and chip protection.
[0005] In the existing semiconductor chip packaging process, after adding components such as resistors and capacitors, a glue dispensing barrier process is usually used to block the conductive thermal interface material to prevent short circuits. However, the glue dispensing process has the following problems: (1) The glue should be precisely placed on the part that needs to be sealed or fixed; (2) The amount and accuracy of the glue dispensing need to be controlled. Too little glue may lead to poor sealing effect, and too much glue may affect the performance of the device; (3) The temperature, pressure, and speed of the glue during the glue dispensing process will also affect the glue dispensing effect. The above problems affect the difficulty of the chip packaging process and easily lead to the uncontrollable thickness of the glue formed by the glue dispensing. Utility Model Content
[0006] Aiming at the problems of high chip packaging process difficulty and uncontrollable glue thickness in the existing chip packaging process of dispensing glue to isolate components and thermal interface materials, the utility model provides a packaging structure for a high heat dissipation chip to solve the above problems.
[0007] The technical solution of the utility model is as follows:
[0008] A packaging structure for a high heat dissipation chip, comprising a substrate and a heat dissipation cover; at least one group of parallel sponges are provided between the substrate and the heat dissipation cover; the sponges are respectively connected to the substrate and the heat dissipation cover through double-sided adhesive tapes; a chip is connected above the substrate through bumps; the chip is located between the parallel sponges; a thermal interface material is provided between the chip and the heat dissipation cover; a circle of steps is provided at the edge of the heat dissipation cover; an adhesive is applied between the steps and the substrate.
[0009] Further, the sponge is set as a closed square or several groups of parallel sponge structures, and a barrier structure is formed through the sponges to effectively isolate the chip.
[0010] Further, the height of the sponge ≥ the gap between the substrate and the heat dissipation cover.
[0011] Further, the thermal interface material is selected from silicone grease, silica gel, silver paste or indium sheet
[0012] Further, a bottom filler is also provided between the chip and the substrate.
[0013] Further, electronic components are provided on the substrate outside the chip and the sponge.
[0014] Further, the sponge is a high-temperature resistant sponge.
[0015] The working principle of the present utility model is as follows: when packaging the chip, first mount the components, and then mount the chip on the substrate through bumps (Bump); then perform bottom filling between the chip and the substrate; then mount the sponge outside the chip; then coat or mount the thermal interface material on the surface of the chip. And apply adhesive between the step part of the heat dissipation cover and the substrate, finally install the heat dissipation cover and cure it, and finally the packaging process ends after processes such as ball planting.
[0016] The beneficial effects of the present utility model are as follows:
[0017] The packaging structure for a high heat dissipation chip provided by the present utility model eliminates the dispensing process and instead mounts the sponge, greatly reducing the processing difficulty. And it avoids the situation that the thickness of the isolation layer formed by the dispensing process is uncontrollable and affects the thickness of the thermal interface material. The thickness of the thermal interface material layer is directly determined by the material properties and pressure of the thermal interface material through the compressibility of the sponge, and by using the air permeability of the sponge, there is no need to open air holes in the isolation layer, improving the reliability. Description of the Drawings
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following will briefly introduce the drawings required for description in the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.
[0019] Figure 1 This is a schematic cross-sectional structure diagram of the present utility model.
[0020] Figure 2 This is a top view of the present utility model before installing the heat dissipation cover.
[0021] In the figure, 1 - substrate, 2 - heat dissipation cover, 3 - thermal interface material, 4 - sponge, 5 - double-sided tape, 6 - chip, 7 - adhesive, 8 - electronic components, 9 - bump, 10 - underfill, 11 - step. Specific embodiments
[0022] In order to enable those skilled in the art to better understand the technical solutions in the present utility model, the following will clearly and completely describe the technical solutions in the embodiments of the present utility model in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments in the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.
[0023] Embodiment 1
[0024] A packaging structure for a high heat dissipation chip, comprising a substrate 1 and a heat dissipation cover 2; a group of parallel sponges 4 are provided between the substrate 1 and the heat dissipation cover 2; the sponges 4 are respectively connected to the substrate 1 and the heat dissipation cover 2 through double-sided tapes 5; a chip 6 is connected above the substrate 1 through a bump 9; the chip 6 is located between the parallel sponges 4; a thermal interface material 3 is provided between the chip 6 and the heat dissipation cover 2; a circle of steps 11 is provided at the edge of the heat dissipation cover 2; an adhesive 7 is applied between the step 11 and the substrate 1.
[0025] Embodiment 2
[0026] A packaging structure for a high heat dissipation chip, comprising a substrate 1 and a heat dissipation cover 2; two groups of parallel sponges 4 are provided between the substrate 1 and the heat dissipation cover 2, and the two groups of sponges 4 form a closed square, and the sponges 4 are high-temperature resistant sponges; the sponges 4 are respectively connected to the substrate 1 and the heat dissipation cover 2 through double-sided tapes 5, and the height of the sponges 4 is greater than the gap between the substrate 1 and the heat dissipation cover 2; a chip 6 is connected above the substrate 1 through a bump 9; the chip 6 is located inside the closed square formed by the two groups of sponges 4; a thermal interface material silicone grease is coated between the chip 6 and the heat dissipation cover 2; an underfill 10 is further provided between the chip 6 and the substrate 1; a circle of steps 11 is provided at the edge of the heat dissipation cover 2; an adhesive 7 is applied between the step 11 and the substrate 1; electronic components 8 are provided on the substrate 1 outside the chip 6 and the sponges 4.
[0027] Although the present utility model has been described in detail by referring to the accompanying drawings and in conjunction with the preferred embodiments, the present utility model is not limited thereto. Without departing from the spirit and essence of the present utility model, those of ordinary skill in the art can make various equivalent modifications or substitutions to the embodiments of the present utility model, and these modifications or substitutions should all fall within the scope of the present utility model / Any person skilled in the art within the technical scope disclosed by the present utility model can easily think of changes or substitutions, which should all be covered by the protection scope of the present utility model.
Claims
1. A packaging structure for a high heat dissipation chip, comprising a substrate and a heat dissipation cover; characterized in that, There is at least one set of parallel sponges between the substrate and the heat dissipation cover; the sponges are respectively connected to the substrate and the heat dissipation cover through double-sided tape; a chip is connected above the substrate through bumps; the chip is located between the parallel sponges; a thermal interface material is provided between the chip and the heat dissipation cover; a circle of steps is provided at the edge of the heat dissipation cover; an adhesive is applied between the steps and the substrate.
2. The encapsulation structure of the high heat dissipation chip according to claim 1, characterized in that, The sponge is arranged as a closed square or several sets of parallel sponge structures.
3. The encapsulation structure of the high heat dissipation chip according to claim 1, characterized in that, The height of the sponge ≥ the gap between the substrate and the heat dissipation cover.
4. The encapsulation structure of the high heat dissipation chip according to claim 1, characterized in that The thermal interface material is selected from silicone grease, silica gel, silver paste or indium sheet.
5. The encapsulation structure of the high heat dissipation chip according to claim 1, characterized in that, There is also an underfill between the chip and the substrate.
6. The encapsulation structure of the high heat dissipation chip according to claim 1, characterized in that Electronic components are provided on the substrate outside the chip and the sponge.
7. The encapsulation structure of the high heat dissipation chip according to claim 1, characterized in that The sponge is a high-temperature resistant sponge.