Test structure and semiconductor structure

Abstract

The utility model relates to a test structure and a semiconductor structure. The test structure comprises a plurality of test units arranged in a two-dimensional array and at least one row of liner units, and each liner unit comprises a plurality of liners arranged at intervals; in the row direction of the two-dimensional array, the test units and the pads are alternately arranged, and at least two adjacent rows of test units share the same row of pad units; the test structure is arranged in a cutting channel of a wafer, and the line direction is parallel to the extending direction of the cutting channel. The semiconductor structure comprises an exposure area, a first cutting channel arranged around the exposure area, a second cutting channel arranged in a residual area around the exposure area and the test structure, the extension direction of the first cutting channel is parallel to a short axis direction, and the extension direction of the second cutting channel is parallel to a long axis direction. And the long axis direction and the short axis direction are respectively the length direction and the width direction of the exposure area. According to the invention, the effective usable area of the wafer is improved on the premise of ensuring the effectiveness of the acceptance test of the wafer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technologies, and particularly to a test structure and a semiconductor structure. Background Art

[0002] The Wafer Acceptance Test (WAT) is carried out after the wafer products are taped out and before quality inspection. The Wafer Acceptance Test detects the process conditions of each wafer product by testing the electrical parameters of specific test structures on the wafer, so as to evaluate the quality and stability of the semiconductor manufacturing process.

[0003] The structure on the wafer for collecting Wafer Acceptance Test data is called a WAT test structure (Testkey). An integrated circuit manufacturing factory (Fab) will design the WAT test structure in the scribe line (also known as the dicing slot) between the dies on the wafer. The integrated circuit manufacturing factory formulates the width design requirements of the scribe line according to the precision requirements of the die saw and the size of the test structure, and strives to make the scribe line have the minimum width and the minimum area.

[0004] With the development of semiconductor technologies, the complexity of the process has been continuously improved, and the test structures (Testkey) for monitoring the Wafer Acceptance Test have gradually increased. This requires that there is a scribe line with a large enough area on the wafer to place these test structures. However, the area of the wafer is fixed. The increase in the area of the scribe line will inevitably lead to a reduction in the die area, thereby resulting in a decrease in the profit of the customer (Customer). Summary of the Utility Model

[0005] Based on this, it is necessary to provide a test structure and a semiconductor structure to reduce the area of the scribe line in the wafer on the premise of ensuring the effectiveness of the Wafer Acceptance Test.

[0006] In a first aspect, the present application provides a test structure, including:

[0007] A plurality of test units arranged in a two-dimensional array;

[0008] At least one row of pad units, each row of the pad units including a plurality of pads arranged at intervals; wherein,

[0009] In the row direction of the two-dimensional array, the test units and the pads are alternately arranged, and at least two adjacent rows of the test units share the same row of the pad units;

[0010] The test structure is arranged in the scribe line of the wafer, and the row direction is parallel to the extension direction of the scribe line.

[0011] In one embodiment, the test structure includes at least one test group, and the test group includes:

[0012] The test units in two adjacent rows;

[0013] Wherein, the test units in two adjacent rows in each test group share the same row of pad units.

[0014] In one embodiment, the test units in at least two adjacent rows sharing the same row of pad units includes:

[0015] The projection of the test unit in the row direction onto the pad falls at most partially on the pad.

[0016] In one embodiment, in the column direction of the two-dimensional array, the test units and the pads are arranged alternately, and the test units in at least two adjacent columns share the same column of pads.

[0017] In a second aspect, the present application further provides a semiconductor structure, including:

[0018] An exposure area;

[0019] A first saw cut, the first saw cut is disposed around the exposure area, and the extending direction of the first saw cut is parallel to a short axis direction;

[0020] A second saw cut, the second saw cut is disposed in the remaining area around the exposure area, and the extending direction of the second saw cut is parallel to a long axis direction;

[0021] The test structure provided in the first aspect of the present application, the test structure is disposed in the first saw cut;

[0022] Wherein, the long axis direction is the length direction of the exposure area, and the short axis direction is the width direction of the exposure area.

[0023] In one embodiment, the width of the second saw cut is the minimum design width allowed by the process.

[0024] In one embodiment, the row direction of the test structure is parallel to the short axis direction.

[0025] In one embodiment, the width range of the first saw cut includes 70μm to 150μm.

[0026] In one embodiment, the width range of the second saw cut includes 20μm to 40μm.

[0027] In one embodiment, the semiconductor structure further includes:

[0028] A semiconductor device, where the semiconductor device is located within the exposure area;

[0029] Wherein, the long axis direction is parallel to the length direction of the design dimension of the semiconductor device, and the short axis direction is parallel to the width direction of the design dimension of the semiconductor device.

[0030] An unexpected effect of this application is that by providing a shared pad in the test structure, at least two adjacent rows of test units in the row direction share the same row of pad units, reducing the pitch between at least two adjacent rows of test units while ensuring the effectiveness of the test structure, thereby reducing the width of the test structure in the column direction. Additionally, the test structure can be disposed within the scribe line, and the row direction of the test structure is parallel to the extension direction of the scribe line. By reducing the width of the test structure in the column direction, the width of the scribe line is reduced, thereby reducing the total area of the scribe lines on the wafer, and further increasing the effective usage area of the wafer while ensuring the effectiveness of the wafer acceptance test.

[0031] Furthermore, by providing a first scribe line extending along the short axis direction and a second scribe line extending along the long axis direction, and disposing the test structure within the first scribe line, the width of the second scribe line is effectively reduced, thereby significantly reducing the total area of the scribe lines within the wafer, and further increasing the effective usage area of the wafer while ensuring the effectiveness of the wafer acceptance test. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] To more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0033] Figure 1 It is a schematic layout structure diagram of a wafer;

[0034] Figure 2 It is a schematic structural diagram of a test structure provided by an embodiment of the present application;

[0035] Figure 3 It is a schematic structural diagram of a test structure provided by an embodiment of the present application that includes two test groups and does not share pads between different groups;

[0036] Figure 4 It is a schematic structural diagram of a test structure provided by an embodiment of the present application that includes two test groups and shares pads between different groups;

[0037] Figure 5Structural schematic diagram of a semiconductor structure provided by an embodiment of the present application;

[0038] Description of reference numerals:

[0039] Figure 1 Among them: 100 - wafer; 110 - exposure area; 120 - scribe lane; 130 - test structure; 131 - test unit; 132 - pad; X1 - long axis direction; Y1 - short axis direction;

[0040] Figure 2 Among them: 200 - test structure; 210 - test unit; 220 - pad; A - row direction; B - column direction;

[0041] Figure 3 Among them: 300 - test structure; 310 - test group; 311 - test unit; 312 - pad; A - row direction; B - column direction;

[0042] Figure 4 Among them: 400 - test structure; 410 - test group; 411 - test unit; 412 - pad; A - row direction; B - column direction;

[0043] Figure 5 Among them: 500 - wafer; 510 - exposure area; 520 - first scribe lane; 521 - test structure; 530 - second scribe lane; X2 - long axis direction; Y2 - short axis direction. Detailed implementation manners

[0044] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the description of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0046] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as the second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types. For instance, the first doping type may be a P-type and the second doping type may be an N-type, or the first doping type may be an N-type and the second doping type may be a P-type.

[0047] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are accordingly interpreted.

[0048] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / include" or "has" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0049] Figure 1 It is a schematic diagram of the layout structure of a wafer. Refer to Figure 1 , in a general wafer layout structure, multiple exposure areas 110 are provided on the wafer 100. Several chips (Dies, not shown in the figure) are provided in the exposure area 110. A scribe line 120 is provided between adjacent exposure areas 110, and a scribe line 120 is also provided between adjacent chips (not shown in the figure). The test structure (Testkey) 130 of the wafer 100 is provided in the scribe line 120. Among them, the length direction of the exposure area 110 is defined as the major axis direction X1, and the width direction of the exposure area 110 is defined as the minor axis direction Y1. Optionally, the width range of the scribe line 120 is 60μm to 150μm, for example, 60μm.

[0050] Continue to refer to Figure 1 , the test structure 130 includes a plurality of test units 131 and a plurality of pads 132 arranged in a two-dimensional array. In the row direction of the two-dimensional array (for example, the Figure 1 X1 direction in

[0051] The size of a general scribe line is between 60μm and 150μm. For devices with a relatively large device design size (DB size), such as liquid crystal display drivers (Liquid Crystal Display, LCD Driver), the integrated circuit manufacturing factory (Fab) will arrange the test structure 130 of the wafer acceptance test (Wafer Acceptance Test, WAT) along the length direction of the device size design ( Figure 1 the X1 direction in

[0052] Table 1. Figure 1 The application status of the layout structure of the wafer shown

[0053]

[0054] Note: The units corresponding to the data without units marked in Table 1 are all micrometers (μm).

[0055] Table 1 shows Figure 1Application of the layout structure of the wafer shown. Referring to Table 1, at this time, the maximum size of the exposure area 110 is 25500μm × 32500μm, the chip size in the exposure area 110 is 491μm × 9765μm, and the widths of the saw streets 120 in the major axis direction and the minor axis direction are both 60μm. Combining the parameters in Table 1 and mathematical knowledge, it can be known that the chips on the wafer 100 are arranged in a two-dimensional array of 46×3. In addition, by way of example, the number of dies in the wafer 100 shown in Table 1 is 12016.

[0056] However, with the progress of semiconductor technology and the increase in the complexity of the process, as well as the gradual increase in the number of test structures in the wafer acceptance test, the area of the saw streets used to set the test structures is also continuously increasing. The continuous increase in the area of the saw streets will inevitably lead to a continuous reduction in the area occupied by the chips in the wafer and a decrease in the profit of the customer.

[0057] To solve the above problems, the present application provides a test structure. Referring to Figure 2 , in one embodiment, the test structure 200 includes a plurality of test units 210 arranged in a two-dimensional array and at least one row of pad units. Each row of pad units includes a plurality of pads 220 arranged at intervals; wherein, in the row direction (i.e., the A direction) of the two-dimensional array, the test units 210 and the pads 220 are arranged alternately, and at least two adjacent rows of test units 210 share the same row of pad units; the test structure 200 is disposed in the saw street (not shown in the figure) of the wafer (not shown in the figure), and the row direction is parallel to the extension direction of the saw street.

[0058] In one embodiment, at least two adjacent rows of test units 210 sharing the same row of pad units includes: the projection of the test unit 210 in the row direction towards the pad 220 falls at most partially on the pad 220. Preferably, the projections of two adjacent test units 210 in the row direction (i.e., the A direction) towards the same pad 220 both fall at most partially on this pad 220, so as to reduce the width of the test structure 200 in the column direction (i.e., the B direction). It should be noted that since Figure 2 there is only one row of pads 220, therefore, the pad units in this embodiment include Figure 2 all the pads 220 in

[0059] Compare Figure 1 and Figure 2, the test structure provided by the present application reduces the pitch between at least two adjacent rows of test units 210 in the row direction (i.e., the A direction) by providing a shared pad 220 in the test structure 200, such that at least two adjacent rows of test units share the same row of pad units, thereby reducing the width of the test structure 200 in the column direction (i.e., the B direction) while ensuring the effectiveness of the test structure.

[0060] In addition, since the test structure provided by the present application is disposed in the scribe lane and the row direction of the test structure is parallel to the extending direction of the scribe lane, therefore, by reducing the width of the test structure in the column direction, the width of the corresponding scribe lane can be reduced, thereby reducing the total area of the scribe lanes on the wafer, and further increasing the effective usage area of the wafer while ensuring the effectiveness of the wafer acceptance test.

[0061] In one embodiment, the test structure includes at least one test group, and the test group includes two adjacent rows of test units; wherein, two adjacent rows of test units in each test group share the same row of pad units. Exemplarily, Figure 2 the test structure 200 in

[0062] In one embodiment, the test structure includes two or more test groups, and no shared pad is provided between two adjacent rows of test units located in different test groups. Exemplarily, referring to Figure 3 , the test structure 300 may include two test groups 310, and no shared pad 312 is provided between the test units 311 of different test groups 310. In other embodiments where no shared pad is provided between different test groups, the arrangement manner between different test groups in the test structure can be flexibly adjusted according to the size of the scribe lane in the wafer. For example, all test groups are disposed in the same row or the same column, or all test groups are arranged in a two-dimensional array, so as to further reduce the size or area of the test structure while ensuring the effectiveness of the test structure.

[0063] In one embodiment, the test structure includes two or more test groups, and a shared pad is provided between two adjacent rows of test units located in different test groups. Exemplarily, referring to Figure 4 , the test structure 400 includes two test groups 410, and a shared pad 412 may also be provided between two adjacent rows of test units 411 located in different test groups 410 to further reduce the size or area of the test structure. It should be emphasized that the number of test groups, the arrangement manner, and whether a shared pad is provided between different test groups in the test structure can all be adjusted according to actual needs, as long as the condition of "ensuring the effectiveness of the test structure" is satisfied.

[0064] Continue to refer to Figure 2 , in one of the embodiments, in the column direction (i.e., the B direction) of the two-dimensional array, the test units 210 and the pads 220 are arranged alternately, and at least two adjacent columns of test units 210 share the same column of pads 220, so as to further reduce the size and the occupied area of the test structure.

[0065] It should be noted that at least two adjacent columns of test units 210 sharing the same column of pads 220 includes: the projection of the test unit 210 in the column direction towards the pad 220 falls on the pad 220 at most partially. Preferably, the projections of two adjacent test units 210 in the column direction (i.e., the B direction) towards the same pad 220 both fall on this pad 220 at most partially, so as to reduce the width of the test structure 200 in the row direction (i.e., the A direction), thereby further reducing the size and the occupied area of the test structure.

[0066] Figure 5 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present application. Refer to Figure 5 , the present application provides a semiconductor structure, including an exposure area 510; a first scribe line 520, the first scribe line 520 is arranged around the exposure area 510, and the extending direction of the first scribe line 520 is parallel to a short-axis direction (i.e., the Y2 direction); a second scribe line 530, the second scribe line 530 is arranged in the remaining area around the exposure area 510, and the extending direction of the second scribe line 530 is parallel to a long-axis direction (i.e., the X2 direction); the test structure 521 provided by the first aspect of the present application (for example, Figures 2 - 4 any of the test structures shown), the test structure 521 is arranged in the first scribe line 520. Wherein, the long-axis direction is the length direction of the exposure area 510, and the short-axis direction is the width direction of the exposure area 510.

[0067] It should be noted that since the test structure 521 is entirely located in the first scribe line 520, that is, no test structure is arranged in the second scribe line 530, therefore, the width of the second scribe line 530 can be the minimum design width allowed by the process, so as to minimize the area of the second scribe line to the greatest extent. Optionally, the width range of the second scribe line 530 includes 20μm to 40μm.

[0068] Furthermore, since the test structure 521 is arranged in the first scribe line 520, therefore, the area of the first scribe line 520 is significantly larger than the area of the second scribe line 530, so as to ensure that the first scribe line 520 can completely accommodate all the test structures 521, thereby ensuring the effectiveness of the test structure, and further ensuring that the wafer acceptance test can be carried out smoothly. Optionally, the width range of the first scribe line 520 includes 70μm to 150μm.

[0069] Comparison Figure 1 and Figure 5 For the semiconductor structure provided by the present application, by providing a first scribe line 520 extending along the short axis direction (i.e., the Y2 direction) and a second scribe line 530 extending along the long axis direction (i.e., the X2 direction), and disposing the test structure 521 in the first scribe line 520, the width of the second scribe line 530 is effectively reduced, thereby greatly reducing the total area of the scribe lines in the wafer (i.e., the sum of the areas of the first scribe line 520 and the second scribe line 530), and further improving the effective usage area of the wafer on the premise of ensuring the effectiveness of the wafer acceptance test.

[0070] Exemplarily, referring to Figure 2 and Figure 5 , the test structure 521 includes a plurality of test units arranged in a two-dimensional array (refer to the test unit 210 in Figure 2 ); at least one row of pad units, and one row of pad units includes a plurality of pads arranged at intervals (refer to the pad 220 in Figure 2 ); wherein, in the row direction of the two-dimensional array (i.e., the Figure 2 A direction in Figure 2 ), the test units (refer to 210) and the pads (refer to 220) are alternately arranged, and at least two adjacent rows of test units (refer to 210) share the same row of pad units; the test structure 521 is disposed in the scribe line (i.e., the first scribe line 320) of the wafer 500, and the row direction (i.e., the Figure 5 A direction in

[0071] It should be noted that since the test structure 521 is entirely disposed in the first scribe line 520, therefore, the row direction of the test structure 521 is parallel to the short axis direction (Y2 direction), that is, the Figure 2 A direction in Figure 5 is parallel to the Figure 2 Y2 direction in Figure 5 . Correspondingly, the column direction of the test structure 521 is parallel to the long axis direction (X2 direction), that is, the

[0072] At this time, since Figure 2In the test structure, by providing a shared pad 220, at least two adjacent rows of test units 210 in the row direction (i.e., the A direction, which can also be understood as the Y2 direction) share the same row of pad units. On the premise of ensuring the effectiveness of the test structure, the pitch between at least two adjacent rows of test units is reduced, thereby reducing the width of the test structure in the column direction (i.e., the B direction, which can also be understood as the X2 direction). Therefore, when the test structure provided in the first aspect of the present application is adopted, the width of the test structure 521 in the long axis direction (i.e., the X2 direction) is reduced, so that the width of the first scribe lane 520 accommodating the test structure 521 can be reduced, further reducing the area of the first scribe lane 520 without affecting the effectiveness of the test structure 521.

[0073] In one embodiment, the test structure 521 includes at least one test group (not shown in the figure), and the test group includes two adjacent rows of test units (not shown in the figure); wherein, two adjacent rows of test units in each test group share the same row of pad units (not shown in the figure). Exemplarily, referring to Figure 2 and Figure 5 , when the test structure 521 includes one test group, two adjacent rows of test units in the test group (refer to the test units 210 in Figure 2 ) share the same row of pad units (refer to the pad units in Figure 2 , and the pad units in Figure 2 include all the pads 220).

[0074] In other embodiments, referring to Figure 3 and Figure 5 , the test structure 521 may include two or more test groups (e.g., the test group 310 in Figure 3 ), and there is no case where the test units of different test groups (refer to the test units 311 in Figure 3 ) share pads (refer to the pads 312 in Figure 3 ). At this time, the arrangement of all test groups (i.e., 310) in the test structure 521 can be flexibly adjusted according to the size of the scribe lane (i.e., the first scribe lane 520) in the wafer 500 to further reduce the size or area of the test structure 521 on the premise of ensuring the effectiveness of the test structure 521.

[0075] In one embodiment, referring to Figure 4 and Figure 5 , when the test structure 521 includes two or more test groups (e.g., the test group 410 in Figure 4 ), shared pads may also be provided between two adjacent rows of test units (refer to the test units 411 in Figure 4 ) located in different test groups (i.e., 410) (refer to Figure 4The pad 412 in the test structure 521 is used to further reduce the size or area of the test structure 521. It should be emphasized that the number and arrangement of the test groups in the test structure and whether to set a common pad between different test groups can be adjusted according to actual needs, as long as the condition of "ensuring the effectiveness of the test structure" is met.

[0076] In one embodiment, continue to refer to Figure 2 and Figure 5 , in the column direction of the two-dimensional array (i.e., B direction, which can also be understood as X2 direction), the test unit (reference Figure 2 The test unit 210) and the pad (reference Figure 2 The pads 220 in the test structure are arranged alternately, and at least two adjacent columns of test units (ie, 210) share the same column of pads (ie, 220), thereby further reducing the size and area occupied by the test structure.

[0077] In one embodiment, the semiconductor structure further includes a semiconductor device (not shown in the figure), which is located in the exposure region; wherein the major axis direction is parallel to the length direction of the designed dimension of the semiconductor device, and the minor axis direction is parallel to the width direction of the designed dimension of the semiconductor device.

[0078] Table 2 shows Figure 5 The application of the semiconductor structure shown. Referring to Table 2, at this time, the maximum size of the exposure area 510 is 25500μm×32500μm, the chip size in the exposure area 510 is 491μm×9765μm, the width of the cutting road (herein representing the first cutting road 520) in the short axis direction is 70μm, and the width of the cutting road (herein representing the second cutting road 530) in the long axis direction is 40μm. Combining the parameters in Table 2 and mathematical knowledge, it can be seen that the chips on the wafer 500 are arranged in a two-dimensional array of 48×3. In addition, illustratively, in the wafer 500 shown in Table 2, the number of dies in the cutting road (herein representing the first cutting road 520) is 12454.

[0079] Table 2 Figure 5 Application of the semiconductor structure shown

[0080]

[0081] Note: The data without marked units in Table 2 correspond to micrometers (μm).

[0082] By comparing Table 1 and Table 2, it can be seen that since no test structure is set in the second cutting road provided in the embodiment of the present application, the width of the cutting road (i.e., the second cutting road 530) extending along the long axis direction in the embodiment of the present application (i.e., 40μm) is significantly smaller than the width of the general cutting road (i.e., 60μm).

[0083] Continuing to compare Table 1 and Table 2, since the test structures 521 provided in the embodiments of the present application are all disposed within the first dicing lane 520, therefore, in the embodiments of the present application, the width of the dicing lane extending along the short axis direction (i.e., the first dicing lane 520) (i.e., 70 μm) is greater than the width of a general dicing lane (i.e., 60 μm).

[0084] It should be noted that even though the width of the dicing lane extending along the short axis direction (i.e., the first dicing lane 520) in the embodiments of the present application is greater than the width of a general dicing lane, the area of the test structure 521 provided in the embodiments of the present application is smaller than the area of a general test structure, and the width of the dicing lane extending along the long axis direction (i.e., the second dicing lane 530) in the embodiments of the present application is significantly smaller than the width of a general dicing lane. Therefore, the total area of the dicing lanes on the finally formed wafer 500 (i.e., the sum of the areas of the first dicing lane and the second dicing lane) is still smaller than the dicing lane area on a general wafer 100, thus indicating that the embodiments of the present application can reduce the dicing lane area of the wafer.

[0085] In addition, the number of die in a general wafer 100 is 12,016, and the number of die in the wafer 500 in the embodiments of the present application is 12,454. The chips on a general wafer 100 are arranged in a 46×3 two-dimensional array, and the chips on the wafer 500 in the embodiments of the present application are arranged in a 48×3 two-dimensional array. It can be seen that the number of die in the wafer in the embodiments of the present application is greater than the number of die in a general wafer, and the number of chips in the wafer in the embodiments of the present application is also greater than the number of chips in a general wafer. Thus, it shows that the embodiments of the present application can increase the number of die and chips in the wafer by reducing the area of the dicing lanes, and further increase the effective usage area of the wafer.

[0086] An unexpected effect of the present application is that by providing a shared pad in the test structure, at least two adjacent rows of test units in the row direction share the same row of pad units, thereby reducing the pitch between at least two adjacent rows of test units while ensuring the effectiveness of the test structure, and thus reducing the width of the test structure in the column direction; disposing the test structure within the dicing lane and making the row direction of the test structure parallel to the extension direction of the dicing lane, by reducing the width of the test structure in the column direction, the width of the dicing lane is reduced, thereby reducing the total area of the dicing lanes on the wafer, and further increasing the effective usage area of the wafer while ensuring the effectiveness of the wafer acceptance test.

[0087] In addition, by providing a first dicing lane extending along the short axis direction and a second dicing lane extending along the long axis direction, and disposing the test structure within the first dicing lane, the width of the second dicing lane is effectively reduced, thereby significantly reducing the total area of the dicing lanes within the wafer, and further increasing the effective usage area of the wafer while ensuring the effectiveness of the wafer acceptance test.

[0088] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present utility model. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0089] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0090] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A test structure, characterized in that, Comprising: A plurality of test units arranged in a two-dimensional array; At least one row of pad units, each row of the pad units including a plurality of pads arranged at intervals; wherein, In the row direction of the two-dimensional array, the test units and the pads are arranged alternately, and at least two adjacent rows of the test units share the same row of the pad units; The test structure is disposed in a dicing channel of a wafer, and the row direction is parallel to the extending direction of the dicing channel.

2. The test structure according to claim 1, wherein The test structure includes at least one test group, and the test group includes: Two adjacent rows of the test units; Wherein, two adjacent rows of the test units in each test group share the same row of the pad units.

3. The test structure according to claim 1, wherein The at least two adjacent rows of the test units sharing the same row of the pad units includes: The projection of the test unit in the row direction onto the pad falls at most partially on the pad.

4. The test structure according to claim 1 or 3, characterized in that, In the column direction of the two-dimensional array, the test units and the pads are arranged alternately, and at least two adjacent columns of the test units share the same column of the pads.

5. A semiconductor structure, characterized in that, Comprising: An exposure area; A first dicing channel, the first dicing channel being disposed around the exposure area, and the extending direction of the first dicing channel being parallel to a short-axis direction; A second dicing channel, the second dicing channel being disposed in the remaining area around the exposure area, and the extending direction of the second dicing channel being parallel to a long-axis direction; The test structure according to any one of claims 1 to 4, the test structure being disposed in the first dicing channel; Wherein, the long-axis direction is the length direction of the exposure area, and the short-axis direction is the width direction of the exposure area.

6. The semiconductor structure according to claim 5, wherein The width of the second dicing channel is the minimum design width allowed by the process.

7. The semiconductor structure according to claim 5, wherein The row direction of the test structure is parallel to the short-axis direction.

8. The semiconductor structure according to claim 5, wherein, The width range of the first dicing channel includes 70 μm to 150 μm.

9. The semiconductor structure according to claim 5, wherein, The width range of the second dicing channel includes 20 μm to 40 μm.

10. The semiconductor structure according to claim 5, wherein The semiconductor structure further includes: A semiconductor device, the semiconductor device being located in the exposure area; Wherein, the long-axis direction is parallel to the length direction of the design size of the semiconductor device, and the short-axis direction is parallel to the width direction of the design size of the semiconductor device.

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