Video image defogging system

Abstract

The utility model discloses a video image defogging system, belongs to the technical field of image processing, and solves the problems that one side of an FPGA (Field Programmable Gate Array) chip needs to acquire an image transmitted by an image acquisition module, and the other side of the FPGA chip needs to carry out defogging processing on the image, so that larger operation burden is brought to the FPGA chip, and if the image is output in real time, the image is not output in real time. And the video image is not smooth. Comprising an image acquisition module used for acquiring an image and transmitting an image signal to the outside; and a plurality of FPGA chips are provided. The video image defogging system adopts a plurality of FPGA chips for parallel processing, realizes efficient distribution and selection of image signals through the demultiplexer and the multiplexer, combines the image signals, ensures data continuity through the external cache module, extracts processed images through the display controller, realizes clear display, reduces the burden of a single FPGA, and improves the image defogging efficiency. The system efficiency and the user experience are improved, and the lagging phenomenon during image processing is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of image processing, in particular to a video image defogging system. Background Art

[0002] Images taken in foggy weather are often affected by the absorption and scattering of light by suspended particles in the atmosphere, resulting in reduced contrast, limited dynamic range, and decreased clarity, making image details blurred, many important features obscured or difficult to identify, and greatly reducing the information recognition rate. In addition, significant color shift and distortion further deteriorate the visual experience. These problems directly affect the performance of multiple systems such as outdoor target recognition, intelligent navigation, traffic monitoring, remote sensing monitoring, and military reconnaissance. Taking road traffic monitoring as an example, thick fog reduces visibility, and the road conditions information obtained by drivers relying on vision is unreliable, increasing the risk of misjudging the environment and thus prone to accidents. Currently, image processing devices basically defog through FPGA chips. However, on one hand, the FPGA chips need to obtain the images transmitted by the image acquisition module, and on the other hand, they also need to perform defogging processing on the images, bringing a large operating burden to the FPGA chips. If images are output in real time, the video images are relatively stuck.

[0003] Therefore, a video image defogging system is proposed to solve or alleviate the above problems. Summary of the Utility Model

[0004] The purpose of the utility model is to solve the deficiencies existing in the prior art and propose a video image defogging system.

[0005] To achieve the above purpose, the utility model adopts the following technical solutions:

[0006] A video image defogging system includes

[0007] An image acquisition module, which is used to acquire images and transmit image signals externally;

[0008] FPGA chips, the number of which is several, and the input ends of several said FPGA chips are all coupled to the output end of the image acquisition module, and are used to receive images and process the images;

[0009] A multiplexer, whose input end is coupled to the output end of the image acquisition module, and several output ends of which are respectively coupled to the input ends of each FPGA chip, and is used to transmit the image signal into each FPGA chip;

[0010] An external cache module, whose input end is coupled to the output ends of several FPGA chips, and is used to receive the image signals processed by each FPGA chip.

[0011] Preferably, it further includes a display controller and a display. The input end of the display controller is coupled to the output end of the external cache module, and the output end of the display controller is coupled to the input end of the display. It is used to extract the processed image from the external cache module and transmit it to the display for image display.

[0012] Preferably, it further includes a multiplexer. Several input ends of the multiplexer are coupled to the output ends of each FPGA chip and the output end of the external cache module, and the output end of the multiplexer is coupled to the input end of the display controller.

[0013] Preferably, it further includes a main control controller. The output end of the main control controller is coupled to the controlled end of the demultiplexer, and the main control controller is used for human-machine interface interaction.

[0014] Preferably, the demultiplexer is a 1-4 line decoder of 74XX139.

[0015] Preferably, the FPGA chip is an XC3S200A programmable chip.

[0016] Preferably, the external cache module is a register, and both the main controller and the display controller are STM32 single-chip microcomputers.

[0017] The utility model has the following beneficial effects:

[0018] The video image defogging system of the utility model adopts parallel processing of multiple FPGA chips, realizes efficient distribution selection and merging of image signals through a demultiplexer and a multiplexer, the external cache module ensures data continuity, the display controller extracts the processed image to achieve clear display. This design reduces the burden on a single FPGA, improves system efficiency and user experience, and reduces the lag phenomenon during image processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present utility model, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0020] Figure 1 It is a structural block diagram of the present utility model;

[0021] Figure 2 It is a wiring diagram of the demultiplexer in the present utility model;

[0022] Figure 3 It is a wiring diagram of the FPGA chip in the present utility model;

[0023] Figure 4 This is the wiring diagram of the multiplexer in the present utility model.

[0024] 1. Image acquisition module; 2. Demultiplexer; 3. Main control controller; 4. FPGA chip; 5. External cache module; 6. Multiplexer; 7. Display controller; 8. Display. Specific embodiments

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present utility model clearer, the technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are some, but not all, of the embodiments of the present utility model. Usually, the components of the embodiments of the present utility model described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of the present utility model provided in the accompanying drawings is not intended to limit the scope of the present utility model claimed, but merely represents selected embodiments of the present utility model. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts shall fall within the scope of protection of the present utility model.

[0027] It should be noted that: similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0028] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship when the product of the present utility model is normally placed, or the orientation or positional relationship commonly understood by those skilled in the art. It is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present utility model.

[0029] In addition, the terms "first", "second", "third", etc. are only used for descriptive distinction and cannot be understood as indicating or implying relative importance.

[0030] In the description of the present utility model, it should also be noted that, unless otherwise clearly specified and defined, the terms "arrangement", "installation", "connection", and "coupling" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific situations.

[0031] A video image defogging system, as Figure 1 shown, includes an image acquisition module 1, an FPGA chip 4, a multiplexer 2, an external cache module 5, a multiplexer 6, a main controller 3, a display controller 7, and a display 8. The multiplexer 2 is a 1-4 line decoder of 74XX139. The FPGA chip 4 is a programmable chip XC3S200A. The external cache module 5 is a register. The main controller and the display controller 7 are both STM32 single-chip microcomputers.

[0032] As Figures 2 - 4 shown, the image acquisition module 1 is used to acquire an image and externally transmit an image signal. The number of FPGA chips 4 is several, and the input ends of several FPGA chips 4 are coupled to the output end of the image acquisition module 1. It is used to receive the image and process the image. The input end of the multiplexer 2 is coupled to the output end of the image acquisition module 1, and its several output ends are respectively coupled to the input ends of each FPGA chip 4. It is used to transmit the image signal into each FPGA chip 4. The input end of the external cache module 5 is coupled to the output ends of several FPGA chips 4. It is used to receive the image signals processed by each FPGA chip 4. The input end of the display controller 7 is coupled to the output end of the external cache module 5, and the output end of the display controller 7 is coupled to the input end of the display 8. It is used to extract the processed image from the external cache module 5 and transmit it to the display 8 for displaying the image. The several input ends of the multiplexer 6 are coupled to the output ends of each FPGA chip 4 and the output end of the external cache module 5. The output end of the multiplexer 6 is coupled to the input end of the display controller 7. The output end of the main controller 3 is coupled to the controlled end of the multiplexer 2, and the main controller 3 is used for human-computer interface interaction.

[0033] The video image dehazing system in this utility model realizes the clarity processing of images through an efficient division of labor and collaboration process. The image acquisition module 1 first captures the scene image and generates a signal. The multiplexer 6 controls which FPGA chips 4 to connect according to the instructions of the main control controller 3, so that the demultiplexer 2 evenly distributes these signals to multiple FPGA chips 4. These chips 4 perform image dehazing processing in parallel to disperse the processing pressure of a single chip 4FPGA. The processed image signal is received and temporarily stored by the external cache module 5 to maintain the continuity and integrity of the data. The image signal is selected from the FPGA chip 4 or the external cache module 5 by the multiplexer 6 and transmitted to the display controller 7. The display controller 7 then extracts the signal from the external cache module 5 and sends it to the display 8 to display the clear image after dehazing processing. Throughout the process, users can adjust the dehazing parameters according to their needs to control the operation of the system. This design significantly improves the efficiency and real-time performance of video image dehazing processing, optimizes the user experience, and several FPGA chips 4 share the work of video image processing and dehazing. Finally, the images are merged and stored through the multiplexer 6 or the external cache module 5, and the display controller 7 only needs to extract the complete image, thus reducing the workload of the FPGA chip 4 and improving the working efficiency of the entire system, making it less prone to jamming.

[0034] The above are only the preferred embodiments of the present utility model and are not intended to limit the present utility model. For those skilled in the art, the present utility model can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. A video image defogging system, characterized in that, including an image acquisition module (1) for acquiring an image and externally transmitting an image signal; a plurality of FPGA chips (4), with the input ends of the plurality of FPGA chips (4) being coupled to the output end of the image acquisition module (1), for receiving the image and processing the image; a demultiplexer (2), with its input end coupled to the output end of the image acquisition module (1), and its plurality of output ends respectively coupled to the input ends of the respective FPGA chips (4), for transmitting the image signal into the respective FPGA chips (4); an external cache module (5), with its input end coupled to the output ends of the plurality of FPGA chips (4), for receiving the image signals processed by the respective FPGA chips (4).

2. The video image defogging system according to claim 1, characterized in that, It further includes a display controller (7) and a display (8), with the input end of the display controller (7) coupled to the output end of the external cache module (5), and the output end of the display controller (7) coupled to the input end of the display (8), for extracting the processed image from the external cache module (5) and transmitting it to the display (8) for image display.

3. A video image defogging system according to claim 1, characterized in that, It further includes a multiplexer (6), with its plurality of input ends coupled to the output ends of the respective FPGA chips (4) and the output end of the external cache module (5), and the output end of the multiplexer (6) coupled to the input end of the display controller (7).

4. A video image defogging system according to claim 1, characterized in that, It further includes a main control controller (3), with the output end of the main control controller (3) coupled to the controlled end of the demultiplexer (2), and the main control controller (3) being used for human-machine interface interaction.

5. A video image defogging system according to claim 1, characterized in that, The demultiplexer (2) is a 1-4 line decoder of 74XX139.

6. A video image defogging system according to claim 1, characterized in that, The FPGA chip (4) is an XC3S200A programmable chip.

7. A video image defogging system according to claim 4, characterized in that, The external cache module (5) is a register, and the main control controller (3) and the display controller (7) are both STM32 single-chip microcomputers.

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