DDR4 memory bank circuit board
By optimizing the DDR4 memory board to a six-layer structure, the problem of high cost in the traditional eight-layer structure is solved, cost reduction and production efficiency improvement are achieved, while maintaining the stability and integrity of signal transmission.
Patent Information
- Application Number
- CN202422377872.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2025-07-22
- Estimated Expiration
- 2034-09-29
AI Technical Summary
The eight-layer structure of traditional DDR4 memory boards results in high production costs and long production cycles, and optimized designs are required to reduce costs and improve production efficiency.
The DDR4 memory stick circuit board structure is optimized to a six-layer structure, including four-layer signal layer and two-layer power/ground layer, separated by insulating materials and used vias to achieve cross-layer connection, and re-planning the signal layout to reduce the number of layers and core board use.
It reduces production costs, improves production efficiency, and ensures the stability of the circuit board and signal transmission performance.
Smart Images
Figure CN223142218U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of memory circuit boards, and specifically relates to a DDR4 memory circuit board. Background Technique
[0002] As Figure 1 shown, the traditional DDR4 circuit board of the memory usually adopts an eight-layer structure, where L1, L3, L5, L6, and L8 are signal layers, and L2, L4, and L7 are power layers and ground layers. Insulating resin materials (Prepreg, abbreviated as PP) and core boards (Core) are used as insulation and support between layers. Although the above design can meet the functional requirements, the cost is relatively high and the production cycle is relatively long.
[0003] In order to reduce costs and improve production efficiency, while ensuring the stability and performance of the circuit board, it is necessary to optimize the structure of the traditional eight-layer circuit board. The utility model precisely proposes an optimized design scheme under this background. By reducing the number of layers and optimizing the routing layout, the cost reduction and production efficiency improvement are achieved.
[0004] Therefore, a DDR4 memory circuit board is proposed. Content of the Utility Model
[0005] The purpose of the utility model is to provide a DDR4 memory circuit board to solve the technical defect of high production cost of the existing eight-layer circuit board structure proposed in the background technique.
[0006] To achieve the above purpose, the utility model provides the following technical solutions:
[0007] A DDR4 memory circuit board, which includes a six-layer structure. The six-layer structure includes four signal layers and two power and ground layers; among them, the four signal layers include L1 layer, L3 layer, L4 layer, and L6 layer, and L1 layer, L3 layer, L4 layer, and L6 layer are signal routing layers; the two power and ground layers include L2 layer and L5 layer, and L2 layer and L5 layer are used as VDD / VSS layers.
[0008] L1 layer, L3 layer, L4 layer, and L6 layer are separated by insulating materials and are connected across layers through vias; L2 layer and L5 provide stable power and ground references for the circuit board, which is achieved through planar layout and provides connections for the four signal layers through vias.
[0009] As a preferred scheme of the utility model, the L1 layer serves as the top signal routing layer. The L1 layer is used to transmit high-speed signals. It is directly adjacent to the L2 layer and is separated by insulating resin materials.
[0010] As a preferred embodiment of the present utility model, the L2 layer serves as a power layer or a ground layer, providing a stable power supply and ground reference for the entire circuit board. It is located between the L1 layer and the L3 layer, separated by an insulating material. The power lines and ground lines on the L2 layer are realized through planar layout.
[0011] As a preferred embodiment of the present utility model, the L3 layer is a signal trace layer responsible for transmitting other key signals. It is adjacent to the L2 layer and the L4 layer, separated by an insulating material.
[0012] As a preferred embodiment of the present utility model, the L4 layer is a signal trace layer responsible for transmitting the remaining key signals. It is located between the L3 layer and the L5 layer, separated by an insulating material.
[0013] As a preferred embodiment of the present utility model, the L5 layer exists as a power layer or a ground layer, providing power supply and ground support for the circuit board. It is located between the L4 layer and the L6 layer, separated by an insulating material.
[0014] As a preferred embodiment of the present utility model, the L6 layer serves as the bottommost signal trace layer, responsible for transmitting the remaining signals. It is directly adjacent to the L5 layer, separated by an insulating material.
[0015] As a preferred embodiment of the present utility model, the thickness between the L3 layer and the L4 layer is ≥ 0.50 mm.
[0016] Compared with the prior art, a DDR4 memory module circuit board provided by the present utility model has the following beneficial effects:
[0017] 1. Reducing the number of layers: Compared with the traditional eight-layer structure, the original L7 and L8 layers, as well as the corresponding core board Core, are cancelled, reducing the manufacturing cost and material consumption.
[0018] 2. Optimizing the signal line layout: The L1, L3, L4, and L6 layers are used as signal trace layers (Signal), and the original L2 and L5 layers are retained as VDD / VSS layers (power supply and ground layers). The number of signal layers is reduced from the original five layers to four layers.
[0019] 3. Increasing the distance between L3 and L4: To improve the heat dissipation performance and electrical performance, the distance between the L3 layer and the L4 layer is increased to reduce the interlayer coupling and signal interference.
[0020] 4. Re-planning the traces: The traces on the L5 layer are cancelled, and the L3 layer and the L4 layer are used as signal trace layers; the traces on the original L6 layer are redesigned on the L4 layer, and some traces and layouts of the original L5 layer are added.
[0021] 5. Reducing the number of core boards: Due to the reduction in the number of layers, the number of core boards Core used is correspondingly reduced, thereby further reducing the production cost. Brief Description of the Drawings
[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only individual cases of the embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0023] Figure 1 It is a schematic structural diagram of a DDR4 memory module circuit board in the prior art;
[0024] Figure 2 It is a schematic structural diagram of an embodiment of the present utility model. Detailed Embodiment
[0025] In order to make the objectives, technical solutions and advantages of the embodiments of the present utility model clearer, the following further details the embodiments of the present utility model in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present utility model and are not used to limit the present utility model.
[0026] In the description of the embodiments of the present utility model, it should be understood that the orientation or positional relationships indicated by the terms "upper", "lower", "front", "rear", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the embodiments of the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the embodiments of the present utility model.
[0027] In the description of the embodiments of the present utility model, it should be noted that unless otherwise clearly specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, an integral connection, or a detachable connection; it can be the communication inside two elements; it can be directly connected, or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present utility model can be understood according to specific situations.
[0028] Refer to the attached Figure 2 As shown, an embodiment of the present utility model for a DDR4 memory module circuit board includes a six-layer structure, and the six-layer structure includes four signal layers and two power supply and ground layers.
[0029] The four signal layers include the L1 layer, the L3 layer, the L4 layer, and the L6 layer. The L1 layer, the L3 layer, the L4 layer, and the L6 layer are signal trace layers Signal;
[0030] The two-layer power and ground layers include Layer L2 and Layer L5, and Layer L2 and Layer L5 serve as the VDD / VSS layers;
[0031] Layers L1, L3, L4, and L6 are separated by insulating materials and are connected across layers through vias.
[0032] Layers L2 and L5 provide stable power and ground references for the circuit board, which are achieved through planar layouts and provide connections for the four signal layers through vias.
[0033] Layer L1 serves as the topmost signal trace layer and is usually used to transmit high-speed signals such as data buses and address buses. Layer L1 is adjacent to Layer L2 (power / ground layer) and is separated by an insulating resin material (Prepreg) to reduce signal interference.
[0034] Layer L2 serves as a power layer or a ground layer and provides stable power and ground references for the circuit board. Layer L2 is located between Layer L1 and Layer L3 and is separated by insulating materials. The power lines and ground lines on Layer L2 are achieved through planar layouts to reduce impedance and noise. At the same time, Layer L2 can also provide power or ground connections for other signal layers through vias.
[0035] Layer L3 is also a signal trace layer and is responsible for transmitting other key signals. Layer L3 is adjacent to Layer L2 and Layer L4 and is separated by insulating materials, and the thickness between Layer L3 and Layer L4 ≥ 0.50 mm. Since the distance between Layer L3 and Layer L4 is relatively increased, it helps to reduce interlayer coupling and signal interference. The signal lines on Layer L3 are connected to Layer L1 or other signal layers through vias (Via).
[0036] Layer L4 is also a signal trace layer and is responsible for transmitting the remaining key signals. Layer L4 is located between Layer L3 and Layer L5 and is also separated by insulating materials. In the optimized solution of the embodiment of the present invention, some traces of the original Layer L5 can be moved to Layer L4 to re-plan the signal layout. The signal lines on Layer L4 also need to be connected to other signal layers or power / ground layers through vias.
[0037] Layer L5 also exists as a power layer or a ground layer and provides power and ground support for the circuit board. Layer L5 is located between Layer L4 and Layer L6 and is separated by insulating materials. The layout of Layer L5 is similar to that of Layer L2, and the stable supply of power and ground is achieved through planar layouts. At the same time, Layer L5 can also provide power or ground connections for other signal layers through vias.
[0038] Layer L6 serves as the bottommost signal trace layer and is responsible for transmitting the remaining signals. Layer L6 is adjacent to Layer L5 (power / ground layer) and is separated by insulating materials. The signal lines on Layer L6 can be connected to other signal layers or power / ground layers through vias.
[0039] As Figure 2 ,through the technical solution of the embodiment of the present utility model, the existing eight-layer structure is optimized into a six-layer structure. Among them, L1 layer, L3 layer, L4 layer, and L6 layer are signal routing layers Signal, and L2 layer and L5 layer are used as VDD / VSS layers; the signal layers are changed to four layers, and the power supply and ground layers are changed to two layers; the total number of layers is reduced by two layers, one core board Core is reduced, and the distance between L3 layer and L4 layer is increased.
[0040] By reducing the number of layers, the manufacturing cost is reduced, the production efficiency is improved, and value is created for the terminal;
[0041] After the number of layers is reduced, the distance of wire routing becomes shorter, the Core design of L4 and L5 in the prior art is cancelled, and the corresponding CUs of L4 layer and L5 layer in the prior art are cancelled.
[0042] The existing L6 layer is optimized into L4 layer in the embodiment of the present utility model, the existing L7 layer is optimized into L5 layer in the embodiment of the present utility model, and the existing L8 pair is optimized into L6 layer design in the embodiment of the present utility model.
[0043] The number of wire routing needs to be increased on the basis of the existing L3 layer, and some wire routings of L5 need to be routed through L3 layer; the wire routings of the existing L5 layer are cancelled, and the wire routings of the existing L5 layer are moved to L3 and L4 layers in the embodiment of the present utility model for production; the wire routings of the existing L6 layer are optimized to be designed in L4 layer in the embodiment of the present utility model, and some wire routings and layouts of the existing L5 layer are increased; the VDD / VSS of the existing L2 and L7 are optimized to be designed in L2 layer and L5 layer in the embodiment of the present utility model; the VDD / VSS design of the existing L4 layer is cancelled, and the VDD / VSS layout of the existing L4 layer is changed to L2 layer and L5 layer in the embodiment of the present utility model; the thickness of PP is changed: the PP thickness between L3 layer and L4 layer in the embodiment of the present utility model is optimized to be ≥0.50mm to ensure that the total thickness remains unchanged.
[0044] The basic principles of the present invention have been shown and described above. The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. The descriptions in the above embodiments and the specification only illustrate the principles of the present invention. Without departing from the scope of the present invention, any modifications, equivalent replacements, and improvements made within the spirit and scope of the present invention shall be included in the protection scope of the present invention.
Claims
1. A DDR4 memory module circuit board, characterized in that: The DDR4 memory module circuit board includes a six-layer structure, and the six-layer structure includes four signal layers and two power and ground layers, where: The four signal layers include the L1 layer, the L3 layer, the L4 layer, and the L6 layer, and the L1 layer, the L3 layer, the L4 layer, and the L6 layer are signal trace layers; The two power and ground layers include the L2 layer and the L5 layer, and the L2 layer and the L5 layer are VDD / VSS layers; The L1 layer, the L3 layer, the L4 layer, and the L6 layer are separated by an insulating material and are connected across layers through vias.
2. The DDR4 memory module circuit board according to claim 1, characterized in that: The L1 layer is a signal trace layer, the L1 layer is adjacent to the L2 layer, and they are separated from each other by an insulating resin material.
3. The DDR4 memory module circuit board according to claim 2, wherein: The L2 layer is a power layer or a ground layer, the L2 layer is located between the L1 layer and the L3 layer, each layer is separated from each other by an insulating material, and the power lines and ground lines on the L2 layer are in a planar layout.
4. The circuit board of a DDR4 memory module according to claim 3, characterized in that: The L3 layer is a signal trace layer, the L3 layer is adjacent to the L2 layer and the L4 layer, and each layer is separated from each other by an insulating material.
5. The circuit board of a DDR4 memory module according to claim 4, wherein: The L4 layer is a signal trace layer, the L4 layer is located between the L3 layer and the L5 layer, and each layer is separated from each other by an insulating material.
6. The circuit board of a DDR4 memory module according to claim 5, wherein: The L5 layer exists as a power layer or a ground layer, the L5 layer is located between the L4 layer and the L6 layer, and each layer is separated from each other by an insulating material.
7. The printed circuit board of a DDR4 memory module according to claim 6, wherein: The L6 layer is a signal trace layer, the L6 layer is directly adjacent to the L5 layer, and they are separated from each other by an insulating material.
8. A DDR4 memory module circuit board according to any one of claims 1-6, characterized in that: The thickness between the L3 layer and the L4 layer ≥ 0.50 mm.