Semiconductor device

Abstract

The embodiment of the utility model relates to a semiconductor device. The semiconductor device includes a first die, a second die, and a third die. The first die has a first side including a plurality of first connection structures and a second side including a plurality of second connection structures, wherein the first side is opposite the second side. A second die has a third side including a plurality of third connection structures, wherein the plurality of third connection structures are in contact with the plurality of first connection structures of the first die. A third die has a fourth side including a plurality of fourth connection structures, wherein the plurality of fourth connection structures are in contact with the plurality of second connection structures of the first die. A first pitch of the plurality of first connecting structures and a second pitch of the plurality of third connecting structures are smaller than a third pitch of the plurality of fourth connecting structures.

Description

Technical Field

[0001] The utility model relates to an integrated semiconductor device. Background Art

[0002] The development of reducing the size of semiconductor devices and electronic devices has made it possible to integrate more devices and components into a given volume, resulting in a high integration density of various semiconductor devices and / or electronic devices. Summary of the Utility Model

[0003] An embodiment of the utility model provides a semiconductor device, including: a first die, having a first side including a plurality of first connection structures and a second side including a plurality of second connection structures, the first side being opposite to the second side; a second die, having a third side including a plurality of third connection structures, the plurality of third connection structures being in contact with the plurality of first connection structures of the first die; and a third die, having a fourth side including a plurality of fourth connection structures, the plurality of fourth connection structures being in contact with the plurality of second connection structures of the first die, wherein a first pitch of the plurality of first connection structures and a second pitch of the plurality of third connection structures are less than a third pitch of the plurality of fourth connection structures.

[0004] An embodiment of the utility model provides a semiconductor device, including: a first stacked structure and a second stacked structure, each including: a first die, having a first side and a second side; a second die, bonded to the first side of the first die through a first bonding interface, the first bonding interface including a first metal-to-metal bonding interface and a first dielectric-to-dielectric bonding interface; and a third die, bonded to the second side of the first die through a second bonding interface, the second bonding interface including a second metal-to-metal bonding interface and a second dielectric-to-dielectric bonding interface, wherein the first stacked structure and the second stacked structure are electrically independent; and a plurality of conductive terminals, disposed on and electrically coupled to the third die of the first stacked structure and the third die of the second stacked structure. Description of the Drawings

[0005] Aspects of the embodiments of the utility model are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard practices in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0006] Figures 1 to 13 are schematic cross-sectional views or schematic plan views of various stages in a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0007] Figure 14Is a schematic cross-sectional view of a semiconductor device according to other embodiments of the present disclosure.

[0008] Figure 15 Is a schematic cross-sectional view of a semiconductor device according to other embodiments of the present disclosure.

[0009] Figures 16 to 18 Is a schematic cross-sectional view or a schematic plan view of various stages in a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0010] Figures 19 to 24 Is a schematic cross-sectional view or a schematic plan view of various stages in a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0011] Figure 25 Is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0012] Figure 26 Is a schematic cross-sectional view of a semiconductor device according to other embodiments of the present disclosure.

[0013] Figure 27 Is a schematic cross-sectional view of a semiconductor device according to other embodiments of the present disclosure.

[0014] Figures 28 to 30 Is a schematic cross-sectional view or a schematic plan view of various stages in a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0015] Figures 31 to 33 Is a schematic plan view of various architectures of a semiconductor device according to some embodiments of the present disclosure.

[0016] Figure 34 Shows a schematic cross-sectional view of an application of a semiconductor device according to some embodiments of the present disclosure.

[0017] [Description of Reference Numerals]

[0018] 10: Stacked structure;

[0019] 50: Stacked cell;

[0020] 100, 100’, 200, 300, 300’, 400: Semiconductor die;

[0021] 101, 101’, 201, 301, 301’, 401’: Substrate;

[0022] 102, 202, 302, 402: Device layer;

[0023] 103, 1031, 1032, 103 N-2 、103N-1 、103 N 、109, 112, 113, 115, 203, 2031, 2032, 203 N-2 、203N -1 、203 N 、209, 303, 3031, 3032, 303 N-2 、303 N-1 、303 N 、309, 312, 313, 319, 403, 4031, 4032, 403 N-2 、403 N-1 、403 N 、412, 413, 430, 500, 600, 903, 9031, 9032, 9033, 915, 916: Dielectric layer;

[0024] 104, 1041, 1042, 104 N-2 、104 N-1 、104 N 、108v, 116v, 204, 2041, 2042, 204 N-2 、204 N-1 、204 N 、208v, 304, 3041, 3042, 304 N-2 、304 N-1 、304 N 、308v, 318v, 404, 4041, 4042, 404 N-2 、404 N-1 、404 N 、431v, 904, 9041, 9042 and 9043: Via portion;

[0025] 105, 1051, 1052, 105 N-2 、105 N-1 、105 N 、108t, 116t, 205, 2051, 2052, 205 N-2 、205 N-1 、205 N 、208t, 305, 3051, 3052, 305 N-2 、305 N-1 、305 N 、308t, 318t, 405, 4051, 4052, 405 N-2 、405 N-1 、405 N 、431t, 905, 9051, 9052 and 9053: Line portion;

[0026] 106, 1061, 1062, 106 N-2 , 106 N-1 , 106 N , 206, 2061, 2062, 206 N-2 , 206 N-1 , 206 N , 306, 3061, 3062, 306 N-2 , 306 N-1 , 306 N , 406, 4061, 4062, 406 N-2 , 406 N-1 , 406 N , 906, 9061, 9062, 9063: Patterened conductive layer;

[0027] 107, 207, 307, 407: Inner connection;

[0028] 108, 114, 116, 208, 308, 314, 318, 414, 431: Connection structure;

[0029] 110, 310, 410: Pad;

[0030] 111, 311, 411: Via;

[0031] 700: Carrier;

[0032] 800, 800m, 1800: Insulating encapsulation;

[0033] 900: Release layer;

[0034] 907: Redistribution line structure;

[0035] 917: Conductive terminal;

[0036] 917c: Conductive device;

[0037] 917u: UBM pattern;

[0038] 1000, 1000A, 1000B, 2000, 3000, 4000, 4000A, 4000B, 5000: Semiconductor device;

[0039] C1: First component;

[0040] C2: Second component;

[0041] CL: Cutting line;

[0042] CT: Terminal;

[0043] DR1, DR2, DR3: Device areas;

[0044] IF1, IF2, IF3, IF4, IF5, IF6: Bonding interfaces;

[0045] P1, P10, P2, P20, P3, P4: Pitch;

[0046] S101’, S301’: Patterned bottom surfaces;

[0047] S112, S201, S301, S310, S311, S312: Surfaces;

[0048] S110, S111: Bottom surfaces;

[0049] S500, S800: Indicated top surfaces;

[0050] SC: Component assembly;

[0051] UF: Underfill;

[0052] W1, W1’, W2, W3, W3’: Wafers;

[0053] X, Y, Z: Directions. Detailed implementation

[0054] This disclosure provides many different embodiments or examples for implementing the different features of this disclosure. Specific examples of components and arrangements are set forth below to simplify this disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, this disclosure may reuse reference numerals and / or letters in various examples. Such reuse is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0055] In addition, for ease of description, in this document, spatial relative terms such as "beneath", "below", "lower", "above", "upper", and the like may be used to describe the relationship between one device or feature shown in the drawings and another device or feature. Except for the orientation depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0056] In addition, for ease of illustration, terms such as "first", "second", "third", "fourth", etc. may be used in this document to describe similar or different devices or features shown in the figures, and these terms may be used interchangeably depending on the order present or the context of the description.

[0057] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that terms (such as those defined in a common dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and should not be interpreted as idealized or overly formal unless expressly defined herein.

[0058] Embodiments of this disclosure may also include other features and processes. For example, test structures may be included to illustrate verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3DIC) devices. The test structures may include, for example, test pads formed in a redistribution layer or on a substrate, which enable testing of the 3D package or 3DIC, use of probes and / or probe cards, and the like. Verification testing may be performed on intermediate structures and final structures. Additionally, the structures and methods disclosed herein may be used in combination with test methods that include intermediate verification of known good dies to improve yield and reduce costs.

[0059] It should be understood that the following embodiments of the present disclosure provide applicable concepts that can be implemented in a variety of specific contexts. The specific embodiments described herein relate to semiconductor devices (or semiconductor packages or structures) having a stacked structure with multiple tiers, each tier including at least one semiconductor die or chip, and are not intended to limit the scope of the present disclosure. Due to the formation of fine-pitch connection structures on the semiconductor die or chip, the overall wiring density is greatly increased, thereby obtaining higher performance and reducing manufacturing costs. Some embodiments of the present disclosure relate to semiconductor devices (or semiconductor packages or structures) having a stacked structure with multiple units, each unit including multiple tiers stacked on top of each other, and each layer in the multiple tiers including at least one semiconductor die or chip, where the multiple units are electrically independent (e.g., isolated) from each other or electrically connected to each other. In the embodiments of the present disclosure, the semiconductor dies or chips in different layers have different sizes in the occupied area, and / or the semiconductor dies or chips in the same layer have different sizes in the occupied area.

[0060] In an embodiment, the manufacturing method is part of a wafer-level packaging process. It should be noted that the process steps described herein cover a part of the manufacturing process for fabricating the packaging structure. Therefore, it should be understood that additional processes may be provided before, during, and after the shown method, and some other processes may only be briefly described herein. In the present disclosure, it should be understood that in all the figures, the legends of the components are schematic and not drawn to scale. In all the various figures and illustrative embodiments of the present disclosure, devices that are similar or substantially the same as the previously described devices will use the same reference numbers, and certain details or descriptions of the same devices (e.g., materials, formation processes, positioning configurations, electrical connections, etc.) will not be repeated. For clarity of illustration, the various figures are shown using the orthogonal axes (X, Y, and Z) of the Cartesian coordinate system, and each figure is oriented according to the Cartesian coordinate system; however, the present disclosure is not specifically limited thereto.

[0061] Figures 1 to 13 is a schematic cross-sectional view or a schematic plan view of various stages in the manufacturing method of a semiconductor device 1000 according to some embodiments of the present disclosure, where Figures 1 to 2 and Figures 4 to 13 The schematic cross-sectional view is taken along the line AA depicted in the Figure 3 schematic plan view. Figure 14 is a schematic cross-sectional view of a semiconductor device (e.g., 1000A) according to other embodiments of the present disclosure.

[0062] Figure 15 is a schematic cross-sectional view of a semiconductor device (e.g., 1000B) according to other embodiments of the present disclosure. The embodiments are intended to provide further explanation of the settings but are not used to limit the scope of the present disclosure.

[0063] See Figure 1 Figure 1 , in some embodiments, a wafer W1 is provided. For example, the wafer W1 includes a variety of components (not shown) (also referred to as semiconductor components) formed therein. The components may include active components, non-active components, or a combination thereof. The components may include integrated circuit devices. The components may include transistors, capacitors, resistors, diodes, photodiodes, fuse devices, jumpers, inductors, or other similar devices. The functions of the components may include memory, processor, sensor, amplifier, power distribution (active component), input / output circuitry, etc. The components may be referred to as the semiconductor components of the present disclosure.

[0064] The wafer W1 may be a semiconductor wafer. In some embodiments, if a top view or a plan view along the direction Z (e.g., the XY plane) is considered, the wafer W1 is in the form of a wafer or a panel. In other words, the wafer W1 is processed in the form of a reconstructed wafer / panel. The wafer W1 may be in the form of a wafer size having a diameter of about 4 inches or greater. The wafer W1 may be in the form of a wafer size having a diameter of about 6 inches or greater. The wafer W1 may be in the form of a wafer size having a diameter of about 8 inches or greater. Alternatively, the wafer W1 may be in the form of a wafer size having a diameter of about 12 inches or greater. In some embodiments, the wafer W1 includes a plurality of device regions DR1 arranged in an array along the direction X and the direction Y, where each device region DR1 is a positioning (or predetermined) location of a semiconductor die or chip (e.g., 100). The directions X, Y, and Z may be different from each other. For example, the direction X is perpendicular to the direction Y, and the directions X and Y are independently perpendicular to the direction Z, as Figure 1 and Figure 3 shown. In the present disclosure, the direction Z may be referred to as the stacking direction, and the XY plane defined by the directions X and Y may be referred to as the plan view or the top view.

[0065] In addition, the semiconductor dies 100 of the wafer W1 formed in different and separate device regions DR1 are electrically independent of each other (e.g., electrically isolated). The semiconductor dies 100 may be individually referred to as semiconductor dies or chips, including digital chips, analog chips, or mixed-signal chips. In some embodiments, the semiconductor dies 100 are independently logic dies, such as a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), a deep learning processing unit (DPU), a tensor processing unit (TPU), a system-on-a-chip (SoC), an application processor (AP), and a microcontroller; a power management die, such as a power management integrated circuit (PMIC) die; a wireless and radio frequency (RF) die; a baseband (BB) die; a sensor die, such as a photo / image sensor chip; a micro-electro-mechanical-system (MEMS) die; a signal processing die, such as a digital signal processing (DSP) die; a front-end die, such as an analog front-end (AFE) die; an application-specific die, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA); combinations thereof; or similar components.In an alternative embodiment, the semiconductor die 100 is independently a memory die with or without a controller, where the memory die includes: a single-form die, such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a resistive random-access memory (RRAM), a magnetoresistive random-access memory (MRAM), a NAND flash memory, a wide I / O memory (WIO); a pre-stacked memory cube, such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module; a combination thereof; or similar components. In a further alternative embodiment, the semiconductor die 100 is independently: an artificial intelligence (AI) engine, such as an AI accelerator; a computing system, such as an AI server, a high-performance computing (HPC) system, a high-power computing device, a cloud computing system, a networking system, an edge computing system, an immersive memory computing system (ImMC), a System in Interposer Chip (SoIC) system, etc.; a combination thereof; or similar components. In some other embodiments, the semiconductor die 100 is independently an electrical and / or optical input / output (I / O) interface die, an integrated passive die (IPD), a voltage regulator die (VR), a local silicon interconnect die (LSI) with or without deep trench capacitor (DTC) features, a local silicon interconnect die with multi-tier functions such as electrical and / or optical network circuit interfaces, IPD, VR, DTC, or similar functions. The type of the semiconductor die 100 can be selected and specified based on requirements and design specifications, and thus is not specifically limited in this disclosure.

[0066] In some embodiments, all the semiconductor dies 100 are of the same type. In alternative embodiments, some of the semiconductor dies 100 are of different types from each other, while some of the semiconductor dies 100 are of the same type. In further alternative embodiments, all the semiconductor dies 100 are of different types. In some embodiments, all the semiconductor dies 100 are of the same size. In alternative embodiments, some of the semiconductor dies 100 are of different sizes from each other, while some of the semiconductor dies 100 are of the same size. In further alternative embodiments, all the semiconductor dies 100 are of different sizes. In some embodiments, all the semiconductor dies 100 are of the same shape. In alternative embodiments, some of the semiconductor dies 100 are of different shapes from each other, while some of the semiconductor dies 100 are of the same shape. In further alternative embodiments, all the semiconductor dies 100 are of different shapes. The type, size, and shape of each semiconductor die 100 are independent of each other and can be selected and designed based on requirements and design layouts. The present disclosure is not limited thereto.

[0067] Before performing a wafer sawing or cutting process along a saw street or cutting line CL (shown as a dashed line in the figure), the device regions DR1 of the wafer W1 are physically connected to each other. For example, as Figure 1 and Figure 3 shown, for example. In Figure 1 as well as Figures 4 to 6 , only two device regions DR1 included in the wafer W1 are shown for illustrative purposes. However, the present disclosure is not limited thereto. The number of device regions DR1 can be more than two. As Figure 1 shown, the wafer W1 may include a substrate 101, a device layer 102 disposed on the substrate 101, an interconnect 107 disposed on the device layer 102 and electrically coupled to the device layer 102, a plurality of connection structures 108 disposed on the interconnect 107 and electrically coupled to the interconnect 107, and a plurality of vias 111 embedded in the interconnect 107 and electrically coupled to the interconnect 107, the plurality of vias 111 further extending into the substrate 101.

[0068] In some embodiments, the substrate 101 includes a bulk semiconductor substrate, a crystalline silicon substrate, a doped semiconductor substrate (e.g., a p-type semiconductor substrate or an n-type semiconductor substrate), a semiconductor-on-insulator (SOI) substrate, or a similar substrate, etc. In certain embodiments, the substrate 101 includes one or more doped regions or various types of doped regions, depending on design requirements. In some embodiments, the doped regions are doped with a p-type dopant and / or an n-type dopant. For example, the p-type dopant is boron or BF2, and the n-type dopant is phosphorus or arsenic. The doped regions can be configured for n-type metal-oxide-semiconductor (NMOS) transistors or p-type metal-oxide-semiconductor (PMOS) transistors. The substrate 101 can be a silicon wafer. Generally, an SOI substrate has a layer of semiconductor material formed on an insulator layer. The insulator layer is, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. Other substrates can also be used, such as multi-layered substrates or gradient substrates. In some alternative embodiments, the substrate 101 includes a semiconductor substrate made of an elemental semiconductor (e.g., diamond or germanium in a crystalline, polycrystalline, or amorphous structure, etc.); a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, etc.); an alloy semiconductor (e.g., silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), etc.), combinations thereof, or other suitable materials. For example, the substrate 101 is a bulk silicon substrate. The compound semiconductor substrate can have a multi-layered structure, or the substrate can include a multi-layered compound semiconductor structure. Alloy SiGe can be formed on the silicon substrate. The SiGe substrate can be strained.

[0069] The device layer 102 may be disposed on the substrate 101, and the components (not shown) formed within the device layer 102 may be or include active components, passive components, other suitable electrical components, and / or combinations thereof. In some embodiments, these components are formed within the device layer 102, and the device layer 102 is disposed at the surface of the substrate 101 near the interconnect 107; these components are formed within the device layer 102, the device layer 102 is disposed at the surface of the substrate 101 near the interconnect 107, and these components further extend locally into the substrate 101; or combinations thereof. In some embodiments, as Figure 1 shown, the shown top surface of the substrate 101 is referred to as the active surface or front side of the substrate 101, and the shown bottom surface of the substrate 101 is referred to as the non-active surface or back side of the substrate 101, wherein the active surface or front side of the substrate 101 faces the non-active surface or back side of the substrate 101 along the direction Z, and the device layer 102 overlies (e.g., physically contacts) the active surface or front side of the substrate 101. In some embodiments, the device layer 102 is between the interconnect 107 and the substrate 101. The device layer 102 may include circuitry (not shown) formed in a front-end-of-line (FEOL) manufacturing process, and the interconnect 107 may be formed in a back-end-of-line (BEOL) manufacturing process.

[0070] In some embodiments, the interconnect 107 is disposed on the device layer 102, and the interconnect 107 is electrically coupled to the components formed within the device layer 102. That is, the interconnect 107 provides a wiring function for the components formed within the device layer 102. In some embodiments, at least some of the components formed within the device layer 102 are electrically connected to each other through the interconnect 107. As Figure 1 shown, the interconnect 107 may be stacked on the device layer 102 and include multiple built-up layers that are electrically connected to each other. For example, as Figure 1 shown, the interconnect 107 is formed on the device layer 102 and is electrically connected to the device layer 102. In some embodiments, the interconnect 107 includes one or more dielectric layers 103 (e.g., 1031, 1032, …, 103 N-2 , 103 N-1 and 103 N ) and one or more patterned conductive layers 106 (e.g., 1061, 1062, …, 106 N-2 , 106 N-1 , 106 N ). In some embodiments, each patterned conductive layer 106 (e.g., 1061, 1062, …, 106 N-2 , 106 N-1 and 106 N)including a line portion 105 (e.g., 1051, 1052, ..., 105 N-2 , 105 N-1 and 105 N ) extending along a horizontal direction (e.g., direction X or direction Y), a through-hole portion 104 (e.g., 1041, 1042, ..., 104 N-2 , 104 N-1 and 104 N ) extending along a vertical direction (e.g., direction Z), and / or a combination thereof. The patterned conductive layer 106 can be referred to as a metallization layer or a redistribution layer of the interconnect 107 to provide a wiring function, and can be collectively referred to as the wiring structure of the interconnect 107. The dielectric layer 103 can be collectively referred to as the dielectric structure of the interconnect 107 to provide protection for the metallization layer, redistribution layer, or wiring structure of the interconnect 107. In some embodiments, in the interconnect 107, the dielectric layer (e.g., 103) and the patterned conductive layer (e.g., 106) are alternately arranged. A dielectric layer and a corresponding metallization layer together can be considered a build-up layer of the interconnect 107 (e.g., 1031 and 1061; 1032 and 1062; 103 N-2 and 106 N-2 ; 103 N-1 and 106 N-1 ; 103 N and 106 N ; or similar layers). As Figure 1 shown, for example, the uppermost layer of the patterned conductive layer 106 (e.g., 106 N ) can be exposed in a touchable manner through the uppermost layer of the dielectric layer 103 (e.g., 103 N ) for external connection. In this disclosure, the number of layers of the dielectric layer 103 and the patterned conductive layer 106 is not limited to Figure 1 shown, and can be selected and specified according to the design layout and requirements. That is, the number of layers of the dielectric layer (e.g., 103) and the patterned conductive layer (e.g., 106) (e.g., N) can be 1 or greater than 1. In some embodiments, the line dimension (e.g., thickness and width) of the patterned conductive layer 106 gradually increases along the direction from the substrate 101 to the connection structure 108.

[0071] In addition, the inner connection 107 may further include one or more seed layers (not shown) to facilitate the formation of the patterned conductive layer 106, where the seed layer may be interposed between the patterned conductive layer 106 and the dielectric layer 103. In embodiments including a seed layer, a patterned conductive layer 106 and a corresponding seed layer (not shown) may together be referred to as the metallization layer or redistribution layer of the inner connection 107 to provide a wiring function. That is, for such embodiments, the patterned conductive layer 106 and the corresponding seed layer (not shown) may be collectively referred to as the wiring structure of the inner connection 107.

[0072] In some embodiments, the inner connection 107 may be formed by (but not limited to) the following: forming a blanket layer of a first dielectric material over the device layer 102; patterning the blanket layer of the first dielectric material to form a dielectric layer 1031 having a plurality of first openings (not labeled) that penetrate the dielectric layer 1031 and expose portions of the device layer 102 in an accessible manner; optionally forming a blanket layer of a first seed layer material over the dielectric layer 1031, the blanket layer of the first seed layer material extending into the first openings to line the first openings and contact the exposed portions of the device layer 102; forming a blanket layer of a first conductive material over the blanket layer of the first seed layer material; patterning the blanket layer of the first conductive material to form a patterned conductive layer 1061; using the patterned conductive layer 1061 as an etch mask to pattern the blanket layer of the first seed layer material and form a first corresponding seed layer, thereby forming a build layer (e.g., a first build layer including 1031 and 1061); forming a blanket layer of a second dielectric material over the patterned conductive layer 1061, the dielectric layer 1031, and the first corresponding seed layer (if any); patterning the blanket layer of the second dielectric material to form a dielectric layer 1032 having a plurality of second openings (not labeled) that penetrate the dielectric layer 1032 and expose the shown top surface of the patterned conductive layer 1061 in an accessible manner; optionally forming a blanket layer of a second seed layer material over the dielectric layer 1032, the blanket layer of the second seed layer material extending into the second openings to line the second openings and contact the exposed portions of the patterned conductive layer 1061; forming a blanket layer of a second conductive material over the blanket layer of the second seed layer material; patterning the blanket layer of the second conductive material to form a patterned conductive layer 1062; using the patterned conductive layer 1062 as an etch mask to pattern the blanket layer of the second seed layer material and form a second corresponding seed layer, thereby forming another build layer (e.g., a second build layer including 1032 and 1062); and then repeating the formation steps of forming the first and / or second build layers to form the remaining portions of the build layers (e.g., a third build layer, a fourth build layer,..., an (N - 2)th build layer (e.g., including 103 N-2 and 106 N-2)、the (N - 1)th construction layer (e.g., including 103 N- 1 and 106 N-1 ) and the Nth construction layer (e.g., including 103 N and 106 N ). Thus, the manufacturing of the internal connection 107 is completed. The internal connection 107 can be formed on the device layer 102 by a single damascene process or a dual damascene process. This disclosure is not limited thereto.

[0073] The material of each of the dielectric layers 103 (e.g., 1031, 1032, …, 103 N-2 , 103 N-1 and 103 N ) can be polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), nitride (e.g., silicon nitride), oxide (e.g., silicon oxide), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), a combination thereof, or the like, where lithography and / or etching processes can be used to pattern. The etching process can include dry etching, wet etching, or a combination thereof. The dielectric material blanket layer for forming the dielectric layer 103 (e.g., 1031, 1032,..., 103 N-2 , 103 N-1 and 103 N ) can be formed by appropriate manufacturing techniques, such as spin-on coating, chemical vapor deposition (CVD) (e.g., plasma-enhanced CVD (PECVD)), or the like. In one embodiment, the materials of the dielectric layers 103 (e.g., 1031, 1032, …, 103 N-2 , 103 N-1 , 103 N ) are the same as each other. As another option, some or all of the materials of the dielectric layers 103 (e.g., 1031, 1032, ……, 103 N-2 , 103 N-1 and 103 N ) are different from each other.

[0074] The optional seed layer is separately referred to as a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. For example, each layer in the optional seed layer may include a titanium layer and a copper layer located above the titanium layer. The seed layer material blanket layer for forming the optional seed layer may be formed in the manner of a blanket layer made of a metal or metal alloy material, and the present disclosure is not limited thereto. The material of each seed layer material blanket layer may include titanium, copper, molybdenum, tungsten, titanium nitride, titanium tungsten, a combination thereof, or the like, and may be formed, for example, by sputtering, physical vapor deposition (PVD), etc. The seed layer material blanket layer can be patterned by etching, such as a dry etching process, a wet etching process, or a combination thereof; the present disclosure is not limited thereto. In one embodiment, the materials of the optional seed layers are the same as each other. As another option, the materials of the optional seed layers can be different from each other.

[0075] For forming the patterned conductive layer 106 (e.g., 1061, 1062, …, 106 N-2 , 106 N-1 and 106 N ), the material of each conductive material blanket layer can be composed of a conductive material formed by electroplating or deposition, such as copper, copper alloy, aluminum, aluminum alloy, or a combination thereof, and can be patterned using photolithography and etching processes to form a plurality of conductive patterns / segments. In some embodiments, each conductive pattern / segment includes a line portion 105 (e.g., 1051, 1052,..., 105 N-2 , 105 N-1 and 105 N ) extending along a horizontal direction (e.g., direction X and / or Y) and / or a line portion 105 extending along a horizontal direction (e.g., direction X and / or Y) and a via portion 104 (e.g., 1041, 1042,..., 104 N-2 , 104 N-1 and 104 N ) extending along a vertical direction (e.g., direction Z), and the via portion 104 (e.g., 1041, 1042,..., 104 N-2 , 104 N-1 and 104 N ) is connected to the line portion 105 (e.g., 1051, 1052,..., 105 N-2 , 105 N-1 and 105 N ). In one embodiment, the patterned conductive layer 106 (e.g., 1061, 1062, …, 106 N-2 , 106 N-1 and 106N ) are made of the same material as each other. As another option, the patterned conductive layers 106 (e.g., 1061, 1062,..., 106 N-2 , 106 N-1 and 106 N ) are made of different materials from each other. Additionally, the line portions 105 (e.g., 1051, 1052,..., 105 N-2 , 105 N-1 and 105 N ) may be referred to as wires, conductive traces, conductive trenches, metallization lines, wirings, or redistribution lines, while the via portions 104 (e.g., 1041, 1042,..., 104 N-2 , 104 N-1 and 104 N ) may be referred to as conductive vias, metallization vias, wiring vias, or redistribution vias.

[0076] For example, after forming the build-up layer for the interconnect 107, a dielectric layer 109 and a connection structure 108 are formed over the dielectric layer 103 N and the patterned conductive layer 106 N . That is, the wafer W1 further includes the dielectric layer 109. In some embodiments, the connection structure 108 is electrically connected to the patterned conductive layer 106 N exposed by the dielectric layer 103 N . In some embodiments, each connection structure 108 includes a line portion 108t extending along a horizontal direction (e.g., direction X or direction Y), a via portion 108v extending along a vertical direction (e.g., direction Z), and / or a combination thereof. The formation and material of the dielectric layer 109 are similar or substantially the same as those of the dielectric layer 103, and the formation and material of the connection structure 108 (including 108t and 108v) are similar or substantially the same as those of the patterned conductive layer 106 (including 105 and 104), so they will not be repeated here.

[0077] For example, as Figure 1As shown, the connection structure 108 penetrates through the dielectric layer 109 and is laterally covered by the dielectric layer 109, wherein the shown top surface of the connection structure 108 is exposed by the dielectric layer 109 in an accessible manner. The connection structure 108 and the dielectric layer 109 may be collectively referred to as the bonding structure or connection layer of the wafer W1. In some embodiments, the shown top surface of the connection structure 108 is substantially level with the shown top surface of the dielectric layer 109. In other words, the shown top surface of the connection structure 108 and the shown top surface of the dielectric layer 109 are substantially coplanar. Before forming the connection structure 108 and after forming the dielectric layer 109, a seed layer (not shown) may be formed to facilitate the formation of the connection structure 108. The formation and materials of the optional seed layer have been described above, and thus will not be repeated here for the sake of brevity. In some embodiments, the material of the dielectric layer 109 is different from that of one or more of the dielectric layers 103. In certain embodiments, the material of the dielectric layer 109 is the same as that of the dielectric layer 103.

[0078] In some embodiments, the pitch P1 between two adjacent connection structures 108 is less than 1 μm and greater than 0 μm. The pitch P1 may be greater than 0 μm and may be less than or substantially equal to 0.95 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.90 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.85 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.80 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.75 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.70 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.65 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.60 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.55 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.50 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.45 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.40 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.35 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.30 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.25 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.20 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.15 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.10 μm or less, etc.

[0079] In some embodiments, vias 111 are formed in the wafer W1 and extend from the inner connection 107 to a location inside the substrate 101. For example, the vias 111 are formed through the patterned conductive layer 106 N-1(e.g., 105 N-1 ) is electrically coupled to the interconnect 107 by direct contact between the via 111 (e.g., its shown top surface). The wafer W1 may further include a plurality of liners 110 to line the sidewalls and the shown bottom surface of the via 111. In some embodiments, each of the vias 111 is covered by a corresponding liner 110. For example, the liners 110 are formed between the vias 111 and the substrate 101, between the vias 111 and the device layer 102, and between the vias 111 and a portion of the interconnect 107. In some embodiments, each of the vias 111 tapers from the interconnect 107 to the substrate 101. As another alternative, the vias 111 have substantially vertical sidewalls. In a cross-sectional view along the direction Z, the shape of the vias 111 depends on the design requirements and is not intended to limit the present disclosure. Additionally, in a top-down (plan) view in the XY plane, the shape of the vias 111 is circular. However, depending on the design requirements, the shape of the vias 111 can be oval, rectangular, polygonal, or a combination thereof; the present disclosure is not limited thereto. In some embodiments, the liners 110 cannot be exposed in a touchable manner by the back surface of the substrate 101.

[0080] The vias 111 can be formed of a conductive material such as copper, tungsten, aluminum, silver, a combination thereof, etc. The present disclosure does not limit the number of vias 111, which can be selected and specified according to the design layout and requirements. The liners 110 can be formed of a barrier material such as TiN, Ta, TaN, Ti, etc. In alternative embodiments, a dielectric liner (not shown) (e.g., silicon nitride, oxide, polymer, a combination thereof, etc.) can also be selectively formed between the liners 110 and the substrate 101, between the liners 110 and the device layer 102, and between the liners 110 and a portion of the interconnect 107. Alternatively, the liners 110 can also be omitted.

[0081] The vias 111, the liners 110, and the optional dielectric liner can be formed (but not limited to) by the following steps: forming a plurality of depressions in the interconnect 107 before forming the patterned conductive layer 106 of the (N - 1)th build layer of the interconnect 107; depositing an optional dielectric material, a barrier material, and a conductive material in the depressions respectively; and removing the excess material located on the plane of the shown opening of the depressions. For example, the depressions are lined with an optional dielectric liner so as to be laterally separated from the liners 110, and the liners 110 line the sidewalls and the shown bottom surface of the vias 111 to be separated from the substrate 101, the device layer 102, and a portion of the interconnect 107. After forming the vias 111, the liners 110, and the optional dielectric liner, the remaining components of the interconnect 107 (e.g., 106 N-1 、103 N-1 、103 N and 106 N)To fabricate the internal connection 107. In some embodiments, the vias 111 are formed by using a via-first approach. In such embodiments, the vias 111 are formed before forming the internal connection 107. As an alternative, the vias 111 can be formed by using a via-last approach. In some embodiments, the vias 111 are electrically coupled to components formed in the device layer 102 through the internal connection 107. It should be understood that each device region DR1 is or includes a semiconductor die (or chip) 100.

[0082] See Figure 2 , in some embodiments, a wafer W2 is provided. For example, the wafer W2 includes various components (not shown) (also referred to as semiconductor components) formed therein. The components can include active components, passive components, or a combination thereof. The components can include integrated circuit devices. The components can include transistors, capacitors, resistors, diodes, photodiodes, fuse devices, jumpers, inductors, or other similar devices. The functions of the components can include memory, processor, sensor, amplifier, power distribution, input / output circuitry, etc. The components can be referred to as the semiconductor components of the present disclosure. The wafer W2 can be a semiconductor wafer. In some embodiments, if a top view or a plan view along the direction Z (e.g., the XY plane) is considered, the wafer W2 is in the form of a wafer or a panel. In other words, the wafer W2 is processed in the form of a reconstructed wafer / panel. The wafer W2 can be in the form of a wafer size having a diameter of about 4 inches or larger. The wafer W2 can be in the form of a wafer size having a diameter of about 6 inches or larger. The wafer W2 can be in the form of a wafer size having a diameter of about 8 inches or larger. Alternatively, the wafer W2 can be in the form of a wafer size having a diameter of about 12 inches or larger. In some embodiments, the wafer W2 includes a plurality of device regions DR2 arranged in an array along the direction X and the direction Y, where each device region DR2 is a positioning (or predetermined) location of a semiconductor die or chip (e.g., 200). Additionally, the semiconductor dies 200 of the wafer W2 formed in different and separate device regions DR2 are electrically independent of each other (e.g., electrically isolated).

[0083] Before performing a wafer sawing or cutting process along a saw street or a cutting line CL (shown as a dashed line in the figure), the device regions DR2 of the wafer W2 are physically connected to each other, e.g., as Figure 2 and Figure 3 shown. In Figure 2 and Figures 4 to 6 , only two device regions DR2 included in the wafer W2 are shown for illustrative purposes, however, the present disclosure is not limited thereto. The number of device regions DR2 can be more than two. As Figure 2As shown, the wafer W2 may include a substrate 201, a device layer 202 disposed on the substrate 201, an interconnect 207 disposed on the device layer 202 and electrically coupled to the device layer 202 (including one or more dielectric layers 203 (e.g., 2031, 2032, …, 203 N-2 , 203 N-1 and 203 N ), and one or more patterned conductive layers 206 (e.g., 2061, 2062, …, 206 N-2 , 206 N-1 and 206 N ), a plurality of connection structures 208 disposed on the interconnect 207 and electrically coupled to the interconnect 207, and a dielectric layer 209 that laterally covers the connection structures 208. In some embodiments, each patterned conductive layer 206 (e.g., 2061, 2062, …, 206 N-2 , 206 N-1 and 206 N ) includes a line portion 205 (e.g., 2051, 2052, …, 205 N-2 , 205 N-1 and 205 N ) extending along a horizontal direction (e.g., direction X or direction Y), a via portion 204 (e.g., 2041, 2042, …, 204 N-2 , 204 N-1 and 204 N ) extending along a vertical direction (e.g., direction Z), and / or a combination thereof.

[0084] The patterned conductive layer 206 may be referred to as a metallization layer or a redistribution layer of the interconnect 207 to provide a wiring function, and may be collectively referred to as the wiring structure of the interconnect 207. The dielectric layers 203 may be collectively referred to as the dielectric structure of the interconnect 207 to provide protection for the metallization layer, redistribution layer, or wiring structure of the interconnect 207. A dielectric layer and a corresponding metallization layer together may be regarded as a building layer of the interconnect 207 (e.g., 2031 and 2061; 2032 and 2062; 203 N-2 and 206 N-2 ; 203 N-1 and 206 N-1 ; 203 N and 206 N ; 203 N-1 and 206 N-1 ; 203 N and 206 N ; or similar layers). In the present disclosure, the number of layers of the dielectric layer 203 and the patterned conductive layer 206 is not limited to Figure 2As shown, it can be selected and specified according to the design layout and requirements. That is, the number (e.g., N) of the number of dielectric layers (e.g., 203) and patterned conductive layers (e.g., 206) can be 1 or greater than 1. In some embodiments, the line dimensions (e.g., thickness and width) of the patterned conductive layer 206 gradually increase along the direction from the substrate 201 to the connection structure 208. Additionally, the interconnect 207 may further include one or more seed layers (not shown) to facilitate the formation of the patterned conductive layer 206. In embodiments including a seed layer, one patterned conductive layer 206 and a corresponding one seed layer (not shown) may be collectively referred to as a metallization layer or redistribution layer of the interconnect 207 to provide a wiring function. That is, for such embodiments, the patterned conductive layer 206 and the corresponding seed layer (not shown) may be collectively referred to as the wiring structure of the interconnect 207. In some embodiments, the pitch P2 between two adjacent connection structures 208 is less than 1 μm and greater than 0 μm. The pitch P2 may be greater than 0 μm and may be less than or substantially equal to 0.95 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.90 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.85 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.80 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.75 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.70 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.65 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.60 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.55 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.50 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.45 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.40 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.35 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.30 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.25 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.20 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.15 μm or less, may be greater than 0 μm and may be less than or substantially equal to 0.10 μm or less, etc.The details, formation, and materials of the substrate 201, device layer 202, interconnect 207 (e.g., including 203 and 206 (including 204 and 205)), connection structure 208 (including line portion 208t and via portion 208v), dielectric layer 209, and optional seed layer are similar to or substantially the same as the details, formation, and materials of the substrate 101, device layer 102, interconnect 107 (e.g., including 103 and 106 (including 104 and 105)), connection structure 108 (including 108t and 108v), dielectric layer 109, and optional seed layer (as described in Figure 1 ), and thus will not be repeated herein for the sake of brevity. It should be understood that each device region DR2 is or includes a semiconductor die (or chip) 200.

[0085] In some embodiments, all the semiconductor dies 200 are of the same type. In alternative embodiments, some of the semiconductor dies 200 are of different types from each other, while some of the semiconductor dies 200 are of the same type. In further alternative embodiments, all the semiconductor dies 200 are of different types. In some embodiments, all the semiconductor dies 200 are of the same size. In alternative embodiments, some of the semiconductor dies 200 are of different sizes from each other, while some of the semiconductor dies 200 are of the same size. In further alternative embodiments, all the semiconductor dies 200 are of different sizes. In further alternative embodiments, all the semiconductor dies 200 are of the same shape. In alternative embodiments, some of the semiconductor dies 100 are of different shapes from each other, while some of the semiconductor dies 100 are of the same shape. In further alternative embodiments, all the semiconductor dies 200 are of different shapes. The type, size, and shape of each semiconductor die 200 are independent of each other and can be selected and designed based on requirements and design layouts, and the present disclosure is not limited thereto.

[0086] In a non - limiting example, the size of the semiconductor dies 200 included in the wafer W2 is different from (e.g., smaller than) the size of the semiconductor dies 100 included in the wafer W1. In another non - limiting example, the size of the semiconductor dies 200 included in the wafer W2 is different from (e.g., larger than) the size of the semiconductor dies 100 included in the wafer W1. In another non - limiting example, the size of the semiconductor dies 200 included in the wafer W2 is substantially equal to the size of the semiconductor dies 100 included in the wafer W1. Alternatively, as another option, a combination of the above conditions can also be adopted.

[0087] See Figure 4 , in some embodiments, the wafer W2 is placed on top of the wafer W1 and bonded to the wafer W1. For example, as Figure 4As shown, each device region DR2 in wafer W2 is arranged to overlap a corresponding device region DR1 in wafer W1 in a vertical projection along direction Z. In this case, in a cross-sectional view, the device region DR2 of wafer W2 and the device region DR1 of wafer W1 overlap each other in a one-to-one configuration. In some embodiments, wafer W2 is placed above wafer W1 by a pick-and-place process for forming a bond. In some embodiments, wafer W2 is bonded to wafer W1 by wafer-on-wafer (WoW) bonding.

[0088] For example, wafer W2 is bonded to wafer W1 by a bonding process that includes metal-to-metal bonding and dielectric-to-dielectric bonding. For example, wafer W2 is disposed on wafer W1 (e.g., physical contact) and electrically connected to wafer W1. In some embodiments, as Figure 4 shown, the connection structure 208 of wafer W2 and the connection structure 108 of wafer W1 support each other and are bonded together by direct metal-to-metal bonding (e.g., "copper" to "copper") bonding), for example. Additionally, as Figure 4 shown, the dielectric layer 209 of wafer W2 and the dielectric layer 109 of wafer W1 support each other and are bonded together by direct dielectric-to-dielectric bonding (e.g., "oxide" to "oxide" bonding, "nitride" to "oxide" bonding, or "nitride" to "nitride") bonding), for example. In such an embodiment, the bonding interface IF1 including a metal-to-metal bonding interface (e.g., "copper" to "copper" bonding interface) and a dielectric-to-dielectric bonding interface (e.g., "oxide" to "oxide" bonding interface, "nitride" to "oxide" bonding interface, or "nitride" to "nitride" bonding interface) coexisting between wafer W2 and wafer W1 is considered the bonding interface between wafer W2 and wafer W1.

[0089] It should be noted that the above joining method is only an example and is not intended to be limiting. There may be an offset (bias) between the sidewalls of the connecting structure 208 and the sidewalls of the connecting structure 108 respectively located below it. Since one of the connecting structure 208 and the connecting structure 108 may have a larger joining surface than the other, direct metal-to-metal joining can still be achieved even in the case of misalignment, and the reliability of the electrical connection between the wafer W2 and the wafer W1 can still be ensured. In this way, for some embodiments, the dielectric layer 209 directly adjacent to the connecting structure 208 is joined to a part of each of the connecting structures 108 (for example, dielectric-to-metal joining), or the dielectric layer 109 directly adjacent to the connecting structure 108 is joined to a part of each of the connecting structures 208 (for example, dielectric-to-metal joining).

[0090] In some embodiments, after joining the wafers W1 and W2, a stacked structure in the form of a wafer is formed. In such a wafer-form stacked structure, the semiconductor dies 200 of the wafer W2 are electrically connected and electrically communicated with the semiconductor dies 200 of the wafer W1 respectively. In addition, the semiconductor dies 200 of the wafer W2 formed in different and separate device regions DR2 are electrically independent of each other (for example, electrically isolated), and the semiconductor dies 100 of the wafer W1 formed in different and separate device regions DR1 are electrically independent of each other (for example, electrically isolated).). Due to the presence of the connecting structure 108 (with pitch P1) and the connecting structure 208 (with pitch P2), the overall wiring density of the semiconductor device 1000 is greatly increased, thereby obtaining higher performance and reduced manufacturing costs.

[0091] See Figure 5 , in some embodiments, a first planarization process is performed on the substrate 101 to thin the substrate 101 and expose the vias 111 in an accessible manner. For example, as Figure 5 shown, a part of the substrate 101 and a part of the pad 110 are removed from the wafer W1 of the stacked structure, thereby exposing the vias 111. In some cases, during the process of removing the part of the substrate 101 and the part of the pad 110, a part of the vias 111 may also be slightly removed. Then, a patterning process is performed on the substrate 101 to further remove a part of the substrate 101 to form a substrate 101' having a patterned bottom surface S101', such that a part of each via 111 and a part of each pad 110 protrude from the patterned bottom surface S101' of the substrate 101'. For example, the patterning process may include an etching process (such as wet etching or dry etching) or a similar process. The present disclosure is not limited thereto. As Figure 5As shown, the liner 110 may cover the entire sidewall of the via 111; however, the present disclosure is not limited thereto. In one embodiment, the liner 110 may only cover the sidewall of the via 111 that is embedded in the substrate 101'. That is, after the first planarization process, for example, the liner 110 disposed on the sidewall of the portion of the via 111 that protrudes from the patterned bottom surface S101' of the substrate 101' is removed during the patterning process. The first planarization process may include a grinding process, a chemical mechanical polishing (CMP) process, an etching process, a combination thereof, and the like. The etching process may include dry etching, wet etching, or a combination thereof.

[0092] In some embodiments, a dielectric material (not shown) is formed over the substrate 101'. In some embodiments, the dielectric material is directly formed over the substrate 101', the via 111, and the liner 110, wherein the substrate 101', the via 111, and the liner 110 are covered by the dielectric material and are in physical contact with the dielectric material. In some embodiments, the dielectric material may be formed as a blanket layer of the dielectric material. In some embodiments, the dielectric material may be a polymer layer made of PI, PBO, BCB, or any other suitable polymer-based dielectric material, etc. In some embodiments, the dielectric material may be an Ajinomoto Buildup Film (ABF), a Solder Resist film (SRF), or a similar film. In some embodiments, the dielectric material may be formed by a suitable fabrication technique such as spin-coating, lamination, deposition, or a similar technique. Thereafter, a second planarization process is performed on the dielectric material to form a dielectric layer 112 that laterally covers the via 111 and the liner 110, wherein the dielectric layer 112 exposes the bottom surface S111 of the via 111 and the bottom surface S110 of the liner 110 and covers the patterned bottom surface S101' of the substrate 101'. In some embodiments, during the second planarization process, the dielectric material located above the patterned bottom surface S101' of the substrate 101' and laterally beside the protruding portion of the via 111 is retained, while the remaining dielectric material is removed; the remaining dielectric material constitutes the dielectric layer 112. In some embodiments, the second planarization process may include a grinding process, a CMP process, an etching process, a combination thereof, and the like. The etching process may include dry etching, wet etching, or a combination thereof. For example, as Figure 5 shown, the surface S112 of the dielectric layer 112 is substantially flush with the bottom surface S111 of the via 111 and the bottom surface S110 of the liner 110. That is, the surface S112 of the dielectric layer 112 is substantially coplanar with the bottom surface S111 of the via 111 and the bottom surface S110 of the liner 110.

[0093] In some embodiments, after the first planarization process and / or the second planarization process, an optional cleaning step may be performed to clean and remove residues generated from the planarization process. However, the present disclosure is not limited thereto, and the first and / or second planarization process may be performed by any other suitable method.

[0094] See Figure 6 , in some embodiments, a dielectric layer 113 and a plurality of connection structures 114 are formed over a wafer W1 of a stacked structure, wherein the connection structures 114 are electrically coupled to the interconnect 107 through vias 111. Some of the connection structures 114 may be electrically coupled to components formed in the device layer 102 through vias 111 and the interconnect 107, and some of the connection structures 114 may be electrically coupled to components formed in the device layer 202 through vias 111, the interconnect 107, and the interconnect 207, as Figure 6 shown. The pitch P10 between two adjacent connection structures 114 is greater than or substantially equal to 1 μm, in some embodiments. In some embodiments, the pitch P10 is greater than the pitches P1 and P2. The formation and materials of each of the dielectric layer 113 and the connection structures 114 are similar or substantially the same as those of each of the dielectric layer 103 and the patterned conductive layer 106 (e.g., 105) discussed previously in Figure 1 , and thus are not repeated herein for the sake of brevity.

[0095] In some embodiments, a dicing (singulation) process is performed to dice the wafers W1 and W2 of the stacked structure, thereby forming a plurality of stacked units 50. See Figure 7 , and only one stacked unit 50 is shown for illustrative purposes. In one embodiment, the dicing (singulation) process is a wafer dicing process including mechanical blade sawing or laser cutting. The present disclosure is not limited thereto. In some embodiments, each stacked unit 50 includes a semiconductor die 100 (e.g., located in the device region DR1 of the wafer W1) and a semiconductor die 200 (e.g., located in the device region DR2 of the wafer W2) stacked thereon, wherein the semiconductor die 200 is electrically connected and electrically coupled to the semiconductor die 100 through the bonding connection structure 208 and the connection structure 108.

[0096] See Figure 8, in some embodiments, a wafer W3 is provided. For example, wafer W3 includes various components (not shown) (also referred to as semiconductor components) formed therein. The components may include active components, passive components, or a combination thereof. The components may include integrated circuit devices. The components may include transistors, capacitors, resistors, diodes, photodiodes, fuse devices, jumpers, inductors, or other similar devices. The functions of the components may include memory, processor, sensor, amplifier, power distribution, input / output circuitry, etc. The components may be referred to as the semiconductor components of the present disclosure. Wafer W3 may be a semiconductor wafer. In some embodiments, if a top view or plan view along the Z direction (e.g., the XY plane) is considered, then wafer W3 is in the form of a wafer or panel. In other words, wafer W3 is processed in the form of a reconstructed wafer / panel. Wafer W3 may be in the form of a wafer size having a diameter of about 4 inches or greater. Wafer W3 may be in the form of a wafer size having a diameter of about 6 inches or greater. Wafer W3 may be in the form of a wafer size having a diameter of about 8 inches or greater. Alternatively, wafer W3 may be in the form of a wafer size having a diameter of about 12 inches or greater. In some embodiments, wafer W3 includes a plurality of device regions DR3 arranged in an array along the X direction and the Y direction, where each device region DR3 is a positioning (or predetermined) location of a semiconductor die or chip (e.g., 300).

[0097] Before performing a wafer sawing or cutting process (shown by the dashed line in the figure) along the dicing street or cut line CL, the device regions DR3 of wafer W3 are physically connected to each other. For example, as Figure 8 shown. In Figures 8 to 13 , only two device regions DR3 included in wafer W3 are shown for illustrative purposes, however, the present disclosure is not limited thereto. The number of device regions DR3 may exceed two. As Figure 8 shown, wafer W3 may include a substrate 301, a device layer 302 disposed on the substrate 301, and interconnects 307 disposed on the device layer 302 and electrically coupled to the device layer 302 (including one or more dielectric layers 303 (e.g., 3031, 3032,..., 303 N-2 , 303 N-1 and 303 N ) and one or more patterned conductive layers 306 (e.g., 3061, 3062,..., 306 N-2 , 306 N-1 and 306 N)) Multiple connection structures 318 disposed on the inner connection 307 and electrically coupled to the inner connection 307, a dielectric layer 319 laterally covering the connection structure 208, multiple vias 311 embedded in the inner connection 307 and electrically coupled to the inner connection 307 and further extending into the substrate 301, and multiple pads 110 lining the sidewalls and bottom surfaces of the vias 311. In some embodiments, each patterned conductive layer 306 (e.g., 3061, 3062, …, 306 N-2 306 N-1 and 306 N ) includes line portions 305 (e.g., 3051, 3052, …, 305 N-2 305 N-1 and 305 N ) extending along a horizontal direction (e.g., direction X or direction Y), via portions 304 (e.g., 3041, 3042, …, 304 N-2 304 N-1 and 304 N ) extending along a vertical direction (e.g., direction Z), and / or combinations thereof.

[0098] The patterned conductive layer 306 may be referred to as a metallization layer or a redistribution layer of the inner connection 307 to provide a wiring function, and may be collectively referred to as the wiring structure of the inner connection 307. The dielectric layer 303 may be collectively referred to as the dielectric structure of the inner connection 307 to provide protection for the metallization layer, redistribution layer or wiring structure of the inner connection 307. A dielectric layer and a corresponding metallization layer together may be regarded as a building layer of the inner connection 307 (e.g., 3031 and 3061; 3032 and 3062; 303 N-2 and 306 N-2 ; 303 N-1 and 306 N-1 ; 303 N and 306 N ; or similar layers). In the present disclosure, the number of layers of the dielectric layer 303 and the patterned conductive layer 306 is not limited to Figure 8As shown, it can be selected and specified according to the design layout and requirements. That is, the number (e.g., N) of the number of dielectric layers (e.g., 303) and patterned conductive layers (e.g., 306) can be 1 or greater than 1. In some embodiments, the line dimensions (e.g., thickness and width) of the patterned conductive layer 306 gradually increase along the direction from the substrate 301 to the connection structure 318. Additionally, the interconnect 307 may further include one or more seed layers (not shown) to facilitate the formation of the patterned conductive layer 306. In embodiments including a seed layer, one patterned conductive layer 306 and a corresponding one seed layer (not shown) may be collectively referred to as a metallization layer or redistribution layer of the interconnect 307 to provide a wiring function. That is, for such embodiments, the patterned conductive layer 306 and the corresponding seed layer (not shown) may be collectively referred to as the wiring structure of the interconnect 307. In some embodiments, the pitch P3 between two adjacent connection structures 318 is greater than or substantially equal to 1 μm. In some embodiments, the pitch P3 is greater than the pitches P1 and P2. On the other hand, the spacing P3 can be less than, greater than, or substantially equal to the spacing P10, and the present disclosure is not limited thereto. The number of vias 311 can be greater than Figure 8 As shown, it can be selected and specified based on requirements and design specifications. The details, formation, and materials of the substrate 301, device layer 302, interconnect 307 (e.g., including 303 and 306 (including 304 and 305)), optional seed layer, via 311, and pad 310 are similar to or substantially the same as those of the substrate 101, device layer 102, interconnect 107 (e.g., including 103 and 106 (including 104 and 105)), optional seed layer, via 111, and pad 110 discussed previously Figure 1 in terms of their respective details, formation, and materials. The formation and materials of the dielectric layer 319 and the connection structure 318 (including the line portion 318t and via portion 318v) are similar to or substantially the same as those of the dielectric layer 103 and the patterned conductive layer 106 (including 105 and 104) discussed previously in Figure 1 and thus are not repeated herein for the sake of brevity. It should be understood that each device region DR3 is or includes a semiconductor die (or chip) 300. Additionally, the semiconductor dies 100 of the wafer W3 formed in different and separate device regions DR3 are electrically independent of each other (e.g., electrically isolated).

[0099] In some embodiments, all of the semiconductor die 300 are of the same type. In alternative embodiments, some of the semiconductor die 300 are of different types from each other, while some of the semiconductor die 300 are of the same type. In further alternative embodiments, all of the semiconductor die 300 are of different types. In some embodiments, all of the semiconductor die 300 are of the same size. In alternative embodiments, some of the semiconductor die 300 are of different sizes from each other, while some of the semiconductor die 300 are of the same size. In further alternative embodiments, all of the semiconductor die 300 are of different sizes. In some embodiments, all of the semiconductor die 300 are of the same shape. In alternative embodiments, some of the semiconductor die 300 are of different shapes from each other, while some of the semiconductor die 300 are of the same shape. In further alternative embodiments, all of the semiconductor die 300 are of different shapes. The type, size, and shape of each semiconductor die 300 are independent of each other and can be selected and designed based on requirements and design layout, and the present disclosure is not limited thereto.

[0100] In one non-limiting example, the size of the semiconductor die 300 included in the wafer W3 is different from (e.g., smaller than) the size of the semiconductor die 100 included in the wafer W1. In another non-limiting example, the size of the semiconductor die 300 included in the wafer W3 is different from (e.g., larger than) the size of the semiconductor die 100 included in the wafer W1. In another non-limiting example, the size of the semiconductor die 300 included in the wafer W3 is substantially equal to the size of the semiconductor die 100 included in the wafer W1. Alternatively, as another option, a combination of the above conditions may also be employed.

[0101] In one non-limiting example, the size of the semiconductor die 300 included in the wafer W3 is different from (e.g., smaller than) the size of the semiconductor die 200 included in the wafer W2. In another non-limiting example, the size of the semiconductor die 300 included in the wafer W3 is different from (e.g., larger than) the size of the semiconductor die 200 included in the wafer W2. In another non-limiting example, the size of the semiconductor die 300 included in the wafer W3 is substantially equal to the size of the semiconductor die 200 included in the wafer W2. Alternatively, as another option, a combination of the above conditions may also be employed.

[0102] See Figure 9 , in some embodiments, one or more stacking units 50 are picked up and placed above the wafer W3. In some embodiments, the stacking units 50 are respectively arranged in the device area DR3, as Figure 9 shown. For illustrative purposes and simplicity, in Figure 9Only two stacked units 50 are shown herein, however, the present disclosure is not limited thereto. The number of stacked units 50 may exceed two. The number of stacked units 50 can be selected and designed based on requirements and design layouts. The number of stacked units 50 corresponds to the number of device regions DR3 included in the wafer W3. In one non-limiting example, the stacked units 50 overlap with the semiconductor die 300 (e.g., located in the device region DR3 of the wafer W3) in a one-to-one architecture manner in the Z direction, as Figure 9 shown. In another non-limiting example, the stacked units 50 overlap with the semiconductor die 300 (e.g., located in the device region DR3 of the wafer W3) in a plurality-to-one configuration (e.g., a two-to-one configuration, a three-to-one configuration, a four-to-one configuration, a five-to-one configuration) in the Z direction.

[0103] After placing the stacked units 50, a bonding process is performed to bond the stacked units 50 to a corresponding one of the semiconductor dies 300 in the wafer W3 overlapping therewith in the Z direction. For example, the stacked units 50 are bonded to the wafer W3 through a bonding process, and the bonding process includes metal-to-metal bonding and dielectric-to-dielectric bonding. For example, the stacked units 50 are disposed on the wafer W3 (e.g., physical contact) and electrically connected to the wafer W3. In some embodiments, as Figure 9 shown, the connection structure 114 of the semiconductor die 100 of the stacked unit 50 and the connection structure 318 (e.g., 318t) of the wafer W3 support each other and are bonded together through direct metal-to-metal bonding (e.g., "copper" to "copper" bonding), for example. Additionally, as Figure 9 shown, the dielectric layer 113 of the semiconductor die 100 of the stacked unit 50 abuts against the dielectric layer 319 of the wafer W3 and is bonded together through direct dielectric-to-dielectric bonding (e.g., "oxide" to "oxide" bonding, "nitride" to "oxide" bonding, or "nitride" to "nitride" bonding), for example. In such an embodiment, the bonding interface IF2 including the metal-to-metal bonding interface (e.g., "copper" to "copper" bonding interface) and the dielectric-to-dielectric bonding interface (e.g., "oxide" to "oxide" bonding interface, "nitride" to "oxide" bonding interface, or "nitride" to "nitride" bonding interface) coexisting between the stacked unit 50 and the wafer W3 is considered as the bonding interface between the stacked unit 50 and the wafer W3.

[0104] It should be noted that the above joining methods are only examples and are not intended to be limiting. There may be an offset (bias) between the sidewalls of the connection structure 114 and the sidewalls of the connection structures 318 respectively located below it. Since one of the connection structure 114 and the connection structure 318 may have a larger joining surface than the other, a direct metal-to-metal join can still be achieved even in the case of misalignment, and the reliability of the electrical connection between the stacked unit 50 and the wafer W3 can still be ensured. In this way, for some embodiments, the dielectric layer 113 directly adjacent to the connection structure 114 is joined to a part of each of the connection structures 318 (e.g., dielectric-to-metal joining), or the dielectric layer 319 directly adjacent to the connection structure 318 is joined to a part of each of the connection structures 114 (e.g., dielectric-to-metal joining). In an embodiment where the stacked unit 50 overlaps the semiconductor die 300 in a one-to-one architecture (e.g., in the device area DR3 of the wafer W3), each single stacked unit 50 overlying a single semiconductor die 300 is electrically independent (e.g., electrically isolated) from each other. In an embodiment where the stacked unit 50 overlaps the semiconductor die 300 in a many-to-one architecture (e.g., in the device area DR3 of the wafer W3), the stacked units 50 overlying one corresponding semiconductor die 300 and the stacked units 50 overlying the remaining semiconductor dies 300 are electrically independent (e.g., electrically isolated). In some embodiments, the stacked unit 50 is joined to the wafer W3 by chip-on-wafer (CoW) bonding.

[0105] See Figure 10 , in some embodiments, the packaged stacked unit 50 is in an insulating material. In some embodiments, the insulating encapsulant 800m is formed conformally on the stacked unit 50 and above the wafer W3, where the stacked unit 50 and the wafer W3 exposed through the stacked unit 50 are completely covered by the insulating encapsulant 800m. The insulating encapsulant 800m can be made of a dielectric material (such as: oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), tetra-ethyl-ortho-silicate (TEOS), or the like) or any suitable gap-filling insulating material, and can be formed by deposition (e.g., CVD process). For example, as Figure 10 shown, the stacked unit 50 cannot be exposed in a touchable manner through the insulating encapsulant 800m.

[0106] As another alternative, the insulating encapsulant 800m can be a molding compound, a molding underfill, a resin (such as an epoxy resin-based resin), or the like, which is formed by a molding process such as a compression molding process or a transfer molding process. The insulating encapsulant 800m can include a polymer (such as an epoxy resin, a phenolic resin, a silicon-containing resin, or other suitable resin) or other suitable materials. Alternatively, the insulating encapsulant 800m can include an acceptable insulating encapsulant material. In some embodiments, the insulating encapsulant 800m further includes an inorganic filler or an inorganic compound (such as silica, clay, etc.) that can be added to the insulating encapsulant 800m to optimize the coefficient of thermal expansion (CTE) of the insulating encapsulant 800m. The present disclosure is not limited thereto.

[0107] See also Figure 10 and Figure 11 , in some embodiments, a third planarization process is performed on the insulating encapsulant 800m to form an insulating encapsulant 800 that exposes the stacked unit 50 (e.g., the semiconductor die 200). For example, a portion of the insulating encapsulant 800m is removed to form an insulating encapsulant 800 having a shown top surface S800, where the shown top surface S800 of the insulating encapsulant 800 exposes the semiconductor die 200 (e.g., the surface S201) in an accessible manner. For example, the shown top surface S800 of the insulating encapsulant 800 is substantially flush with the surface S201 of the semiconductor die 200 included in the stacked unit 50. In other words, the shown top surface S800 of the insulating encapsulant 800 is substantially coplanar with the surface S201 of the semiconductor die 200 included in the stacked unit 50.

[0108] In some embodiments, after the third planarization process, an optional cleaning step can be performed to clean and remove the residues generated from the third planarization process. However, the present disclosure is not limited thereto, and the third planarization process can be performed by any other suitable method. Additionally, in the third planarization process, a portion of each substrate 201 of the semiconductor die 200 included in the stacked unit 50 can also be slightly removed. The present disclosure is not limited thereto.

[0109] See Figure 12 , in some embodiments, after forming the insulating encapsulant 800, a dielectric layer 500 is formed over the insulating encapsulant 800 and the stacked unit 50 exposed by the insulating encapsulant 800. The dielectric layer 500 can be disposed on the insulating encapsulant 800 and the stacked unit 50, and the insulating encapsulant 800 and the stacked unit 50 can be disposed between the wafer W3 and the dielectric layer 500, as Figure 12As shown. In some embodiments, the dielectric layer 500 is a blanket layer of a dielectric material composed of nitrides such as silicon nitride, oxides such as silicon oxide, oxynitrides such as silicon oxynitride, etc. As an alternative, the dielectric layer 500 can be a polymer layer made of a dielectric material such as PI, PBO, BCB, or any other suitable polymer. As another alternative, the dielectric layer 500 can be an ABF, SR film, etc. As Figure 12 shown, for example, the top surface S500 of the dielectric layer 500 shown is level and can have high coplanarity. The dielectric layer 500 can be formed by appropriate manufacturing techniques such as spin coating, lamination, deposition, etc.

[0110] Subsequently Figure 12 , in some embodiments, the carrier 700 coated with the dielectric layer 600 is bonded to the wafer W3 through a bonding process, where the dielectric layer 600 and the dielectric layer 500 are disposed between the carrier 700 and the wafer W3. The bonding process can include dielectric-to-dielectric bonding. As Figure 9 shown, the dielectric layer 600 formed on the carrier 700 and the dielectric layer 500 formed on the insulating encapsulant 800 and the semiconductor die 200 support each other and are bonded together through direct dielectric-to-dielectric bonding (such as "oxide" to "oxide" bonding, "nitride" to "oxide" bonding, or "nitride" to "nitride" bonding), for example. In such an embodiment, the bonding interface IF3 including the dielectric-to-dielectric bonding interface (such as "oxide" to "oxide" bonding interface, "nitride" to "oxide" bonding interface, or "nitride" to "nitride" bonding interface) coexisting between the dielectric layer 500 and the dielectric layer 600 is considered the bonding interface of the dielectric layer 500 and the dielectric layer 600. However, the present disclosure is not limited thereto, and the bonding interface IF3 can include an "inorganic dielectric" to "inorganic dielectric" bonding interface, an "inorganic dielectric" to "organic dielectric" bonding interface, or an "organic dielectric" to "organic dielectric" bonding interface.

[0111] In a non-limiting example, since the material of the carrier 700 is a Si substrate, the carrier 700 can act as a heat dissipation device for a semiconductor device (e.g., Figure 13 1000 depicted in). In such an embodiment, the carrier 700 can also be used for warp control. In another non-limiting example, the carrier 700 can be a mechanical support structure that can not be removed after the manufacturing method of the semiconductor structure. In another non-limiting example, since the carrier 700 is a glass carrier, the carrier 700 can be removed during or after the manufacturing of the semiconductor device (e.g., Figure 14 1000A depicted in and / or Figure 15 1000B depicted in).

[0112] The material of the dielectric layer 600 can be any material suitable for bonding and peeling the carrier 700 relative to the upper layer or any wafer disposed thereon. In some embodiments, the dielectric layer 600 includes a blanket layer composed of a dielectric material, and the dielectric material includes nitrides (such as silicon nitride, etc.), oxides (such as silicon oxide, etc.), oxynitrides (such as silicon oxynitride, etc.). As an alternative, the dielectric layer 600 can include a dielectric material layer made of a dielectric material, and the dielectric material includes any suitable polymer-based dielectric material (such as BCB, PBO, or the like). As an alternative, the dielectric layer 600 can include a dielectric material layer made of an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating film. As an alternative, the dielectric layer 600 can include a dielectric material layer made of a UV glue that loses its adhesive properties when exposed to ultraviolet (UV) light. In some embodiments, the dielectric layer 600 can be dispensed as a liquid and cured on the carrier 700, can be a laminate film laminated onto the carrier 700, or can be formed on the carrier 700 by any suitable method. The surface of the dielectric layer 600 (which faces the carrier 700) is planar and has high coplanarity.

[0113] See Figure 13 , in some embodiments, a fourth planarization process is performed on the wafer W3 to thin the substrate 301 to form a substrate 301', and the substrate 301' exposes the perforation 311 in an accessible manner and laterally covers the pad 310 covering the perforation 311, wherein a dielectric layer 312 is formed above the substrate 301' and laterally covers the perforation 311 and the pad 310 protruding from the surface S301' of the substrate 301'. The formation and material of the dielectric layer 312 are similar or substantially the same as those of the dielectric layer 112 discussed previously in Figure 5 , and the details of the substrate 301', the dielectric layer 312, the perforation 311, and the pad 310 (such as the positioning structure or the like) are similar or substantially the same as the details of the substrate 101', the dielectric layer 112, the perforation 111, and the pad 110 discussed previously in Figure 5 , so for the sake of brevity, they are not repeated herein.

[0114] In some embodiments, after forming the dielectric layer 312, a dielectric layer 313 and a plurality of connection structures 314 are formed on the dielectric layer 312, and at least some of the connection structures 314 are electrically coupled to the perforation 311, as Figure 13As shown. For example, the connection structure 314 is electrically coupled to the stacked unit 50 through the vias 311, the internal wiring 307, and the connection structure 318. In other words, the semiconductor die 300 (e.g., formed in the corresponding device region DR3) is electrically coupled and electrically connected to the semiconductor dies 100 and 200 in the corresponding stacked unit 50 disposed thereon. In such a case, the semiconductor die 300 (e.g., formed in a corresponding one of the device regions DR3) is electrically independent (e.g., electrically isolated) from the semiconductor dies 100 and 200 in the stacked unit 50 disposed on the remaining semiconductor dies 300 (e.g., formed in the remaining device regions DR3). Details, formation, and materials of the dielectric layer 313 and the connection structure 314 are similar or substantially the same as those of the dielectric layer 313 and the connection structure 314 previously discussed in Figure 6 and thus, for the sake of brevity, will not be repeated herein.

[0115] Continuing Figure 13 , after the formation of the dielectric layer 313 and the connection structure 314, the dielectric layer 915, the dielectric layer 916, and the plurality of conductive terminals 917 are successively formed on the dielectric layer 313 and the connection structure 314, wherein the conductive terminals 917 are disposed on the connection structure 314 and electrically coupled to the connection structure 314. As Figure 13 shown, the dielectric layer 915 may be formed on the dielectric layer 313 and the connection structure 314, and a plurality of first openings (not labeled) are formed in the dielectric layer 915 and penetrate through the dielectric layer 915, the first openings exposing the connection structure 314 in an accessible manner. The dielectric layer 915 may be referred to as a passivation layer. In such a case, the dielectric layer 916 is formed on the dielectric layer 915, and a plurality of second openings (not labeled) are formed in the dielectric layer 916 and penetrate through the dielectric layer 916, the second openings exposing some of the connection structure 314 that is exposed in an accessible manner through the dielectric layer 915. The dielectric layer 916 may be referred to as a post - passivation layer. In some embodiments, the dielectric layer 915 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials, and may be formed by deposition such as CVD (e.g., PECVD). The present disclosure is not limited thereto. For example, in some embodiments, the dielectric layer 916 may be a PI layer, a PBO layer, or a dielectric layer formed of other suitable polymers, and may be formed by spin coating or deposition.

[0116] In some embodiments, each of the conductive terminals 917 may include an under bump metallurgy (UBM) pattern 917u and a conductive device 917c disposed thereon and electrically coupled thereto. As Figure 13As shown, for example, the conductive element 917c of the conductive terminal 917 is electrically coupled to the connection structure 314 through the UBM pattern 917u of the conductive terminal 917. In this case, the conductive terminal 917 passes through the dielectric layer 915 and the dielectric layer 916 to be electrically coupled to the connection structure 314.

[0117] Each of the UBM patterns 917u includes, for example, a metal layer, wherein the metal layer may include a single layer or a composite layer including a plurality of sub-layers formed of different materials. In some embodiments, the material in the UBM pattern 917u includes, for example, copper, nickel, titanium, molybdenum, tungsten, titanium nitride, titanium tungsten, alloys thereof, or the like, and may be formed by an electroplating process. Each of the UBM patterns 917u may include a titanium layer and a copper layer on the titanium layer. In some embodiments, the UBM pattern 917u is formed, for example, by sputtering, PVD, or the like. The present disclosure does not limit the shape and number of the UBM patterns 917u. For example, the conductive device 917c includes a microbump, a metal column, a controlled collapse chip connection (C4) bump (e.g., which may have a size of, but not limited to, about 80 microns), a ball grid array (BGA) bump or ball (e.g., which may have a size of, but not limited to, about 400 microns), a solder ball, a bump formed by electroless nickel-immersion gold technology (ENIG), a bump formed by electroless nickel-palladium immersion gold (ENEPIG), or the like. The present disclosure is not limited thereto. The present disclosure does not limit the shape and number of the conductive element 917c.

[0118] Continue Figure 13 In some embodiments, after forming the conductive terminals 917, a singulation process is performed to cut through the dielectric layer 915, the dielectric layer 916, the wafer W3, the insulating encapsulation 800, the dielectric layer 500, the dielectric layer 600, and the carrier 700 to form a plurality of semiconductor devices 1000 each including a plurality of stacked structures 10. At this point, the semiconductor device 1000 has been manufactured. Figure 13 In the figure, for illustration purposes and simplicity, only one semiconductor device 1000 is shown. In a non-limiting example, Figure 13As shown in semiconductor device 1000, each stacked structure 10 includes semiconductor die 300, semiconductor die 200, semiconductor die 100 interposed between and electrically coupled to semiconductor die 300 and semiconductor die 200, insulating encapsulant 800 laterally covering semiconductor die 100 and 200 and covering semiconductor die 300 exposed by semiconductor die 100 and 200, carrier 700 disposed on semiconductor die 200, dielectric layer 500 disposed between carrier 700 and semiconductor die 200 and between carrier 700 and insulating encapsulant 800, dielectric layer 600 disposed between carrier 700 and dielectric layer 500, conductive terminal 917 disposed on and electrically coupled to semiconductor die 300, dielectric layer 915 disposed between semiconductor die 300 and conductive terminal 917, and dielectric layer 916 disposed between dielectric layer 915 and conductive terminal 917. In some embodiments, for each stacked structure 10 included in semiconductor device 1000, conductive terminal 917 is electrically coupled to semiconductor die 300 through connection structure 314, some of conductive terminal 917 are electrically coupled to semiconductor die 100 through connection structure 314, via 311, inner connection 307, some of connection structure 318, and connection structure 114, and some of conductive terminal 917 are electrically coupled to semiconductor die 200 through connection structure 314, via 311, inner connection 307, some of connection structure 318, connection structure 114, via 111, inner connection 107, connection structure 108, and connection structure 208. In some embodiments, the stacked structures 10 included in a single semiconductor device 1000 are electrically independent of each other (e.g., electrically isolated).

[0119] In some embodiments, semiconductor die 100 included in each stacked structure 10 of semiconductor device 1000 includes substrate 101’, device layer 102, inner connection 107, connection structure 108, dielectric layer 109, pad 110, via 111, dielectric layer 112, dielectric layer 113, and connection structure 114. In some embodiments, semiconductor die 200 included in each stacked structure 10 of semiconductor device 1000 includes substrate 201, device layer 202, inner connection 207, connection structure 208, and dielectric layer 209. In some embodiments, semiconductor die 300 included in each stacked structure 10 of semiconductor device 1000 includes substrate 301’, device layer 302, inner connection 307, connection structure 318, dielectric layer 319, pad 310, via 311, dielectric layer 312, dielectric layer 313, and connection structure 314.

[0120] In some embodiments, Figure 14 semiconductor device 1000A and Figure 13Similar to the semiconductor device 1000, except that the carrier 700 and the dielectric layer 600 are removed, exposing the shown top surface S500 of the dielectric layer 500. In some embodiments, Figure 15 The semiconductor device 1000B is similar to Figure 13 The semiconductor device 1000, except that the carrier 700, the dielectric layer 600, and the dielectric layer 500 are removed, exposing the shown top surface S800 of the insulating encapsulant 800 and the surface S201 of the semiconductor die 200.

[0121] In some embodiments, in the stacked structure 10 of the semiconductor device 1000, in the XY plane (e.g., top view (or plan view)), the size of the semiconductor die 100 and the size of the semiconductor die 200 are the same as each other and smaller than the size of the semiconductor die 300 that overlaps them. In other embodiments, in the stacked structure 10 of the semiconductor device 1000, in the XY plane (e.g., top view (or plan view)), the size of the semiconductor die 100 and the size of the semiconductor die 200 are the same as each other and larger than the size of the semiconductor die 300 that overlaps them. In yet other embodiments, in the stacked structure 10 of the semiconductor device 1000, in the XY plane (e.g., top view (or plan view)), the size of the semiconductor die 100 and the size of the semiconductor die 200 are the same as each other and are substantially equal to the size of the semiconductor die 300 that overlaps them.

[0122] On the other hand, in the semiconductor device 1000, in the XY plane (e.g., top view (or plan view)), the sizes of the semiconductor dies 100 included in each of the stack structures 10 are substantially the same as each other. In other embodiments, in the XY plane (e.g., top view (or plan view)), the size of the semiconductor die 100 included in one of the stack structures 10 is substantially the same as the sizes of the semiconductor dies 100 included in some of the stack structures 10, and is different from the sizes of the semiconductor dies 100 included in the remaining stack structures 10. In still other embodiments, in the XY plane (e.g., top view (or plan view)), the sizes of the semiconductor dies 100 included in each of the stack structures 10 are different from each other. In a non-limiting example, for instance, in the semiconductor device 1000, in the XY plane (e.g., top view (or plan view)), the sizes of the semiconductor dies 200 included in each of the stack structures 10 are substantially the same as each other. In other embodiments, in the XY plane (e.g., top view (or plan view)), the size of the semiconductor die 200 included in one of the stack structures 10 is substantially the same as the sizes of the semiconductor dies 200 included in some of the stack structures 10, and is different from the sizes of the semiconductor dies 200 included in the remaining stack structures 10. In still other embodiments, in the XY plane (e.g., top view (or plan view)), the sizes of the semiconductor dies 200 included in each of the stack structures 10 are different from each other. In a non-limiting example, for instance, in the semiconductor device 1000, in the XY plane (e.g., top view (or plan view)), the sizes of the semiconductor dies 300 included in each of the stack structures 10 are substantially the same as each other. In other embodiments, in the XY plane (e.g., top view (or plan view)), the size of the semiconductor die 300 included in one of the stack structures 10 is substantially the same as the sizes of the semiconductor dies 300 included in some of the stack structures 10, and is different from the sizes of the semiconductor dies 300 included in the remaining stack structures 10. In still other embodiments, in the XY plane (e.g., top view (or plan view)), the sizes of the semiconductor dies 300 included in each of the stack structures 10 are different from each other.

[0123] Figures 16 to 18 are schematic cross-sectional views or schematic plan views of various stages in a method of manufacturing a semiconductor device 2000 according to some embodiments of the present disclosure. Devices similar to or having substantially the same reference numbers as the above-described devices, as well as certain details or descriptions of the same devices (e.g., formation and materials) and their relationships (e.g., relative positioning architectures and electrical connections) are not repeated herein.

[0124] See Figure 16 , in some embodiments, in Figure 5After the process described in, a dielectric layer 115 and a plurality of connection structures 116 are formed on the perforation 111 and the dielectric layer 112. In some embodiments, the pitch P20 between two adjacent connection structures 116 is less than 1 μm and greater than 0 μm. The pitch P20 can be greater than 0 μm and can be less than or substantially equal to 0.95 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.90 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.85 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.80 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.75 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.70 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.65 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.60 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.55 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.50 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.45 μm, can be greater than 0 μm and can be less than or substantially equal to 0.40 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.35 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.30 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.25 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.20 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.15 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.10 μm or less, etc. The pitch P20 can be less than, greater than, or substantially equal to the pitches P1 and P2, and the present disclosure is not limited thereto. In some embodiments, the pitch P20 is less than the pitches P3 and P10. The details, formation, and materials of the dielectric layer 115 and the connection structures 116 (including the line portion 116t and the via portion 116v) are similar or substantially the same as the details, formation, and materials of the dielectric layer 109 and the connection structures 108 (including 108t and 108v) discussed previously in Figure 1 , and thus are not repeated herein for the sake of brevity. It should be understood that Figure 16 each device region DR1 of the wafer W1' shown in is or includes a semiconductor die (or chip) 100'. The size, shape, and type of the semiconductor die 100' are similar or substantially the same as the size, shape, and type of the semiconductor die 100 discussed previously in Figure 1 , and thus are not repeated herein.

[0125] See Figure 17, in some embodiments, a wafer W3' is provided. Wafer W3' is similar to wafer W3, except that dielectric layer 309 and a plurality of via connection structures 308 replace dielectric layer 319 and connection structure 318. In some embodiments, the pitch P4 between two adjacent connection structures 308 is less than 1 μm and greater than 0 μm. Pitch P4 can be greater than 0 μm and can be less than or substantially equal to 0.95 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.90 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.85 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.80 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.75 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.70 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.65 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.60 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.55 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.50 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.45 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.40 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.35 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.30 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.25 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.20 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.15 μm or less, can be greater than 0 μm and can be less than or substantially equal to 0.10 μm or less, etc. Pitch P4 can be less than, greater than, or substantially equal to pitches P1, P2, and P20, and the present disclosure is not limited thereto. In some embodiments, pitch P4 is less than pitches P3 and P10. The details, formation, and materials of dielectric layer 309 and connection structures 308 (including line portion 308t and via portion 308v) are similar or substantially the same as the details, formation, and materials of dielectric layer 109 and connection structures 108 (including 108t and 108v) as previously discussed in Figure 1 and are thus not repeated herein for the sake of brevity. It should be understood that Figure 17 each device region DR3 in the wafer W3' depicted in Figure 7 is or includes a semiconductor die (or chip) 300'. The size, shape, and type of semiconductor die 300' are similar or substantially the same as the size, shape, and type of conductor die 300 previously discussed in Figure 7 and are thus not repeated here.

[0126] In some embodiments, the structure depicted in Figure 16 is placed on wafer W3' and bonded to wafer W3' through a bonding process, as in Figure 17As shown. The bonding process is referred to as the WoW bonding process. For example, Figure 16 In the structure shown, the wafer W1' is bonded to the wafer W3' through a bonding process, which includes metal-to-metal bonding and dielectric-to-dielectric bonding. For example, the wafer W1' is disposed on the wafer W3' (e.g., physical contact) and electrically connected to the wafer W3'. In some embodiments, as Figure 17 shown, the connection structure 116 of the wafer W1' and the connection structure 308 of the wafer W3' support each other and are bonded together through direct metal-to-metal bonding (e.g., "copper" to "copper") bonding), for example. Additionally, as Figure 17 shown, the dielectric layer 115 of the wafer W1' abuts against the dielectric layer 309 of the wafer W3' and is bonded together through direct dielectric-to-dielectric bonding (e.g., "oxide" to "oxide" bonding, "nitride" to "oxide" bonding, or "nitride" to "nitride") bonding), for example. In such an embodiment, the bonding interface IF4 including the metal-to-metal bonding interface (e.g., "copper" to "copper" bonding) and the dielectric-to-dielectric bonding interface (e.g., "oxide" to "oxide" bonding interface, "nitride" to "oxide" bonding interface, or "nitride" to "nitride" bonding interface) coexisting between the wafer W1' and the wafer W3' is considered as the bonding interface between the wafer W1' and the wafer W3'.

[0127] It should be noted that the above bonding methods are only examples and are not intended to be limiting. There may be an offset (bias) between the sidewalls of the connection structure 116 and the sidewalls of the connection structure 308 respectively located below it. Since one of the connection structure 116 and the connection structure 308 may have a larger bonding surface than the other, direct metal-to-metal bonding can still be achieved even in the case of misalignment, and the reliability of the electrical connection between the wafer W1' and the wafer W3' can still be ensured. In this way, for some embodiments, the dielectric layer 115 directly adjacent to the connection structure 116 is bonded to a part of each of the connection structures 308 (e.g., dielectric-to-metal bonding), or the dielectric layer 309 directly adjacent to the connection structure 308 is bonded to a part of each of the connection structures 116 (e.g., dielectric-to-metal bonding). Due to the presence of the connection structure 116 (having a pitch P20) and the connection structure 308 (having a pitch P4), the overall wiring density of the semiconductor device 2000 is greatly improved, thereby obtaining higher performance and reducing the manufacturing cost.

[0128] See Figure 18 , in some embodiments, the process described in Figure 17 is performed on the structure of Figure 13 to form a plurality of semiconductor devices 2000. In Figure 18For illustrative purposes and simplicity, only one semiconductor device 2000 is shown. In a non-limiting example, as shown in the semiconductor device 2000 of Figure 18 each stacked structure 10 includes a semiconductor die 300', a semiconductor die 200, a semiconductor die 100' interposed between and electrically coupled to the semiconductor die 300' and the semiconductor die 200, an insulating encapsulant 800 that laterally covers the semiconductor die 100' and 200 and covers the semiconductor die 300' exposed by the semiconductor die 100' and 200, a conductive terminal 917 disposed on the semiconductor die 300' and electrically coupled to the semiconductor die 300', a dielectric layer 915 disposed between the semiconductor die 300' and the conductive terminal 917, and a dielectric layer 916 disposed between the dielectric layer 915 and the conductive terminal 917. In some embodiments, for each stacked structure 10 included in the semiconductor device 2000, the conductive terminal 917 is electrically coupled to the semiconductor die 300' through a connection structure 314, some of the conductive terminals 917 are electrically coupled to the semiconductor die 100' through the connection structure 314, vias 311, internal connections 307, some of the connection structures 308, and the connection structure 116, and some of the conductive terminals 917 are electrically coupled to the semiconductor die 200 through the connection structure 314, vias 311, internal connections 307, some of the connection structures 308, the connection structure 116, vias 111, internal connections 107, the connection structure 108, and the connection structure 208. In some embodiments, the stacked structures 10 included in a single semiconductor device 2000 are electrically independent of each other (e.g., electrically isolated).

[0129] In some embodiments, the semiconductor die 100' included in each stacked structure 10 of the semiconductor device 2000 includes a substrate 101', a device layer 102, internal connections 107, a connection structure 108, a dielectric layer 109, a pad 110, vias 111, a dielectric layer 112, a dielectric layer 115, and a connection structure 116. In some embodiments, the semiconductor die 200 included in each stacked structure 10 of the semiconductor device 2000 includes a substrate 201, a device layer 202, internal connections 207, a connection structure 208, and a dielectric layer 209. In some embodiments, the semiconductor die 300' included in each stacked structure 10 of the semiconductor device 2000 includes a substrate 301', a device layer 302, internal connections 307, a connection structure 308, a dielectric layer 309, a pad 310, vias 311, a dielectric layer 312, a dielectric layer 313, and a connection structure 314. In some embodiments, in the stacked structure 10 of the semiconductor device 2000, in the XY plane (e.g., top view (or plan view)), the size of the semiconductor die 100 and the size of the semiconductor die 200 are substantially the same as each other and are substantially the same as the size of the semiconductor die 300 that overlaps with them.

[0130] Figures 19 to 24 are schematic cross-sectional views or schematic plan views of various stages in the method of manufacturing a semiconductor device 3000 according to some embodiments of the present disclosure. Devices similar to the above-described devices or substantially the same reference numbers, as well as certain details or descriptions of the same devices (e.g., formation and materials) and their relationships (e.g., relative positioning architectures and electrical connections) are not repeated here. Refer to Figure 19 , in some embodiments, after Figure 5 the process described above, Figure 5 the structure is flipped (upside down).

[0131] Refer to Figure 20 , in some embodiments, one or more semiconductor dies 300 are picked up and placed on a wafer W1. Details of the semiconductor die 300 have been described in Figure 7 , and thus are not repeated here for the sake of brevity. In some embodiments, the semiconductor dies 300 (in chip form) are arranged on a stacked unit 50 (in wafer form) respectively, as shown in Figure 20 . For illustrative purposes and simplicity, only two semiconductor dies 300 are shown in Figure 20 , however, the present disclosure is not limited thereto. The number of semiconductor dies 300 can exceed two. The number of semiconductor dies 300 can be selected and designed based on requirements and design layouts. The number of semiconductor dies 300 corresponds to the number of stacked units 50. In a non-limiting example, in the Z direction, the semiconductor dies 300 overlap the stacked units 50 (in wafer form) in a one-to-one architecture manner, as shown in Figure 20 . In another non-limiting example, the semiconductor dies 300 overlap the stacked units 50 (in wafer form) in a multi-to-one architecture (e.g., two-to-one architecture, three-to-one architecture, four-to-one architecture, five-to-one architecture or the like) manner in the Z direction.

[0132] After placing the semiconductor die 300 (in chip form), a bonding process is performed to bond the semiconductor chip 300 to a corresponding one of the stacked units 50 (in wafer form) overlapping therewith along the Z direction, in some embodiments. For example, the semiconductor die 300 is bonded to the wafer W1 through a bonding process, and the bonding process includes metal-to-metal bonding and dielectric-to-dielectric bonding. For example, the semiconductor die 300 is disposed on the wafer W1 (e.g., physical contact) and electrically connected to the wafer W1. In some embodiments, as shown in Figure 20 , the connection structure 114 of the semiconductor die 100 of the wafer W1 and the connection structure 318 (e.g., 318t) of the semiconductor die 300 support each other and are bonded together through a direct metal-to-metal bonding (e.g., "copper" to "copper" bonding), for example. Additionally, as shown in Figure 20As shown, the dielectric layer 113 of the semiconductor die 100 of the wafer W1 abuts against the dielectric layer 319 of the semiconductor die 300 and is joined together by a direct dielectric-to-dielectric bond (e.g., "oxide" to "oxide" bond, "nitride" to "oxide" bond, or "nitride" to "nitride" bond), for example. In such an embodiment, the bonding interface IF5 including a metal-to-metal bonding interface (e.g., "copper" to "copper" bond) and a dielectric-to-dielectric bonding interface (e.g., "oxide" to "oxide" bond, "nitride" to "oxide" bond, or "nitride" to "nitride" bond) coexisting between the wafer W1 and the semiconductor die 300 is considered the bonding interface between the wafer W1 and the semiconductor die 300.

[0133] It should be noted that the above bonding methods are only examples and are not intended to be limiting. There may be an offset (bias) between the sidewalls of the connection structure 114 and the sidewalls of the connection structures 318 respectively located below it. Since one of the connection structures 114 and 318 may have a larger bonding surface than the other, a direct metal-to-metal bond can still be achieved even in the case of misalignment, and the reliability of the electrical connection between the wafer W1 and the semiconductor die 300 can still be ensured. In this way, for some embodiments, the dielectric layer 113 directly adjacent to the connection structure 114 is bonded to a part of each of the connection structures 318 (e.g., dielectric-to-metal bond), or the dielectric layer 319 directly adjacent to the connection structure 318 is bonded to a part of each of the connection structures 114 (e.g., dielectric-to-metal bond). In an embodiment where the semiconductor die 300 overlaps the stacking unit 50 (in the form of a wafer) in a one-to-one architecture, the single-form semiconductor dies 300 covering a single semiconductor die 100 in the wafer W1 are electrically independent of each other (e.g., electrically isolated). In an embodiment where the semiconductor die 300 overlaps the stacking unit 50 (in the form of a wafer) in a multi-to-one architecture, the single-form semiconductor dies 300 covering a corresponding one of the conductor dies 100 in the wafer W1 are electrically independent of the single-form semiconductor dies 300 covering the remaining semiconductor dies 100 in the wafer W1 (e.g., electrically isolated). In some embodiments, the semiconductor die 300 is bonded to the wafer W1 by CoW bonding.

[0134] See Figure 21 , in some embodiments, an insulating encapsulant 800m is conformally formed on the semiconductor die 300 and above the wafer W1, where the semiconductor die 300 and the wafer W1 exposed through the semiconductor die 300 are completely covered by the insulating encapsulant 800m. The formation and material of the insulating encapsulant 800m have been previously described in Figure 10 and will not be repeated here.

[0135] See Figure 22 , in some embodiments, a planarization process is performed on the insulating encapsulant 800m to form an insulating encapsulant 800 that exposes the semiconductor die 300 (e.g., the substrate 301, the vias 311, and the pads 310). The details of the planarization process are similar to or substantially the same as the planarization process discussed in Figure 5 and / or Figure 13 the patterning process discussed in, and thus will not be repeated here. For example, the shown top surface S800 of the insulating encapsulant 800 is substantially flush with the surface S301 of the substrate 301, the surface S311 of the via 311, and the surface S310 of the pad 310. In other words, the shown top surface S800 of the insulating encapsulant 800 is substantially coplanar with the surface S301 of the substrate 301, the surface S311 of the via 311, and the surface S310 of the pad 310.

[0136] See Figure 23 , in some embodiments, the substrate 301 is patterned to further locally remove the substrate 301' to form a substrate 301' having a patterned bottom surface S301', such that a portion of each via 311 and a portion of each pad 310 protrude from the patterned bottom surface S301' of the substrate 301'. The details of the patterning process are similar to or substantially the same as the patterning process discussed in Figure 5 and / or Figure 13 the patterning process discussed in, and thus will not be repeated here. As shown in Figure 23 , the pad 310 may cover the entire sidewall of the via 311; however, the present disclosure is not limited thereto. In one embodiment, the pad 310 may only cover the sidewall of the via 311 that is embedded in the substrate 301'. That is, after the planarization process, for example, the pad 310 disposed on the sidewall of the portion of the via 311 that protrudes from the patterned bottom surface S301' of the substrate 301' is removed during the patterning process. After the via 311 protrudes out of the substrate 301', a dielectric layer 112 is formed on the substrate 301' that laterally covers the via 311. The formation and material of the dielectric layer 312 are similar to or substantially the same as the formation and material of the dielectric layer 112 described previously in Figure 5 and / or similar to or the same as the formation and material of the dielectric layer 312 described previously in Figure 13 , and thus will not be repeated here. For example, as shown in Figure 23 , the surface S312 of the dielectric layer 312 is substantially flush with the bottom surface S311 of the via 311 and the bottom surface S310 of the pad 310. That is, the surface S312 of the dielectric layer 312 is substantially coplanar with the bottom surface S311 of the via 311 and the bottom surface S310 of the pad 310.

[0137] SeeFigure 24 , in some embodiments, a dielectric layer 313, a plurality of connection structures 314, a dielectric layer 915, a dielectric layer 916, and a plurality of conductive terminals 917 are successively formed over a semiconductor die 300 and an insulating encapsulant 800 that laterally covers the semiconductor die 300, and a dicing (or singulation) process is performed to form a plurality of semiconductor devices 3000. The formation and materials of the dielectric layer 313, the connection structures 314, the dielectric layer 915, the dielectric layer 916, and the conductive terminals 917 have been discussed in Figure 13 and will not be repeated here.

[0138] In Figure 24 , for illustrative purposes and simplicity, only one semiconductor device 3000 is shown. In a non-limiting example, as shown in the semiconductor device 3000 of Figure 24 , each stacked structure 10 includes a semiconductor die 300, a semiconductor die 200, a semiconductor die 100 interposed between and electrically coupled to the semiconductor dies 300 and 200, an insulating encapsulant 800 that laterally covers the semiconductor die 300 and covers the semiconductor die 100 exposed by the semiconductor die 300, a conductive terminal 917 disposed on and electrically coupled to the semiconductor die 300, a dielectric layer 915 disposed between the semiconductor die 300 and the conductive terminal 917, and a dielectric layer 916 disposed between the dielectric layer 915 and the conductive terminal 917. In some embodiments, for each stacked structure 10 included in the semiconductor device 3000, the conductive terminal 917 is electrically coupled to the semiconductor die 300 through the connection structure 314, some of the conductive terminals 917 are electrically coupled to the semiconductor die 100 through the connection structure 314, vias 311, internal wiring 307, some of the connection structures 318, and the connection structure 114, and some of the conductive terminals 917 are electrically coupled to the semiconductor die 200 through the connection structure 314, vias 311, internal wiring 307, some of the connection structures 318, the connection structure 114, vias 111, internal wiring 107, the connection structure 108, and the connection structure 208. In some embodiments, the stacked structures 10 included in a single semiconductor device 3000 are electrically independent of each other (e.g., electrically isolated).

[0139] In some embodiments, the semiconductor die 100 included in each of the stacked structures 10 of the semiconductor device 3000 includes a substrate 101', a device layer 102, interconnects 107, a connection structure 108, a dielectric layer 109, a pad 110, vias 111, a dielectric layer 112, a dielectric layer 113, and a connection structure 114. In some embodiments, the semiconductor die 200 included in each of the stacked structures 10 of the semiconductor device 3000 includes a substrate 201, a device layer 202, interconnects 207, a connection structure 208, and a dielectric layer 209. In some embodiments, the semiconductor die 300 included in each of the stacked structures 10 of the semiconductor device 3000 includes a substrate 301', a device layer 302, interconnects 307, a connection structure 318, a dielectric layer 319, a pad 310, vias 311, a dielectric layer 312, a dielectric layer 313, and a connection structure 314.

[0140] In some embodiments, in the stacked structure 10 of the semiconductor device 3000, in the XY plane (e.g., top view (or plan view)), the size of the semiconductor die 100 and the size of the semiconductor die 200 are the same as each other and greater than the size of the semiconductor die 300 that overlaps with them. In other embodiments, in the stacked structure 10 of the semiconductor device 3000, in the XY plane (e.g., top view (or plan view)), the size of the semiconductor die 100 and the size of the semiconductor die 200 are the same as each other and less than the size of the semiconductor die 300 that overlaps with them. In still other embodiments, in the stacked structure 10 of the semiconductor device 3000, in the XY plane (e.g., top view (or plan view)), the size of the semiconductor die 100 and the size of the semiconductor die 200 are the same as each other, and are substantially equal to the size of the semiconductor die 300 that overlaps with them.

[0141] In an embodiment of the semiconductor device 1000, the stacked structures 10 included therein are electrically isolated from each other. However, the present disclosure is not limited thereto. Figure 25 is a schematic cross-sectional view of a semiconductor device 4000 according to some embodiments of the present disclosure. Figure 26 is a schematic cross-sectional view of a semiconductor device 4000A according to other embodiments of the present disclosure. Figure 27 is a schematic cross-sectional view of a semiconductor device 4000B according to other embodiments of the present disclosure. Devices or substantially the same reference numbers as the above-described devices, and certain details or descriptions of the same devices (e.g., formation and materials) and their relationships (e.g., relative positioning architecture and electrical connection) are not described herein again.

[0142] In some embodiments, Figure 25 the semiconductor device 4000 of Figure 13Similar to the semiconductor device 1000, except that the semiconductor device 4000 includes a redistribution line structure 907, where the redistribution line structure 907 is disposed between the vias 311 and the conductive terminals 917 and electrically coupled to the vias 311 and the conductive terminals 917, such that the stacked structures 10 included in the semiconductor device 4000 are electrically coupled to each other through the redistribution line structure 907. As Figure 25 shown, the redistribution line structure 907 may be formed after the dielectric layer 312 and before the formation of the dielectric layer 915. In some embodiments, the redistribution line structure 907 is disposed over the vias 311, the dielectric layer 312, and the insulation encapsulation 800, and the redistribution line structure 907 is electrically coupled to the vias 311 of the semiconductor die 300. That is, the redistribution line structure 907 provides a wiring function for the semiconductor die 300. In some embodiments, at least some of the semiconductor dies 300 in the semiconductor device 4000 are electrically connected to each other through the redistribution line structure 907. As Figure 25 shown, the redistribution line structure 907 may be stacked over the semiconductor die 300 and the insulation encapsulation 800, and includes a plurality of build-up layers electrically connected to each other. As Figure 25 shown, the redistribution line structure 907 includes more than one dielectric layer 903 (e.g., 9031, 9032, 9033) and more than one patterned conductive layer 906 (e.g., 9061, 9062, 9063). In some embodiments, each patterned conductive layer 906 (e.g., 9061, 9062, and 9063) includes a line portion 905 (e.g., 9051, 9052, and 9053) extending along a horizontal direction (e.g., direction X or direction Y), a via portion 904 (e.g., 9041, 9042, and 9043) extending along a vertical direction (e.g., direction Z), and / or a combination thereof. The patterned conductive layer 906 may be referred to as a metallization layer or a redistribution layer of the redistribution line structure 907 to provide a wiring function, and may be collectively referred to as the wiring structure of the redistribution line structure 907. The dielectric layer 903 may be collectively referred to as the dielectric structure of the redistribution line structure 907 to provide protection for the metallization layer, the redistribution layer, or the wiring structure of the redistribution line structure 907. In some embodiments, in the redistribution line structure 907, the dielectric layer (e.g., 903) and the patterned conductive layer (e.g., 906) are alternately arranged. One dielectric layer and a corresponding one metallization layer together may be considered as one build-up layer of the redistribution line structure 907 (e.g., 9031 and 9061; 9032 and 9062; 9033 and 9063; or similar layers). As Figure 25As shown, for example, the bottom layer of the patterned conductive layer 906 (e.g., 9063) can be exposed in an accessible manner through the bottom layer of the dielectric layer 903 (e.g., 9033) for external connection (e.g., through the conductive terminal 917). In the present disclosure, the number of layers of the dielectric layer 903 and the patterned conductive layer 906 is not limited to Figure 25 as shown, which can be selected and specified according to the design layout and requirements. That is, the number of layers of the dielectric layer (e.g., 903) and the patterned conductive layer (e.g., 906) can independently be 1 or greater than 1. In some embodiments, the line dimensions (e.g., thickness and width) of the patterned conductive layer 906 gradually increase along the direction from the semiconductor die 300 to the conductive terminal 917. In some embodiments, the conductive terminal 917 is electrically coupled to the semiconductor die 300 through the redistribution line structure 907.

[0143] In addition, the redistribution line structure 907 may further include one or more seed layers (not shown) to facilitate the formation of the patterned conductive layer 906, where the seed layer may be between the patterned conductive layer 906 and the dielectric layer 903. In embodiments including a seed layer, one patterned conductive layer 906 and a corresponding seed layer (not shown) may be collectively referred to as the metallization layer or redistribution layer of the redistribution line structure 907 to provide a wiring function. That is, for such embodiments, the patterned conductive layer 906 and the corresponding seed layer (not shown) may be collectively referred to as the wiring structure of the redistribution line structure 907. The formation and materials of the dielectric layer 903, the patterned conductive layer 906, and the optional seed layer are similar or substantially the same as those of the dielectric layer 103, the patterned conductive layer 106, and the optional seed layer previously discussed in Figure 1 so the details will not be repeated here. Due to the redistribution line structure 907, a horizontal electrical connection is established between the stacked structures 10 of the semiconductor device 4000.

[0144] Similarly, the redistribution line structure 907 can be adopted by the semiconductor device 1000A of Figure 14 (see the semiconductor device 4000A of Figure 26 ), the semiconductor device 1000B of Figure 15 (see the semiconductor device 4000B of Figure 27 ), the semiconductor device 2000 of Figure 18 and the semiconductor device 3000 of Figure 24 . The present disclosure is not limited thereto.

[0145] Figures 28 to 30 are schematic cross-sectional views or schematic plan views of various stages in the manufacturing method of a semiconductor device 5000 according to some embodiments of the present disclosure.Figures 31 to 33 FIG. 1 is a schematic plan view of various architectures of semiconductor devices in accordance with some embodiments of the present disclosure. Devices similar to or substantially the same as the above-described devices, as well as certain details or descriptions of the same devices (e.g., formation and materials) and their relationships (e.g., relative positioning architectures and electrical connections) are not repeated herein.

[0146] See Figure 28 , in some embodiments, a carrier 700 coated with a release layer 900 is provided. Details of the carrier 700 have been described in Figure 12 and are not repeated herein. The material of the release layer 900 can be any material suitable for bonding and releasing the carrier 700 relative to an overlying layer or any wafer disposed thereon. In some embodiments, the release layer 900 can include a dielectric material layer made of a dielectric material, which includes any suitable polymeric dielectric material (e.g., BCB, PBO, or the like). As a non-limiting example, the release layer 900 can include a dielectric material layer made of an epoxy-based thermal release material such as an LTHC release coating film that loses its adhesive properties when heated. For another non-limiting example, the release layer 900 can include a dielectric material layer made of a UV glue that loses its adhesive properties when exposed to UV light. The release layer 900 can be dispensed as a liquid and cured on the carrier 700, can be a laminate film laminated onto the carrier 700, or can be formed on the carrier 700 by any suitable method. For example, as Figure 28 shown, the shown top surface of the release layer 900 (which is opposite to the shown bottom surface in contact with the carrier 700) is planar and has high coplanarity. In certain embodiments, the release layer 900 is an LTHC release layer with good chemical resistance, and such a layer can be peeled from the carrier 700 at room temperature by applying laser irradiation, however, the present disclosure is not limited thereto.

[0147] In an alternative embodiment, a dielectric layer 500 is coated on the release layer 900, where the release layer 900 is sandwiched between the dielectric layer 500 and the carrier 700. As Figure 28 shown, the shown top surface of the dielectric layer 500 further provides a high degree of coplanarity. Details, formation, and materials of the dielectric layer 500 have been described in Figure 12 and are not repeated here.

[0148] In some embodiments, one or more stacked units 50 are picked up and placed on the dielectric layer 500 above the carrier 700, and an insulating encapsulant 800 is formed to laterally cover the stacked units 50 and the dielectric layer 500 exposed by the stacked units 50. For example, as Figure 28As shown, the connection structure 114 and the dielectric layer 113 are exposed in a touchable manner through the insulation encapsulant 800. Details of the stacking unit 50 have been described in Figures 1 to 7 and details of the insulation encapsulant 800 have been described in Figure 10 and Figure 11 and will not be repeated here.

[0149] Referring to Figure 29 , in some embodiments, one or more semiconductor dies 400 are picked up and placed on the stacking unit 50 laterally encapsulated in the insulation encapsulant 800 and above the carrier 700. Each semiconductor die 400 includes a substrate 401', a device layer 402 disposed on the substrate 401', and internal connections 407 (including a plurality of dielectric layers 403 (e.g., 4031, 4032,..., 403 N-2 , 403 N-1 and 403 N ) and a plurality of patterned conductive layers 406 (e.g., 4061, 4062,..., 406 N-2 , 406 N-1 and 406 N ) disposed on the device layer 402 and electrically coupled to the device layer 402. Each patterned conductive layer 406 includes a line portion 405 (e.g., 4051, 4052,..., 405 N-2 , 405 N-1 and 405 N ), and a via portion 404 (e.g., 4041, 4042,..., 404 N-2 , 404 N-1 and 404 N ) connected to the line portion 405 (e.g., 4051, 4052,..., 405 N-2 , 404 N-1 and 404 N), and / or combinations thereof), a dielectric layer 430 disposed on the inner connection 407, a plurality of connection structures 431 (including a line portion 431t and a via portion 431v) disposed on the inner connection 407 and electrically coupled thereto and penetrating the dielectric layer 430, a plurality of vias 411 embedded in the inner connection 407 and further extending from the inner connection 407 to a position within the substrate 401', a plurality of liners 410 lining the sidewalls and the shown bottom surface of the vias 411, a dielectric layer 412 disposed on the substrate 401' and laterally covering the vias 411 and the liners 410, a dielectric layer 413 disposed on the dielectric layer 412, the vias 411 and the liners 410, and a plurality of connection structures 414 penetrating the dielectric layer 413 and disposed on the vias 411 and electrically coupled thereto. The substrate 401', the device layer 402, the inner connection 407 (including 403 and 406 (such as 405 and 404)), the dielectric layer 430, the liner 410, the via 411, the dielectric layer 412, the dielectric layer 413 and the connection structure 414 in each semiconductor die 400 are similar to or substantially the same as the substrate 101', the device layer 102, the inner connection 107 (including 103 and 106 (such as, 105 and 104)), the dielectric layer 109, the liner 110, the via 111, the dielectric layer 112, the dielectric layer 113 and the connection structure 114 in each semiconductor die 100 as previously discussed in Figure 1 and thus will not be repeated here. In some embodiments, the connection structure 414 is an aluminum pad or other suitable metal pad and is formed, for example, by a deposition and patterning process. The patterning process may include a photolithography and etching process.

[0150] For illustrative purposes and simplicity, only two semiconductor dies 400 are shown in Figure 29 , however, the present disclosure is not limited thereto. The number of semiconductor dies 400 may exceed two. The number of semiconductor dies 400 may be selected and designed based on requirements and design layouts. The number of semiconductor dies 400 corresponds to the number of stacked units 50. In a non-limiting example, the semiconductor dies 400 and the stacked units 50 overlap in a one-to-one architecture manner in the Z direction, as shown in Figure 29 . In another non-limiting example, the semiconductor dies 400 and the stacked units 50 overlap in a multi-to-one architecture (such as, a two-to-one architecture, a three-to-one architecture, a four-to-one architecture, a five-to-one architecture) manner in the Z direction.

[0151] After placing the semiconductor die 400 (in chip form), a bonding process is performed to bond the semiconductor die 400 to a corresponding one of the stacked units 50 in chip form that overlaps it in the Z direction. For example, the semiconductor die 400 is bonded to the semiconductor die 100 by a bonding process that includes metal-to-metal bonding and dielectric-to-dielectric bonding. For example, the semiconductor die 400 is disposed on the semiconductor die 100 (e.g., physical contact) and electrically connected to the semiconductor die 100. In some embodiments, as Figure 29 shown, the connection structure 114 of the semiconductor die 100 and the connection structure 414 of the semiconductor die 400 support each other and are bonded together by direct metal-to-metal bonding (e.g., "copper" to "copper" bonding). Additionally, as Figure 29 shown, the dielectric layer 113 of the semiconductor die 100 and the dielectric layer 413 of the semiconductor die 400 are abutted against each other and bonded together by direct dielectric-to-dielectric bonding (e.g., "oxide" to "oxide" bonding, "nitride" to "oxide" bonding, or "nitride" to "nitride" bonding), for example. In such an embodiment, the bonding interface IF6 including the metal-to-metal bonding interface (e.g., "copper" to "copper" bonding) and the dielectric-to-dielectric bonding interface (e.g., "oxide" to "oxide" bonding, "nitride" to "oxide" bonding, or "nitride" to "nitride" bonding) coexisting between the semiconductor die 100 and the semiconductor die 400 is considered the bonding interface between the semiconductor die 100 and the semiconductor die 400.

[0152] It should be noted that the above bonding methods are only examples and are not intended to be limiting. There may be an offset (bias) between the sidewalls of the connection structure 414 and the sidewalls of the connection structure 114 respectively located below it. Since one of the connection structure 114 and the connection structure 414 may have a larger bonding surface than the other, direct metal-to-metal bonding can still be achieved even in the case of misalignment, and the reliability of the electrical connection between the semiconductor die 100 and the semiconductor die 400 can still be ensured. In this way, for some embodiments, the dielectric layer 113 directly adjacent to the connection structure 114 is bonded to a part of each of the connection structures 414 (e.g., dielectric-to-metal bonding), or the dielectric layer 413 directly adjacent to the connection structure 414 is bonded to a part of each of the connection structures 114 (e.g., dielectric-to-metal bonding). In an embodiment where the semiconductor die 400 overlaps the stacking unit 50 (in the form of a chip) in a one-to-one architecture, each semiconductor die 400 covering a single semiconductor die 100 is electrically independent (e.g., electrically isolated) from each other. In an embodiment where the semiconductor die 400 overlaps the stacking unit 50 (in the form of a chip) in a multi-to-one architecture, the semiconductor die 400 covering a corresponding semiconductor die 100 and the semiconductor die 400 covering the remaining semiconductor dies 100 are electrically independent (e.g., electrically isolated). In some embodiments, the semiconductor die 400 is bonded to the semiconductor die 100 by chip-on-chip (CoC) bonding.

[0153] See Figure 30 , in some embodiments, after bonding the semiconductor die 400 to the semiconductor die 100, an insulating encapsulant 1800, a dielectric layer 915, a dielectric layer 916, and a plurality of conductive terminals 917 are sequentially formed, and a cutting (or singulation) process is performed to form a plurality of semiconductor devices 5000. The formation and material of the insulating encapsulant 1800 are similar or substantially the same as those of the insulating encapsulant 800 discussed previously in Figure 10 and Figure 11 , and the formation and material of each of the dielectric layer 915, the dielectric layer 916, and the conductive terminals 917 (e.g., 917c and 917u) have been discussed previously in Figure 13 and will not be repeated here. For example, the insulating encapsulant 1800 laterally covers the semiconductor die 400 and the stacking unit 50 and the insulating encapsulant 800 exposed by the semiconductor die 400, and the connection structure 414 and the dielectric layer 413 of each semiconductor die 400 are exposed in an accessible manner by the insulating encapsulant 1800. In some embodiments, the conductive terminals 917 penetrate the dielectric layer 915 and the dielectric layer 916 to be electrically coupled to the semiconductor die 400 by directly contacting the connection structure 414.

[0154] In Figure 30 , for illustrative purposes and simplicity, only one semiconductor device 5000 is shown. In a non-limiting example, as Figure 30 shown for the semiconductor device 5000, each stacked structure 10 includes a semiconductor die 400, a semiconductor die 200, a semiconductor die 100 interposed between and electrically coupled to the semiconductor die 400 and the semiconductor die 200, an insulating encapsulant 800 that laterally covers the semiconductor die 100 and 200, an insulating encapsulant 1800 that laterally covers the semiconductor die 400 and covers the semiconductor die 100 and the insulating encapsulant 800 exposed by the semiconductor die 400, a conductive terminal 917 disposed on the semiconductor die 400 and electrically coupled to the semiconductor die 400, a dielectric layer 915 disposed between the semiconductor die 400 and the conductive terminal 917, a dielectric layer 916 disposed between the dielectric layer 915 and the conductive terminal 917, a carrier 700 disposed above the semiconductor die 200, a release layer 900 disposed between the carrier 700 and the semiconductor die 200, and a dielectric layer 500 disposed between the release layer 900 and the semiconductor die 200. In some embodiments, for each stacked structure 10 included in the semiconductor device 5000, the conductive terminal 917 is electrically coupled to the semiconductor die 400 through a connection structure 431, some of the conductive terminals 917 are electrically coupled to the semiconductor die 100 through the connection structure 431, an inner connection 407, a via 411, some of the connection structures 414, and some of the connection structures 114, and some of the conductive terminals 917 are electrically coupled to the semiconductor die 200 through the connection structure 431, an inner connection 407, a via 411, some of the connection structures 414, some of the connection structures 114, a via 111, an inner connection 107, a connection structure 108, and a connection structure 208. In some embodiments, the stacked structures 10 included in a single semiconductor device 5000 are electrically independent of each other (e.g., electrically isolated).

[0155] In some embodiments, the semiconductor die 100 included in each stacked structure 10 of the semiconductor device 5000 includes a substrate 101', a device layer 102, internal connections 107, a connection structure 108, a dielectric layer 109, a pad 110, a via 111, a dielectric layer 112, a dielectric layer 113, and a connection structure 114. In some embodiments, the semiconductor die 200 included in each stacked structure 10 of the semiconductor device 5000 includes a substrate 201, a device layer 202, internal connections 207, a connection structure 208, and a dielectric layer 209. In some embodiments, the semiconductor die 400 included in each stacked structure 10 of the semiconductor device 4000 includes a substrate 401', a device layer 402, internal connections 407, a connection structure 431, a dielectric layer 430, a pad 410, a via 411, a dielectric layer 412, a dielectric layer 413, and a connection structure 414.

[0156] In some embodiments, in the stacked structure 10 of the semiconductor device 5000, in the XY plane (e.g., Figure 31 top view (or plan view) in), the size of the semiconductor die 100 and the size of the semiconductor die 200 are the same as each other and greater than the size of the semiconductor die 400 that overlaps therewith. In other embodiments, in the stacked structure 10 of the semiconductor device 5000, in the XY plane (e.g., Figure 32 top view (or plan view) in), the size of the semiconductor die 100 and the size of the semiconductor die 200 are the same as each other and are substantially equal to the size of the semiconductor die 400 that overlaps therewith. In still other embodiments, in the stacked structure 10 of the semiconductor device 5000, in the XY plane (e.g., Figure 33 top view (or plan view) in), the size of the semiconductor die 100 and the size of the semiconductor die 200 are the same as each other and are less than the size of the semiconductor die 400 that overlaps therewith.

[0157] Similarly, the redistribution line structure 907 can be Figure 30 adopted by the semiconductor device 5000 of. The present disclosure is not limited thereto.

[0158] In some embodiments, the semiconductor die 300 and / or 400 and their respective variations may each be a memory (e.g., DRAM) alone. The semiconductor die 300 and / or 400 and their respective variations may each be a logic die. The semiconductor devices 1000, 1000A, 1000B, 2000, 3000, 4000, 4000A, 4000B, 5000 and / or their variations may each be further mounted on another electronic component or circuit structure, such as a mother board, a package substrate, a printed circuit board (PCB), a printed wiring board, and / or other carriers capable of carrying integrated circuits. Alternatively, the semiconductor devices 1000, 1000A, 1000B, 2000, 3000, 4000, 4000A, 4000B, 5000 and / or their variations may be integrated Fan-Out (InFO) packages, InFO packages with a Package-on-Package (PoP) structure, chip-on-wafer-on-substrate (CoWoS) packages, flip chip packages with InFO packages or the like, or may be part of an InFO package, an InFO package with a PoP structure, a CoWoS package, a flip chip package with an InFO package or the like. The present disclosure is not limited thereto. The conductive terminal 917 may be referred to as a connector or a terminal of the semiconductor devices 1000, 1000A, 1000B, 2000, 3000, 4000, 4000A, 4000B, 5000 and / or their variations.

[0159] Figure 34 A schematic cross-sectional view showing the application of a semiconductor device (e.g., the semiconductor devices 1000, 1000A, 1000B, 2000, 3000, 4000, 4000A, 4000B, 5000 and / or their variations) according to some embodiments of the present disclosure. Devices similar to the above devices or substantially the same reference numbers, as well as certain details or descriptions of the same devices (e.g., formation and materials) and their relationships (e.g., relative positioning architectures and electrical connections) are not repeated herein.

[0160] See Figure 34, in some embodiments, a component assembly SC is provided that includes a first component C1 and a second component C2 disposed above the first component C1. The first component C1 may be or may include a circuit structure, such as a motherboard, a package substrate, another printed circuit board (PCB), a printed wiring board, and / or other carrier capable of carrying integrated circuits. In some embodiments, the second component C2 mounted on the first component C1 may be similar to one of the semiconductor devices 1000, 1000A, 1000B, 2000, 3000, 4000, 4000A, 4000B, 5000 and / or its variants described above. For example, one or more second components C2 (e.g., semiconductor devices 1000, 1000A, 1000B, 2000, 3000, 4000, 4000A, 4000B, 5000 and / or its variants) may be electrically coupled to the first component C1 through a plurality of terminals CT. The terminals CT may be conductive terminals 917. In some embodiments, an underfill UF is formed between the gaps of the first component C1 and the second component C2 to at least laterally cover the terminals CT. Alternatively, the underfill UF is omitted. The underfill UF may be any acceptable material, such as a polymer, an epoxy resin, a molded underfill, or the like. In one embodiment, the underfill UF may be formed by underfill dispensing, capillary flow process, or any other suitable method. Due to the presence of the underfill UF, the bonding strength between the first component C1 and the second component C2 is enhanced.

[0161] According to some embodiments, a semiconductor device includes a first die, a second die, and a third die. The first die has a first side including a plurality of first connection structures and a second side including a plurality of second connection structures, wherein the first side is opposite to the second side. The second die has a third side including a plurality of third connection structures, wherein the plurality of third connection structures are in contact with the plurality of first connection structures of the first die. The third die has a fourth side including a plurality of fourth connection structures, wherein the plurality of fourth connection structures are in contact with the plurality of second connection structures of the first die. A first pitch of the plurality of first connection structures and a second pitch of the plurality of third connection structures are less than a third pitch of the plurality of fourth connection structures.

[0162] In one embodiment, in the semiconductor device, a first bonding interface between the plurality of first connection structures and the plurality of third connection structures includes a first metal-to-metal bonding interface and a first dielectric-to-dielectric bonding interface, and a second bonding interface between the plurality of second connection structures and the plurality of fourth connection structures includes a second metal-to-metal bonding interface and a second dielectric-to-dielectric bonding interface. In one embodiment, the semiconductor device further includes: an insulating encapsulant that laterally covers the first die and the second die, wherein a sidewall of the insulating encapsulant is substantially aligned with a sidewall of the third die. In one embodiment, the semiconductor device further includes: an insulating encapsulant that laterally covers the third die, wherein a sidewall of the insulating encapsulant is substantially aligned with sidewalls of the first die and the second die. In one embodiment, the semiconductor device further includes: a first insulating encapsulant that laterally covers the first die and the second die; and a second insulating encapsulant that laterally covers the third die, wherein a sidewall of the first insulating encapsulant is substantially aligned with a sidewall of the second insulating encapsulant. In one embodiment, in the semiconductor device, sidewalls of the first die, the second die, and the third die are substantially aligned with each other. In one embodiment, the semiconductor device further includes: a plurality of conductive terminals disposed on and electrically coupled to a plurality of fifth connection structures, the plurality of fifth connection structures being distributed on a fifth side of the third die, the fourth side being opposite to the fifth side. In one embodiment, in the semiconductor device, wherein a material of the plurality of fifth connection structures includes aluminum.

[0163] According to some embodiments, a semiconductor device includes a first stacked structure, a second stacked structure, and a plurality of conductive terminals. The first stacked structure and the second stacked structure each include a first die, a second die, and a third die. The first die has a first side and a second side. The second die is bonded to the first side of the first die through a first bonding interface that includes a first metal-to-metal bonding interface and a first dielectric-to-dielectric bonding interface. The third die is bonded to the second side of the first die through a second bonding interface that includes a second metal-to-metal bonding interface and a second dielectric-to-dielectric bonding interface. The first stacked structure and the second stacked structure are electrically independent. The plurality of conductive terminals are disposed on and electrically coupled to the third die of the first stacked structure and the third die of the second stacked structure.

[0164] In one embodiment, in the semiconductor device, in the stacking direction of the first die, the second die, and the third die, the projection of the first die is substantially equal to the projection of the second die. In one embodiment, in the semiconductor device, the first die of the first stacked structure is connected to the first die of the second stacked structure, the second die of the first stacked structure is connected to the second die of the second stacked structure, and the third die of the first stacked structure is connected to the third die of the second stacked structure. In one embodiment, in the semiconductor device, the first die of the first stacked structure is connected to the first die of the second stacked structure, the second die of the first stacked structure is connected to the second die of the second stacked structure, and the semiconductor device further includes: an insulating encapsulation that laterally covers the third die of the first stacked structure and the third die of the second stacked structure. In one embodiment, in the semiconductor device, the third die of the first stacked structure is connected to the third die of the second stacked structure, and the semiconductor device further includes: an insulating encapsulation that laterally covers the first die and the second die of the first stacked structure and the first die and the second die of the second stacked structure. In one embodiment, the semiconductor device further includes: a first insulating encapsulation that laterally covers the first die and the second die of the first stacked structure and the first die and the second die of the second stacked structure; and a second insulating encapsulation that laterally covers the third die of the first stacked structure and the third die of the second stacked structure. In one embodiment, the semiconductor device further includes: a redistribution line structure disposed on the third die of the first stacked structure and the third die of the second stacked structure, wherein the first stacked structure and the second stacked structure are electrically coupled to each other through the redistribution line structure.

[0165] According to some embodiments, a method of manufacturing a semiconductor device includes the following steps: providing a first wafer including a first die, the first die having a first side including a plurality of first connection structures and a second side including a plurality of second connection structures, the first side being opposite to the second side; providing a second wafer including a second die, the second die having a third side including a plurality of third connection structures; bonding the first die of the first wafer to the second die of the second wafer, the plurality of third connection structures being in contact with the plurality of first connection structures of the first die; providing a third die, the third die having a fourth side including a plurality of fourth connection structures; and bonding the first die to the third die, the plurality of fourth connection structures being in contact with the plurality of second connection structures of the first die, wherein a first pitch of the plurality of first connection structures and a second pitch of the plurality of third connection structures are less than a third pitch of the plurality of fourth connection structures.

[0166] In one embodiment, in the method, wherein providing the third die includes providing a third wafer including the third die, and bonding the first die to the third die includes performing wafer - on - wafer bonding having metal - to - metal bonding and dielectric - to - dielectric bonding. In one embodiment, in the method, wherein providing the third die includes providing a third wafer including the third die, and the method further includes: after bonding the first die of the first wafer to the second die of the second wafer and before bonding the first die to the third die, cutting the first wafer and the second wafer bonded thereto, wherein bonding the first die to the third die includes performing chip - on - wafer bonding having metal - to - metal bonding and dielectric - to - dielectric bonding. In one embodiment, in the method, wherein bonding the first die to the third die includes performing wafer - on - chip bonding having metal - to - metal bonding and dielectric - to - dielectric bonding. In one embodiment, the method further includes: after bonding the first die of the first wafer to the second die of the second wafer and before bonding the first die to the third die, cutting the first wafer and the second wafer bonded thereto, wherein bonding the first die to the third die includes performing chip - on - chip bonding having metal - to - metal bonding and dielectric - to - dielectric bonding.

[0167] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: A first die, having a first side including a plurality of first connection structures and a second side including a plurality of second connection structures, the first side being opposite to the second side; A second die, having a third side including a plurality of third connection structures, the plurality of third connection structures being in contact with the plurality of first connection structures of the first die; And A third die, having a fourth side including a plurality of fourth connection structures, the plurality of fourth connection structures being in contact with the plurality of second connection structures of the first die, wherein a first pitch of the plurality of first connection structures and a second pitch of the plurality of third connection structures are less than a third pitch of the plurality of fourth connection structures.

2. The semiconductor device according to claim 1, wherein Further comprising: An insulating encapsulant, laterally covering the first die and the second die, wherein sidewalls of the insulating encapsulant are substantially aligned with sidewalls of the third die.

3. The semiconductor device according to claim 1, wherein Further comprising: An insulating encapsulant, laterally covering the third die, wherein sidewalls of the insulating encapsulant are substantially aligned with sidewalls of the first die and the second die.

4. The semiconductor device according to claim 1, wherein Further comprising: A first insulating encapsulant, laterally covering the first die and the second die; and A second insulating encapsulant, laterally covering the third die, wherein sidewalls of the first insulating encapsulant are substantially aligned with sidewalls of the second insulating encapsulant.

5. The semiconductor device according to claim 1, characterized in that, Wherein sidewalls of the first die, the second die, and the third die are substantially aligned with each other.

6. A semiconductor device, characterized in that, Comprising: A first stacked structure and a second stacked structure, each comprising: A first die, having a first side and a second side; A second die, joined to the first side of the first die through a first bonding interface, the first bonding interface including a first metal-to-metal bonding interface and a first dielectric-to-dielectric bonding interface; and A third die, joined to the second side of the first die through a second bonding interface, the second bonding interface including a second metal-to-metal bonding interface and a second dielectric-to-dielectric bonding interface, wherein the first stacked structure and the second stacked structure are electrically independent; and A plurality of conductive terminals, disposed on and electrically coupled to the third die of the first stacked structure and the third die of the second stacked structure.

7. The semiconductor device according to claim 6, wherein Wherein the first die of the first stacked structure is connected to the first die of the second stacked structure, the second die of the first stacked structure is connected to the second die of the second stacked structure, and the third die of the first stacked structure is connected to the third die of the second stacked structure.

8. The semiconductor device according to claim 6, wherein Wherein the first die of the first stacked structure is connected to the first die of the second stacked structure, the second die of the first stacked structure is connected to the second die of the second stacked structure, and the semiconductor device further comprises: An insulating encapsulant, laterally covering the third die of the first stacked structure and the third die of the second stacked structure.

9. The semiconductor device according to claim 6, wherein Wherein the third die of the first stacked structure is connected to the third die of the second stacked structure, and the semiconductor device further comprises: An insulating encapsulation laterally covers the first die and the second die of the first stacked structure and the first die and the second die of the second stacked structure.

10. The semiconductor device according to claim 6, wherein, Further comprising: A first insulating encapsulation laterally covers the first die and the second die of the first stacked structure and the first die and the second die of the second stacked structure; And A second insulating encapsulation laterally covers the third die of the first stacked structure and the third die of the second stacked structure.

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