Semiconductor device

Abstract

The semiconductor device comprises a memory unit. The memory unit comprises a first transistor, a second transistor and a resistor. The first transistor and the second transistor are respectively operably coupled in series to the resistor. A second transistor is formed on the one or more dielectric layers such that the second transistor is configured to accumulate heat and provide the accumulated heat to the resistor when the memory cell is programmed.

Description

Technical Field

[0001] The present disclosure relates to a one-time programmable memory device, and more particularly to a one-time programmable memory device with a heating device. Background Art

[0002] The development of electronic devices, such as computers, portable devices, smart phones, Internet of Things (IoT) devices, etc., has increased the demand for memory devices. Generally, memory devices can be volatile memory and non-volatile memory devices. Volatile memory can store data when powered, but may lose the stored data once the power is turned off. Different from volatile memory, non-volatile memory can retain data even after the power is turned off, but may be slower than volatile memory. Summary of the Utility Model

[0003] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a memory cell. The memory cell includes a first transistor, a second transistor, and a resistor. The first transistor and the second transistor are respectively operably coupled in series to the resistor. The second transistor is formed on one or more dielectric layers such that the second transistor is configured to accumulate heat and supply the accumulated heat to the resistor when programming the memory cell.

[0004] In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a plurality of one-time programmable (OTP) memory cells formed as a memory array. Each OTP memory cell includes a first transistor; a second transistor, and a metal resistor, wherein the first transistor and the second transistor are respectively operably coupled in series to the metal resistor.

[0005] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a memory cell. The memory cell includes a first transistor, a second transistor, and a resistor. The first transistor and the second transistor are respectively operably coupled in series to the resistor. Wherein the first transistor includes a three-dimensional channel formed of a first semiconductor surface oxide material, and the second transistor includes a two-dimensional channel formed of a semiconductor surface oxide material. Brief Description of the Drawings

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figure 1Block diagram showing an exemplary semiconductor device according to some embodiments;

[0008] Figure 2 Exemplary schematic diagram of a fuse memory cell of a semiconductor device shown according to some embodiments Figure 1 which includes a heating transistor;

[0009] Figure 3 Cross-sectional view of a semiconductor device including one of the Figure 2 fuse memory cells shown according to some embodiments;

[0010] Figure 4 Cross-sectional view of a semiconductor device including one of the Figure 2 fuse memory cells shown according to some embodiments;

[0011] Figure 5 Cross-sectional view of a semiconductor device including one of the Figure 2 fuse memory cells shown according to some embodiments;

[0012] Figure 6 Cross-sectional view of a semiconductor device including one of the Figure 2 fuse memory cells shown according to some embodiments;

[0013] Figure 7 Exemplary layout diagram of a fuse memory cell of a semiconductor device shown according to some embodiments Figure 2 shown;

[0014] Figure 8 , Figure 9 , Figure 10 Other exemplary schematic diagrams of a fuse memory cell of a semiconductor device including a heating transistor according to some embodiments Figure 1 shown;

[0015] Figure 11 is an exemplary flowchart of a manufacturing method of a semiconductor device including the disclosed fuse memory cell according to some embodiments;

[0016] Figure 12 is an exemplary flowchart of an operating method of a semiconductor device including the disclosed fuse memory cell according to some embodiments;

[0017] Figure 13 Exemplary schematic diagram of an antifuse memory cell of a semiconductor device shown according to some embodiments Figure 1 shown;

[0018] Figure 14 Exemplary schematic diagram of a semiconductor device including Figure 13Cross-sectional view of a semiconductor device of one of the antifuse memory cells shown;

[0019] Figure 15 Illustrated according to some embodiments Figure 1 Exemplary schematic diagram of an antifuse memory cell of a semiconductor device;

[0020] Figure 16 、 Figure 17 Illustrated according to some embodiments respectively including Figure 15 Cross-sectional view of a semiconductor device of one of the antifuse memory cells shown.

[0021]

Symbol description

[0022] 100: Memory device

[0023] 102: Memory array

[0024] 103: Memory cell

[0025] 104: Row decoder

[0026] 106: Column decoder

[0027] 108: I / O circuit

[0028] 110: Control logic circuit

[0029] 200: Electric fuse memory cell

[0030] 202: Fuse resistor

[0031] 204: Access transistor

[0032] 206: Heating transistor

[0033] 300, 400: Semiconductor device

[0034] 301, 401: Substrate

[0035] 301F, 401F: Main surface

[0036] 302, 402: Fuse resistor

[0037] 304, 404: Access transistor

[0038] 306, 406: Heating transistor

[0039] 308, 408: Channel structure

[0040] 310, 410: Source / drain structure

[0041] 312, 412: Source / drain structure

[0042] 314,414: Metal gate structure

[0043] 316,416: Channel structure

[0044] 318,418: Source / drain structure

[0045] 320,420: Source / drain structure

[0046] 322,422: Metal gate structure

[0047] 330,430: Dielectric layer

[0048] 332,432: Middle-end conductor structure

[0049] 334,434: Middle-end conductor structure

[0050] 336,436: Metal wire

[0051] 338,438: Metal wire

[0052] 340,440: Via structure

[0053] 342,442: Via structure

[0054] 344,444: Metal wire

[0055] 346,446: Metal wire

[0056] 348,448: Via structure

[0057] 350,450: Via structure

[0058] 352,452: Metal wire

[0059] 500,600: Semiconductor device

[0060] 501,601: Substrate

[0061] 501F,601F: Main surface

[0062] 502,602: Fuse resistor

[0063] 504,604: Access transistor

[0064] 506,606: Heating transistor

[0065] 508,608: Channel structure

[0066] 510,610: Source / drain structure

[0067] 512,612: Source / drain structure

[0068] 514,614: Metal gate structure

[0069] 516,616: Bottom gate

[0070] 518,618: Gate dielectric

[0071] 520,620: Channel structure

[0072] 522,622: Source / drain structure

[0073] 524,624: Source / drain structure

[0074] 526,626: Via structure

[0075] 528,628: Via structure

[0076] 530,630: Metal wire

[0077] 532,632: Metal wire

[0078] 534,634: Via structure

[0079] 536,636: Via structure

[0080] 538,638: Metal wire

[0081] 640,646: Metal wire

[0082] 642,644,648: Via structure

[0083] 700: Layout

[0084] 702,704: Active region / pattern

[0085] 712,714,716,718,720,722,724,726,728,730: Gate structure / pattern

[0086] 732: Active region / pattern

[0087] 734,736,738,740: Gate structure / pattern

[0088] 750,752,754,756,758: Metal structure

[0089] 800: Electric fuse memory cell

[0090] 802: Fuse resistor

[0091] 804: Access transistor

[0092] 806: Heating Transistor

[0093] 900: Electric Fuse Memory Cell

[0094] 902: Fuse Resistor

[0095] 904: Access Transistor

[0096] 906: First Heating Transistor

[0097] 908: Second Heating Transistor

[0098] 1000: Electric Fuse Memory Cell

[0099] 1002: Fuse Resistor

[0100] 1004: Access Transistor

[0101] 1006: Heating Transistor

[0102] 1100: Method

[0103] 1102, 1104, 1106, 1108: Operations

[0104] 1200: Method

[0105] 1202, 1204: Operations

[0106] 1300: Antifuse Memory Cell

[0107] 1302: Programming Transistor

[0108] 1304: Reading Transistor

[0109] 1400: Semiconductor Device

[0110] 1401: Substrate

[0111] 1401F: Main Surface

[0112] 1402: Programming Transistor

[0113] 1404: Reading Transistor

[0114] 1500: Antifuse Memory Cell

[0115] 1502: Programming Transistor

[0116] 1504: First Reading Transistor

[0117] 1506: Second Reading Transistor

[0118] 1600: Semiconductor Device

[0119] 1601: Substrate

[0120] 1601F: Main surface

[0121] 1602: Programmed transistor

[0122] 1604: First read transistor

[0123] 1606: Second read transistor

[0124] 1700: Semiconductor device

[0125] 1701: Substrate

[0126] 1701F: Main surface

[0127] 1702: Programmed transistor

[0128] 1704, 1706: Read transistors

[0129] BL: Bit line

[0130] D: Drain

[0131] G: Gate

[0132] M0, M1, M2, M3, M4, M5, M6: Metallization layers

[0133] S: Source

[0134] SL: Source line

[0135] WL: Word line

[0136] WL1: First word line

[0137] WL2: Second word line

[0138] WLP: Programmed word line

[0139] WLR: Read word line

[0140] WLR1: First read word line

[0141] WLR2: Second read word line

[0142] X, Y, Z: Directions Detailed implementation manners

[0143] It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific embodiments or examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature over or above a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or symbols in the various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0144] In addition, for ease of description, the present disclosure may use spatial relative terms, such as "below", "beneath", "lower", "above", "upper", etc., to describe the relationship of one element or feature to one or more other elements or features, as shown in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0145] A one-time-programmable (OTP) memory device is a non-volatile memory device used in integrated circuits to adjust the circuit after integrated circuit fabrication. For example, OTP memory devices are used to provide repair information that controls the use of redundant cells when replacing defective cells in a memory array. Another use is to tune analog circuits by adjusting the capacitance or resistance values of analog circuits or by enabling and disabling certain parts of the system. Recently, the trend is that although the same product uses common process technologies, the same product may be manufactured in different manufacturing facilities. Despite the best engineering efforts, the processes in each facility may vary slightly. Therefore, using OTP memory devices can independently optimize the product functionality of each manufacturing facility.

[0146] As integrated circuit technology advances, the characteristics of integrated circuits (e.g., the width of the interconnect structure) decrease, thereby allowing more circuits to be implemented in the integrated circuit. When implementing OTP memories such as fuses, electrofuses (efuses), etc. in an integrated circuit, various challenges may be encountered. For example, as the width of the interconnect structure decreases, generally the size of one or more fuse components of the OTP memory shrinks accordingly. Given the continuously shrinking size of the fuse components, programming (e.g., burning out) the fuse components can become very challenging. Therefore, existing OTP memories are not entirely satisfactory in many aspects.

[0147] The present disclosure provides various embodiments of an OTP memory device including a plurality of fuse memory cells, each fuse memory cell including or operatively coupled to a heating device, where the heating device can be implemented as any of various forms of transistors. For example, each fuse memory cell may include a metal resistor (fuse element), a first transistor, and a second transistor. The first transistor and the second transistor are both electrically connected in series to the metal resistor, and further, the second transistor is thermally coupled to the metal resistor. In various embodiments of the present disclosure, the first transistor can be operatively used as an access transistor for selectively allowing the memory cell (e.g., the metal resistor) to be programmed or read, and the second transistor can be operatively used as a heating transistor, which can raise the temperature of the metal resistor during programming. The metal resistor can be programmed once or a limited number of times. In one aspect of the present disclosure, the second transistor can be formed in a front-end-of-line (FEOL) network and include one or more bottom dielectric isolation (BDI) layers. Such BDI layers can prevent heat (e.g., heat generated from the second transistor) from dissipating through the substrate. In another aspect of the present disclosure, the second transistor can be formed as a back-gate transistor embedded in a back-end-of-line (BEOL) network. Since it is embedded in the BEOL network (usually formed by multiple dielectric layers), heat (e.g., heat generated from the second transistor) is not easily dissipated. Thus, in either aspect, the second transistor can advantageously heat the fuse element. Such a "heated" fuse element can help improve the programming yield of the fuse memory cell while keeping the size of the fuse element compatible with the sizes of various other device features in advanced technology nodes.

[0148] Figure 1 Exemplary block diagram of a semiconductor (e.g., memory) device 100 shown according to various embodiments. In Figure 1 the embodiment shown, the memory device 100 includes a memory array 102, a row decoder 104, a column decoder 106, an input / output (I / O) circuit 108, and control logic circuitry 110. Although not explicitly shown in Figure 1 it, the components of the memory device 100 are operatively coupled to each other and to control logic circuitry 112. For example, control logic circuitry 110, I / O circuit 108, row decoder 104, column decoder 106, can be electrically coupled to the memory array 102. Although in Figure 1In the example shown, for purposes of clarity of illustration, the elements are shown as separate blocks, but in some other embodiments, Figure 1 some or all of the elements shown in Figure 1 may be integrated together. For example, memory array 102 may include embedded I / O circuit 108.

[0149] Memory array 102 is a hardware element for storing data. In one aspect, memory array 102 is implemented as a semiconductor memory device. Memory array 102 includes a plurality of memory cells (or other storage units) 103. Memory array 102 includes a plurality of rows R1, R2, R3... R each extending along a first direction (e.g., the X direction), M and a plurality of columns C1, C2, C3... C each extending along a second direction (e.g., the Y direction). N (e.g., the Y direction). Each row / column may include one or more conductive structures. In some embodiments, each memory cell 103 is arranged at the intersection of a corresponding row and a corresponding column, and may be operated according to the voltage or current through the corresponding conductive structures of the column and the row.

[0150] According to various embodiments of the present disclosure, each memory cell 103 can be implemented as a one-time programmable (OTP) memory device, e.g., a fuse memory cell including a fuse resistor, an access transistor, and a heating transistor, wherein the access transistor and the heating transistor are both serially coupled to the fuse resistor. The access transistor and the heating transistor may be coupled to (e.g., gated by) the same word line (WL) or different WLs respectively. The access transistor and the heating transistor can be turned on / off simultaneously or separately to enable / disable access to the corresponding fuse resistor (e.g., programming, reading). For example, once selected, the access transistor and the heating transistor of the selected fuse cell can be turned on simultaneously (e.g., through the same WL) to create a programming or reading path through its fuse resistor and itself. When in programming, the heating transistor can generate heat for at least the fuse resistor by preventing heat dissipation. By placing the heating transistor substantially close to the fuse resistor, the accumulated heat can help raise the temperature of the fuse resistor. Thus, the programming efficiency of memory cell 103 can be significantly improved. A detailed description of memory cell 103 configured as a fuse memory cell (sometimes referred to as fuse memory cell 103) will be discussed below with reference to Figure 2 Figure 2 .

[0151] The row decoder 104 is a hardware component that can receive a row address of the memory array 102 and assert a conductive structure (e.g., a word line) at this row address. The column decoder 106 is a hardware component that can receive a column address of the memory array 102 and assert one or more conductive structures (e.g., bit lines, source lines) at this row address. The I / O circuit 108 is a hardware component that can access (e.g., read, program) each memory cell 103 asserted by the row decoder 104 and the column decoder 106. The control logic circuit 110 is a hardware component that can control the coupled components (e.g., the memory array 102 to the I / O circuit 108).

[0152] Figure 2 According to some embodiments, a exemplary configuration of the fuse memory cell 200 is shown, which has improved programming efficiency by heating through a heating transistor included in the fuse memory cell 200. The fuse memory cell 200 can be Figure 1 one of the memory cells 103. In Figure 2 the example, the fuse memory cell 200 is implemented as a two-transistor-one-resistor (2T1R) configuration, e.g., a fuse resistor 202, an access transistor 204, and a heating transistor 206, where the access transistor 204 and the heating transistor 206 are both serially coupled to the fuse resistor 202. Specifically, the access transistor 204 can have one of its source / drain terminals (e.g., Figure 2 the drain terminal in Figure 2 ), and the heating transistor 206 can have one of its source / drain terminals (e.g.,

[0153] Figure 2 the drain terminal in

[0153] ), and is electrically coupled to the same terminal of the fuse resistor 202. However, it should be understood that the fuse memory cell 200 can use any of various other fuse configurations that exhibit fuse characteristics, such as a two-diodes-one-resistor (2D1R) configuration, a multi-diode configuration, a many-transistors-one-resistor (multi-T1R) configuration, etc., while still being within the scope of this disclosure.

[0153] According to various embodiments of the present disclosure, the fuse resistor 202, the access transistor 204, and the heating transistor 206 are formed on the same side of the substrate, e.g., the front side of the semiconductor substrate. In one aspect of the present disclosure, both the access transistor 204 and the heating transistor 206 are formed along the front side surface of the semiconductor substrate, which is sometimes referred to as part of the front-end-of-line (FEOL) network. Such transistors are sometimes referred to as FEOL transistors. Above the FEOL network, a plurality of metallization layers are formed, each metallization layer including a plurality of conductive (e.g., metal) interconnect structures. Such metallization layers are sometimes referred to as part of the back-end-of-line (BEOL) network. The fuse resistor 202 can be formed as one or more metal structures in one of the metallization layers disposed above the access transistor 204 and the heating transistor 206. In another aspect of the present disclosure, the access transistor 204 can be formed in the FEOL network, while the heating transistor 206 and the fuse resistor 202 can be formed in the BEOL network. Such transistors are sometimes referred to as BEOL transistors. In another aspect of the present disclosure, the fuse resistor 202, the access transistor 204, and the heating transistor 206 can all be formed in the BEOL network.

[0154] In the case where the fuse resistor 202 of the electro-fuse memory cell 200 is implemented as a metal structure, e.g., the fuse resistor 202 can exhibit an initial resistance value (or resistivity) as manufactured. To program the electro-fuse memory cell 200, the access transistor 204 (if implemented as an n-type transistor) is turned on by applying a (e.g., voltage) signal corresponding to a logic high state via the first word line (WL1) to the gate terminal of the access transistor 204. Simultaneously or subsequently, a sufficiently high (e.g., voltage / current) signal is applied to one of the terminals of the fuse resistor 202 via the bit line (BL). When the access transistor 204 is turned on, a (e.g., programming) path can be provided from the BL, through the fuse resistor 202 and the access transistor 204, and to the source line (SL).

[0155] Before, simultaneously with, or after forming the program path, the heating resistor 206 (if implemented as another n-type transistor) can be turned on by applying a signal (e.g., voltage) corresponding to a logic high state via the second word line (WL2) to the gate terminal of the heating resistor 206. The first word line WL1 and the second word line WL2 can be the same or different. In various embodiments of the present disclosure, the heating transistor 206 can include one or more components (e.g., channel structure, source / drain structure) substantially close to or embedded in the dielectric layer, which can help accumulate heat. This heat can be provided to the thermally coupled fuse resistor 202 to raise the temperature of at least a portion of the corresponding metal structure (of the fuse resistor 202). As the above portion of the heating metal structure is heated, a high voltage / current signal can more effectively burn out (or fuse) the metal structure (of the fuse resistor 202). Thus, the fuse resistor 202 can transition from a first state (e.g., short circuit) to a second state (e.g., open circuit), which causes the electro-fuse memory cell 200 to irreversibly transition from a first logic state (e.g., logic 0) to a second logic state (e.g., logic 1). The logic state can be read out by applying a relatively low voltage signal on the BL and turning on the access transistor 204 to provide a path (e.g., for reading).

[0156] Figure 3 , Figure 4 , Figure 5 and Figure 6 According to some embodiments, cross-sectional views of semiconductor devices 300, 400, 500, and 600 are respectively shown, each semiconductor device including one of the electro-fuse memory cells 200, each electro-fuse memory cell being composed of a fuse resistor, an access transistor, and a heating transistor (e.g., the fuse resistor 202, access transistor 204, and heating transistor 206 respectively corresponding to Figure 2 . Figures 3 to 6 The cross-sectional views are taken along the length direction (e.g., X direction) of the channel structure of the access / heating transistor. In Figures 3 to 6 the illustrated embodiment, both the access transistor and the heating transistor can be implemented as gate-all-around (GAA) field-effect-transistor (FET) devices. However, it should be understood that the access transistor and the heating transistor can be implemented as any of various other types of transistor structures while still being within the scope of the present disclosure. Figures 3 to 6 is simplified to show the relative spatial configuration of the above components. Therefore, it should be understood that the semiconductor devices 300 to 600 can each include one or more other features / structures while still being within the scope of the present disclosure.

[0157] First, refer to Figure 3, the semiconductor device 300 includes a fuse resistor 302, an access transistor 304, and a heating transistor 306. In some embodiments, the fuse resistor 302, the access transistor 304, and the heating transistor 306 are formed on a first side (e.g., the front side) of a substrate 301. The substrate 301 can be implemented as part of a semiconductor wafer (e.g., a silicon wafer). Further, the access transistor 304 and the heating transistor 306 are formed along a main surface 301F of the substrate 301, while the fuse resistor 302 is formed as one or more metal structures (e.g., metal lines) disposed in one of a plurality of metallization layers (e.g., M0, M1, M2, etc.). Each of the above-mentioned metallization layers includes a plurality of metal structures or metal lines embedded in an inter-layer dielectric (ILD) or an inter-metal dielectric (IMD), and is generally disposed above the main surface 301F of the front side of the substrate 301. Hereinafter, the access transistor 304 and the heating transistor 306 are referred to as being formed in a FEOL network, and the fuse resistor 302 is referred to as being formed in a BEOL network.

[0158] In Figure 3 the illustrated embodiment, both the access transistor 304 and the heating transistor 306 are formed as GAA FETs. For example, the access transistor 304 includes a channel structure 308, source / drain structures 310, 312, and an active (e.g., metal) gate structure 314; the heating transistor 306 includes a channel structure 316, source / drain structures 318, 320, and an active (e.g., metal) gate structure 322. The channel structures 308 and 316 each consist of one or more nanostructures (e.g., nanosheets, nanowires) vertically spaced apart from each other along the Z direction. The metal gate structure 314 surrounds each nanostructure of the channel structure 308, and the source / drain structures 310 and 312 are coupled to the ends of the channel structure 308 along the X direction; the metal gate structure 322 surrounds the nanostructures of the channel structure 316, and the source / drain structures 318 and 320 are coupled to the ends of the channel structure 316 along the X direction.

[0159] Further, the access transistor 304 can be directly formed above the substrate 301, and in some embodiments according to the present disclosure, one or more components of the heating transistor 306 can be separated from the substrate 301 by a corresponding dielectric layer. As shown, a dielectric layer 330 is interposed between the substrate 301 and each of the source / drain structures 318 and 320. In some embodiments, the dielectric layer 330 can be a nitride oxide or a hydrogenated oxide composite of silicon oxide. In some embodiments, the dielectric layer 330 can be composed of silicon germanium oxide (SiGeO x ) and / or germanium oxide (GeO x) is formed. By forming a dielectric layer 330 between the source / drain structures 318, 320 and the substrate 301, heat generated during the operation of the semiconductor device 300 (e.g., the heating transistor 306) can be prevented from dissipating through the substrate 301, and thus accumulates rapidly. By placing the heating transistor 306 directly under the fuse resistor 302, the accumulated heat can be advantageously transferred to the fuse resistor 302, which can raise the temperature of the fuse resistor 302. In this way, the fuse resistor 302 can be programmed more effectively.

[0160] The semiconductor device 300 may further include a plurality of middle-end conductor (e.g., metal) structures, and each middle-end conductor structure may provide an electrical connection path for a corresponding gate structure or source / drain structure. For example, the semiconductor device 300 includes middle-end conductor structures 332 and 334. The middle-end conductor structure 332 is formed as a via structure and is in electrical contact with the gate structure 314 (sometimes referred to as "VG"), and the middle-end conductor structure 334 is in electrical contact with the source / drain structure 312 (sometimes referred to as "MD"). Above the middle-end interconnect structures (e.g., VG, MD), the semiconductor device 300 may further include a plurality of front-side metallization layers, such as M0, M1, M2, etc.

[0161] Above the middle-end interconnect structures (e.g., VG, MD), the semiconductor device 300 may further include a plurality of front-side metallization layers, such as M0, M1, M2, etc. Each metallization layer includes a plurality of back-end conductor structures, such as metal lines and via structures, embedded in a corresponding dielectric material (e.g., IMD or ILD). The IMD / ILD may include one or more of a low-k dielectric layer (i.e., a dielectric having a dielectric constant less than about 3.9), an ultra-low-k dielectric layer, or an oxide (e.g., silicon oxide).

[0162] For example, in Figure 3 , the semiconductor device 300 includes front-side metallization layers M0, M1, and M2. Although three front-side metallization layers are shown, it should be understood that the semiconductor device 300 may include any number of front-side metallization layers while still being within the scope of this disclosure. The metallization layer M0 includes metal lines 336 and 338 (sometimes referred to as "M0 tracks") and via structures 340 and 342 (sometimes referred to as "V0"); the metallization layer M1 includes metal lines 344 and 346 (sometimes referred to as "M1 tracks") and via structures 348 and 350 (sometimes referred to as "V1"); the metallization layer M2 includes metal lines 352 and 302 (sometimes referred to as "M2 tracks"). Thus, in the Figure 3 illustrated example, the fuse resistor 302 is one of the M2 tracks.

[0163] Next, refer to Figure 4, the semiconductor device 400 includes a fuse resistor 402, an access transistor 404, and a heating transistor 406. The semiconductor device 400 is substantially similar to the semiconductor device 300, except that the components of the heating transistor 406 are separated from the substrate having the corresponding dielectric layer 430. In other words, the heating transistor 406 is completely isolated from the substrate, as compared to the heating transistor 306 that is partially isolated from the substrate portion. Hereinafter, the access transistor 404 and the heating transistor 406 are referred to as being formed in the FEOL network, and the fuse resistor 402 is referred to as being formed in the BEOL network.

[0164] As shown, the access transistor 404 and the heating transistor 406 are formed along the main surface 401F of the substrate 401, while the fuse resistor 402 is formed as one or more metal structures (e.g., metal lines), where the metal structures are disposed in one of a plurality of metallization layers (e.g., M0, M1, M2, etc.) above the substrate 401. Both the access transistor 404 and the heating transistor 406 are formed as GAA FETs. For example, the access transistor 404 includes a channel structure 408, source / drain structures 410, 412, and an active (e.g., metal) gate structure 414; the heating transistor 406 includes a channel structure 416, source / drain structures 418, 420, and an active (e.g., metal) gate structure 422. Each of the channel structures 408 and 416 is composed of one or more nanostructures (e.g., nanosheets, nanowires) that are vertically spaced apart from each other along the Z direction. The metal gate structure 414 surrounds each nanostructure of the channel structure 408, and the source / drain structures 410 and 412 are coupled to the ends of the channel structure 408 along the X direction; the metal gate structure 422 surrounds each nanostructure of the channel structure 416, and the source / drain structures 418 and 420 are coupled to the ends of the channel structure 416 along the X direction.

[0165] According to some embodiments of the present disclosure, the access transistor 404 can be directly formed above the substrate 401, while the components of the heating transistor 406 can be separated from the substrate 401 by a common dielectric layer. As shown, the dielectric layer 430 is interposed between the substrate 401 and each of the source / drain structures 418 and 420. In some embodiments, the dielectric layer 430 can be a nitrided oxide or a hydrogenated oxide composite of silicon oxide. In some embodiments, the dielectric layer 430 can be composed of silicon germanium oxide (SiGeO x ) and / or germanium oxide (GeO x) is formed. By forming a dielectric layer 430 between the source / drain structures 418, 420 and the substrate 401, heat generated during the operation of the semiconductor device 400 (e.g., the heating transistor 406) can be prevented from dissipating through the substrate 401, thus accumulating rapidly. By placing the heating transistor 406 directly under the fuse resistor 402, the accumulated heat can be advantageously transferred to the fuse resistor 402, which can raise the temperature of the fuse resistor 402. In this way, the fuse resistor 402 can be programmed more effectively.

[0166] The semiconductor device 400 may also include a plurality of mid-end conductor (e.g., metal) structures, and each mid-end conductor structure may provide an electrical connection path for a corresponding gate structure or source / drain structure. For example, the semiconductor device 300 includes mid-end conductor structures 432 and 434. The mid-end conductor structure 432 is formed as a via structure and is in electrical contact with the gate structure 414 (sometimes referred to as "VG"), and the mid-end conductor structure 434 is in electrical contact with the source / drain structure 412 (sometimes referred to as "MD").

[0167] Above the mid-end interconnect structures (e.g., VG, MD), the semiconductor device 400 may also include a plurality of front-side metallization layers, such as M0, M1, M2, etc. Each metallization layer includes a plurality of back-end conductor structures, such as metal wires and via structures, embedded in a corresponding dielectric material (e.g., IMD or ILD). The IMD / ILD may include one or more of a low-k dielectric layer (i.e., a dielectric having a dielectric constant less than about 3.9), an ultra-low-k dielectric layer, or an oxide (e.g., silicon oxide).

[0168] For example, in Figure 4 , the semiconductor device 400 includes front-side metallization layers M0, M1, and M2. Although three front-side metallization layers are shown, it should be understood that the semiconductor device 400 may include any number of front-side metallization layers while still being within the scope of this disclosure. The metallization layer M0 includes metal wires 436, 438 (sometimes referred to as "M0 tracks") and via structures 440 and 442 (sometimes referred to as "V0"); the metallization layer M1 includes metal wires 444 and 446 (sometimes referred to as "M1 tracks") and via structures 448 and 450 (sometimes referred to as "V1"); the metallization layer M2 includes metal wires 452 and 402 (sometimes referred to as "M2 tracks"). Thus, in Figure 4 the example shown, the fuse resistor 402 is one of the M2 tracks.

[0169] Next, refer to Figure 5, the semiconductor device 500 includes a fuse resistor 502, an access transistor 504, and a heating transistor 506. The semiconductor device 500 has one or more components similar to those of the semiconductor device 300. For example, the access transistor 504 may also be formed along the main surface of the substrate (i.e., in the FEOL network), and the fuse resistor 502 may also be formed in one of the metallization layers disposed above the substrate (i.e., in the BEOL network). However, different from the heating transistor 306 of the semiconductor device 300, the heating transistor 506 may be formed in another metallization layer (i.e., in the BEOL network). Hereinafter, the access transistor 504 is referred to as being formed in the FEOL network, and the fuse resistor 502 and the heating transistor 506 are referred to as being formed in the BEOL network.

[0170] As shown, the access transistor 504 is formed along the main surface 501F of the substrate 501, while the fuse resistor 502 is formed as one or more metal structures (e.g., metal lines), where the metal structure is disposed in one of the plurality of metallization layers (e.g., M0, M1, M2, M3, M4, M5, etc.) located above the substrate 501, and the heating transistor 506 is formed in another metallization layer. For example, the fuse resistor 502 is formed in the metallization layer M4, and the heating transistor 506 is formed in the metallization layer M2. The access transistor 504 is formed as a GAA FET. For example, the access transistor 504 includes a channel structure 508, source / drain structures 510, 512, and an active (e.g., metal) gate structure 514. The channel structure 508 is composed of one or more nanostructures (e.g., nanosheets, nanowires) vertically spaced apart from each other along the Z direction. The metal gate structure 514 surrounds each nanostructure of the channel structure 508, and the source / drain structures 510 and 512 are coupled to the ends of the channel structure 508 along the X direction.

[0171] According to some embodiments of the present disclosure, the heating transistor 506 may have its components embedded in one or more dielectric layers. As shown, the heating transistor 506 is formed as a two-dimensional back-gate transistor, which includes a bottom gate 516, a gate dielectric 518 disposed above the bottom gate 516, a channel structure 520 disposed above the gate dielectric 518, and a pair of source / drain structures 522 and 524 disposed above the channel structure 520. The term "two-dimensional back-gate transistor" may refer to a transistor in which the gate is formed as a relatively flat structure and the channel structure contacts the top surface of the gate. The bottom gate 516, the gate dielectric 518, the channel structure 520, and the source / drain structures 522 and 524 are all disposed in the metallization layer M2. In addition, both the bottom gate 516 and the source / drain structures 522 and 524 may be formed as metal structures embedded in the ILD / IMD of the metallization layer M2.

[0172] Since the components of the heating transistor 506 are embedded in the ILD / IMD and disposed away from the substrate 501, heat generated during the operation of the semiconductor device 500 (e.g., the heating transistor 506) can be prevented from dissipating through the substrate 501, thereby rapidly accumulating heat. By directly placing the heating transistor 406 under or substantially close to the fuse resistor 502, the accumulated heat can be advantageously transferred to the fuse resistor 502, which can increase the temperature of the fuse resistor 502. In this way, the fuse resistor 502 can be programmed more effectively.

[0173] To compatibly fabricate the heating transistor 506 in the BEOL network, the channel structure 520 may include one or more n-type semiconductive-behaving oxide materials or two-dimensional (2D) materials. In the case where the access transistor 504 is formed as an n-type GAA FET, the channel structure 520 may include one or more n-type semiconductive oxide materials, such as IGZO, InZnO, InSnO, SnO2, MgAlZnO, etc. In some other embodiments, the channel structure 520 may be formed of one or more n-type 2D materials, such as transition metal dichalcogenide (TMD) materials, graphene, etc. Two-dimensional materials generally refer to crystalline solids composed of a single layer of atoms. The single layer of atoms may be derived from a single element or multiple elements. 2D materials may include compounds of transition metal atoms (Mo, W, Ti, etc.) and chalcogen atoms (S, Se, Te, etc.), such as WS2, WSe2, WTe2, MoS2, MoSe2, MoTe2, HfS2, ZrS2, and TiS2, GaSe, InSe, phosphorene, and other similar materials.

[0174] Generally, access transistor 504 and heating transistor 506 have the same conduction type (e.g., n-type). Thus, channel structure 520 is formed of one or more of the above-described n-type materials. However, it should be understood that in the case where access transistor 504 is formed as a p-type GAA FET, channel structure 520 may be formed of one or more p-type materials (i.e., heating transistor 506 is p-type). In this way, channel structure 520 may include one or more p-type semiconductor-exhibiting oxide materials such as CuO, SnO, oxides of the cuprite family Cu-X-O with or without doping, etc. In some other embodiments, channel structure 520 may be formed of one or more p-type 2D materials such as transition metal dichalcogenide (TMD) materials, graphene, etc.

[0175] Each front-side metallization layer, such as metallization layers M0 to M5, includes a plurality of back-end conductor structures such as metal lines and via structures embedded in corresponding dielectric materials (e.g., IMD or ILD). The IMD / ILD may include one or more of a low-k dielectric layer (i.e., a dielectric having a dielectric constant less than about 3.9), an ultra-low-k dielectric layer, or an oxide (e.g., silicon oxide).

[0176] For example, in Figure 5 , semiconductor device 500 includes front-side metallization layers M0, M1, M2, M3, M4, and M5. Although six front-side metallization layers are shown, it should be understood that semiconductor device 500 may include any number of front-side metallization layers while still being within the scope of this disclosure. Metallization layer M2 may house heating transistor 506 and further includes via structures 526 and 528 (sometimes referred to as "V2"); metallization layer M3 includes metal lines 530 and 532 (sometimes referred to as "M3 tracks") and via structure 534 (sometimes referred to as "V3"); metallization layer M4 includes metal line 502 (sometimes referred to as "M4 track") and via structure 536 (sometimes referred to as "V4"); metallization layer M5 includes metal line 538 (sometimes referred to as "M5 track"). Thus, in Figure 5 the example shown, fuse resistor 502 is one of the M4 tracks.

[0177] Then refer to Figure 6, the semiconductor device 600 includes a fuse resistor 602, an access transistor 604, and a heating transistor 606. The semiconductor device 600 has one or more components similar to those of the semiconductor device 500. For example, the fuse resistor 602 and the heating transistor 606 may also be formed in the BEOL network. However, different from the access transistor 504 of the semiconductor device 500 formed in the FEOL network, the access transistor 604 may be formed in the same metallization layer as the heating transistor 606 (i.e., in the BEOL network). Hereinafter, the access transistor 604, the fuse resistor 602, and the heating transistor 606 are all referred to as being formed in the BEOL network.

[0178] As shown, one or more transistors (e.g., GAAFETs) can be formed along the main surface 601F of the substrate 601 and operably used as a control circuit (e.g., a driver circuit, a control logic circuit, a decoder, etc.) of the memory cell of the semiconductor device 600, while the fuse resistor 602, the access transistor 604, and the heating transistor 606 are all formed in one or more of a plurality of metallization layers, such as M0, M1, M2, M3, M4, M5, etc., where the metallization layers are disposed on the substrate 501. For example, the fuse resistor 602 is formed in the metallization layer M5, and the access transistor 604 and the heating transistor 606 are formed in the metallization layer M2.

[0179] According to some embodiments of the present disclosure, the components of the access transistor 604 can be embedded in one or more dielectric layers. As shown, the access transistor 604 is formed as a three-dimensional back-gate transistor. The term "three-dimensional back-gate transistor" may refer to a transistor in which the gate is formed as a relatively protruding structure and the channel structure contacts multiple surfaces of the gate. For example, the access transistor 604 includes a bottom gate 608, a gate dielectric 610 disposed above the bottom gate 608, a channel structure 612 disposed above the gate dielectric 610, and a pair of source / drain structures 614, 616 disposed above the channel structure 612. The bottom gate 608, the gate dielectric 610, the channel structure 612, and the source / drain structures 614, 616 are all disposed in the metallization layer M2. In addition, the bottom gate 608 and the source / drain structures 614, 616 can both be formed as metal structures embedded in the ILD / IMD of the metallization layer M2. The gate dielectric 610 and the channel structure 612 can be sequentially conformally formed above the bottom gate 608. Thus, the bottom gate 608 can have at least three surfaces operably coupled (e.g., electrically coupled) to the channel structure 612, such as the top surface and sidewalls of the bottom gate 608.

[0180] According to some embodiments of the present disclosure, the heating transistor 606 may have its components embedded in one or more dielectric layers. As shown, the heating transistor 606 is formed as a two-dimensional back-gate transistor, which includes a bottom gate 618, a gate dielectric 620 disposed above the bottom gate 618, a channel structure 622 disposed above the gate dielectric 620, and a pair of source / drain structures 624 and 626 disposed above the channel structure 622. The bottom gate 618, the gate dielectric 620, the channel structure 622, and the source / drain structures 624 and 626 are all disposed in the metallization layer M2, such as the same metallization layer as the access transistor 604. However, it should be understood that the access transistor 604 and the heating transistor 606 may be disposed in different metallization layers respectively while still being within the scope of the present disclosure. In addition, the bottom gate 618 and the source / drain structures 624, 626 can both be formed as metal structures embedded in the ILD / IMD of the metallization layer M2.

[0181] Since the components of the heating transistor 606 are embedded in the ILD / IMD and are disposed away from the substrate 601, the heat generated during the operation of the semiconductor device 600 (e.g., the heating transistor 606) can be prevented from dissipating through the substrate 601 and thus can accumulate rapidly. By placing the heating transistor 306 directly under the fuse resistor 602, the accumulated heat can be advantageously transferred to the fuse resistor 602, which can raise the temperature of the fuse resistor 602. In this way, the fuse resistor 602 can be programmed more effectively.

[0182] To compatibly fabricate the access transistor 604 and the heating transistor 606 in the BEOL network, the channel structures 612, 622 may include one or more n-type semiconductive-behaving oxide materials or two-dimensional (2D) materials. In the case where the access transistor 504 is formed as an n-type transistor, the channel structures 612, 622 may include one or more n-type semiconductive oxide materials, such as IGZO, InZnO, InSnO, SnO2, MgAlZnO, etc. In some other embodiments, the channel structures 612, 622 may be formed of one or more n-type 2D materials, such as transition metal dichalcogenide (TMD) materials, graphene, etc. Two-dimensional materials generally refer to crystalline solids composed of single layers of atoms. The single layer of atoms can be derived from a single element or multiple elements. 2D materials may include compounds of transition metal atoms (Mo, W, Ti, etc.) and chalcogen atoms (S, Se, Te, etc.), such as WS2, WSe2, WTe2, MoS2, MoSe2, MoTe2, HfS2, ZrS2, and TiS2, GaSe, InSe, phosphorene, and other similar materials.

[0183] However, it should be understood that the channel structures 612, 622 can be formed of one or more p-type materials. In this way, the channel structures 612, 622 can include one or more p-type semiconductor-exhibiting oxide materials, such as CuO, SnO, oxides of the cuprite family Cu-X-O with or without doping, etc. In some other embodiments, the channel structures 612, 622 can be formed of one or more p-type 2D materials, such as transition metal dichalcogenide (TMD) materials, graphene, etc.

[0184] Each front-side metallization layer includes a plurality of back-end conductor structures, such as metal lines and via structures, embedded in a corresponding dielectric material (e.g., IMD or ILD). The IMD / ILD can include one or more of a low-k dielectric layer (i.e., a dielectric with a dielectric constant less than about 3.9), an ultra-low-k dielectric layer, or an oxide (e.g., silicon oxide).

[0185] For example, in Figure 6 , the semiconductor device 600 includes front-side metallization layers M0, M1, M2, M3, M4, and M5. Although six front-side metallization layers are shown, it should be understood that the semiconductor device 600 can include any number of front-side metallization layers while still being within the scope of this disclosure. The metallization layer M2 can accommodate both the access transistor 604 and the heating transistor 606, and also includes via structures 628, 630, 632, and 634 (sometimes referred to as "V2s"); the metallization layer M3 includes metal lines 636, 638, and 640 (sometimes referred to as "M3 tracks") and via structures 642 and 644 (sometimes referred to as "V3s"); the metallization layer M4 includes a metal line 646 (sometimes referred to as "M4 track") and a via structure 648 (sometimes referred to as "V4"); the metallization layer M5 includes a metal line 602 (sometimes referred to as "M5 track"). Thus, in Figure 6 the example shown, the fuse resistor 602 is one of the M5 tracks.

[0186] Figure 7 According to some embodiments, a semiconductor device 300 configured as the disclosed electric fuse memory cell is shown (e.g., Figure 3 ), Figure 4Example layout or top view of the semiconductor device 400). As disclosed herein, the fuse memory cell is formed by an access transistor, a heating transistor, and a fuse resistor, wherein both the access transistor and the heating transistor are serially connected to the fuse resistor. In addition, the heating transistor can be directly disposed under the fuse resistor to effectively spread the accumulated heat to the fuse resistor. In some embodiments, the access transistor can be composed of a plurality (e.g., about 100) of sub-transistors coupled in parallel to each other. The heating transistor can also be composed of a plurality of sub-transistors connected in parallel to each other. The fuse resistor can be composed of at least a front-side metal structure disposed above these sub-transistors.

[0187] As shown, the layout 700 includes patterns 702 and 704, each configured to form an active region (hereinafter referred to as "active region 702" and "active region 704", respectively); and patterns 712, 714, 716, 718, 720, 722, 724, 726, 728, and 730, each configured to form a gate structure (hereinafter referred to as "gate structure 712", "gate structure 714", "gate structure 716", "gate structure 718", "gate structure 720", "gate structure 722", "gate structure 724", "gate structure 726", "gate structure 728", and "gate structure 730", respectively). It should be understood that the layout 700 can include any number of active regions and gate structures while still being within the scope of this disclosure.

[0188] The active regions 702, 704 can extend along a first lateral direction (e.g., the X direction), while the gate structures 712 to 730 can extend along a different second lateral direction (e.g., the Y direction). In addition, the gate structures 712 to 720 can each cross the active region 702, and the gate structures 722 to 730 can each cross the active region 704. In various embodiments, each of the active regions 702, 704 is formed by a stacked structure protruding from the front-side surface of the substrate. This stacked structure includes a plurality of semiconductor nanostructures (e.g., nanosheets) extending along the X direction and vertically separated from each other. The portion of the semiconductor structure of the stacked structure covered by the gate structure is retained, while the other portions are replaced by a plurality of epitaxial structures. The remaining portion of the semiconductor structure can be configured as the channel of the corresponding transistor (or sub-transistor), the epitaxial structures coupled to both sides (or ends) of the remaining portion of the semiconductor structure can be configured as the source / drain structure (or terminal) of the transistor (or sub-transistor), and the portion of the semiconductor structure covered (e.g., across) by the gate structure can be configured as the gate structure (or terminal) of the transistor (or sub-transistor).

[0189] For example, in Figure 7In [the figure], the portion of the active region 702 covered by the gate structure 712 may include a plurality of nanostructures vertically separated from each other, which may be used as the channels of sub-transistors. The epitaxial structure replaces the portion of the active region 702 disposed on the opposite side of the gate structure portion 712. Such an epitaxial structure may be used as the source / drain terminals ( Figure 2 “D” and “S”) of the sub-transistors. The gate structure 712 may be used as the gate terminal ( Figure 2 “G”) of the sub-transistors. Therefore, it should be understood that the layout 700 may be used to fabricate a certain number of such sub-transistors. In some embodiments, such sub-transistors formed based on the patterns 702, 704, and the patterns 712 to 730 may be electrically coupled in parallel to each other to jointly serve as access transistors of an electric fuse memory cell (e.g., Figure 3 the access transistor 304).

[0190] The layout 700 further includes patterns 732, 734, 736, 738, and 740, where the pattern 732 is configured to form an active region (hereinafter referred to as “active region 732”), and the patterns 734 to 740 span across the active region 732 for forming gate structures (hereinafter referred to as “gate structure 734”, “gate structure 736”, “gate structure 738”, and “gate structure 740” respectively). Similar to the active regions 702-704 and the gate structures 712-730, the active region 732 and the gate structures 734-740 may jointly serve as a transistor, e.g., the heating transistor of an electric fuse memory cell (e.g., Figure 3 the heating transistor 306), so the description will not be repeated.

[0191] The layout 700 further includes patterns 750, 752, 754, 756, and 758, each configured to form a metal structure (hereinafter referred to as “metal structure 750”, “metal structure 752”, “metal structure 754”, “metal structure 756”, and “metal structure 758” respectively). The metal structures 750 to 758 may extend along a first lateral direction (e.g., the X direction), the metal structure 750 is the longest, and its length is approximately the same as the length of the active regions 702-704 (along the X direction), and the remaining portions of the metal structures 752 to 758 are shorter and offset from the metal structure 750 along the Y direction. The metal structures 750 to 758 may all be formed as metal lines (e.g., M2 tracks) disposed in the metallization layer M2 ( Figure 3 ). The metal structure 750 may be used as the fuse resistor of the electric fuse memory cell (e.g., Figure 3 the fuse resistor 302). The metal structure 750 may be used as the fuse resistor of the electric fuse memory cell (e.g., Figure 3The fuse resistor 302). In some embodiments, the active region 732 is directly disposed below the metal structure 750, which enables the heating transistor (e.g., Figure 3 The heating transistor 306) is directly disposed below the fuse resistor (e.g., Figure 3 The fuse resistor 302). As a result, the temperature of the fuse resistor can be effectively increased by the heating transistor.

[0192] In addition to the electrofuse memory cell 200 discussed with reference to Figure 2 , the present disclosure provides various other configurations in which an electrofuse memory cell can be effectively programmed by one or more heating transistors. Figure 8 , Figure 9 and Figure 10 show configurations of electrofuse memory cells 800, 900, and 1000 according to some embodiments of the present disclosure, respectively.

[0193] In Figure 8 , the electrofuse memory cell 800 includes a fuse resistor 802, an access transistor 804, and a heating transistor 806. The electrofuse memory cell 800 is similar to the electrofuse memory cell 200 ( Figure 2 ). However, different from the configuration shown in Figure 2 , one of the source / drain terminals of the access transistor 804 (e.g., Figure 8 The drain terminal in) can be electrically coupled to one of the terminals of the fuse resistor 802, while one of the source / drain terminals of the heating transistor 806 (e.g., Figure 8 The drain terminal in) can be electrically coupled to the other terminal of the fuse resistor 802. In some embodiments, both the access transistor 804 and the heating transistor 806 can be formed in the FEOL network as any one of various transistor structures (e.g., GAA FET), while the fuse resistor 802 can be formed in the BEOL network. In addition, at least one component of the heating transistor 806 can be isolated from the corresponding semiconductor substrate by a dielectric layer.

[0194] In Figure 9 , the electrofuse memory cell 900 includes a fuse resistor 902, an access transistor 904, a first heating transistor 906, and a second heating transistor 908. The electrofuse memory cell 900 is similar to the electrofuse memory cell 200 ( Figure 2 ). However, different from the configuration shown in Figure 2 , the electrofuse memory cell 900 includes an additional heating transistor 908. One of the source / drain terminals of the first heating transistor 906 (e.g., Figure 9 The drain terminal in) is electrically coupled to one of the terminals of the fuse resistor 902, and one of the source / drain terminals of the second heating transistor 908 (e.g.,Figure 9 The drain terminal (in []) can be electrically coupled to another terminal of the fuse resistor 902. In some embodiments, all access transistors 904, the first heating transistor 906, and the second heating transistor 908 can be formed as any one of various transistor structures (e.g., GAA FET) in the FEOL network, while the fuse resistor 902 can be formed in the BEOL network. Additionally, the first heating transistor 906 and the second heating transistor 908 can each have at least one component isolated from the corresponding semiconductor substrate by a dielectric layer.

[0195] In Figure 10 , the electro-fuse memory cell 1000 includes a fuse resistor 1002, an access transistor 1004, and a heating transistor 1006. The electro-fuse memory cell 1000 is similar to the electro-fuse memory cell 200 ( Figure 2 ). However, different from the configuration shown in Figure 2 , the gate terminals of the access transistor 1004 and the heating transistor 1006 can be controlled by the same bit line (WL). In some embodiments, the access transistor 1004 and the heating transistor 1006 can be formed as any one of various transistor structures (e.g., GAA FET) in the FEOL network, while the fuse resistor 1002 can be formed in the BEOL network. Additionally, on one hand, the heating transistor 1006 can have at least one component isolated from the corresponding semiconductor substrate by a dielectric layer. On the other hand, the access transistor 1004 and the heating transistor 1006 can each have at least one component isolated from the corresponding semiconductor substrate by a dielectric layer.

[0196] Figure 11 is a flowchart of an exemplary method 1100 for manufacturing a semiconductor device according to various aspects of the present disclosure. This semiconductor device includes the disclosed electro-fuse memory cell (e.g., Figure 3 's semiconductor device 300, Figure 4 's semiconductor device 400, Figure 5 's semiconductor device 500, Figure 6 's semiconductor device 600), and this electro-fuse memory cell has a fuse resistor, an access transistor, and at least one heating transistor. On one hand, some operations of the method 1100 can be used to manufacture at least one of the access transistor or the heating transistor as a transistor in the FEOL network. On the other hand, some operations of the method 1100 can be used to manufacture at least one of the access transistor or the heating transistor as a transistor in the BEOL network. It should be noted that the method 1100 is only an example and does not limit the present disclosure. Therefore, it should be understood that additional operations can be provided before, during, and / or after the method 1100, and some other operations may be briefly described herein. The following discussion of the method 1100 can refer toFigures 1 to 6 One or more components discussed

[0197] Brief overview, method 1100 begins at operation 1102, where a semiconductor substrate is provided. Method 1100 proceeds to operation 1104, where a plurality of first transistors are formed along a front-side surface of the semiconductor substrate. Method 1100 proceeds to operation 1106, where a plurality of front-side metallization layers are formed over the first transistors. Method 1100 selectively proceeds to 1108, where a plurality of second transistors are formed in one or more of the front-side metallization layers.

[0198] The interconnect structure of the first transistors and the front-side metallization layers can form a plurality of disclosed fuse memory cells (e.g., an array of fuse memory cells). In one aspect of the present disclosure, each fuse memory cell can include an access transistor, a heating transistor, and a fuse resistor, where the access transistor (e.g., access transistors 304, 404) and the heating transistor (e.g., heating transistors 306, 406) are implemented as corresponding first transistors, and the fuse resistor (e.g., fuse resistors 302, 402) is implemented as being disposed in one of the metallization layers. In another aspect of the present disclosure, each fuse memory cell can include an access transistor, a heating transistor, and a fuse resistor, where the access transistor (e.g., access transistor 504) is implemented as one of the first transistors, and the fuse resistor (e.g., fuse resistor 502) is implemented as an interconnect structure disposed in one of the metallization layers, and the heating transistor (e.g., heating transistor 506) is implemented as one of the second transistors. In another aspect of the present disclosure, each fuse memory cell can include an access transistor, a heating transistor, and a fuse resistor, where the fuse resistor (e.g., fuse resistor 602) is implemented as an interconnect structure disposed in one of the metallization layers, and the access transistor (e.g., access transistor 604) and the heating transistor (e.g., heating transistor 606) are implemented as corresponding second transistors.

[0199] First, referring to operation 1102, the semiconductor substrate can be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., where the semiconductor substrate can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate can be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a semiconductor material layer formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates can also be used, such as multi-layer or gradient substrates. In some embodiments, the semiconductor material of the substrate can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof.

[0200] Next, referring to operation 1104, a plurality of first transistors are formed along the front surface of the semiconductor substrate. The first transistors formed along the surface of the substrate are sometimes referred to as FEOL transistors. In an exemplary embodiment of the present disclosure, the first transistors can be implemented as GAA transistor structures. The GAA transistors can be formed by at least some of the following process steps: forming fin structures protruding from the substrate, where the fin structures include a plurality of first semiconductor nanostructures and a plurality of second semiconductor nanostructures stacked alternately with each other; forming a dummy gate structure across the fin structures; forming gate spacers disposed along opposite sidewalls of the dummy gate structure; recessing portions of the fin structures not covered by the dummy gate structure (and the gate spacers); replacing the ends of the second semiconductor nanostructures with dielectric materials to form a plurality of inner spacers; forming source / drain structures in the fin structures, the source / drain structures being disposed on opposite sides of the dummy gate structure; removing the dummy gate structure; removing the remaining second semiconductor nanostructures; and forming active (e.g., metal) gate structures to surround each of the first semiconductor nanostructures. In some embodiments, the first semiconductor nanostructures can be collectively referred to as the channels of the GAA transistors, and the second semiconductor nanostructures replaced by the active gate structures can be referred to as sacrificial nanostructures.

[0201] In examples where some of the first transistors are operatively configured as heating transistors (e.g., 306, 406), one or more dielectric layers may be formed along the front-side surface of the semiconductor substrate or buried in the semiconductor substrate before forming the first transistors. Such dielectric layers may be formed by oxidizing the front-side surface of the semiconductor substrate, performing epitaxial growth from the semiconductor substrate, or performing a deposition process. In one aspect of the present disclosure, the positions of the dielectric layers (e.g., 330) may respectively correspond to the source / drain structures of the heating transistors. In another aspect of the present disclosure, the positions of the dielectric layers (e.g., 430) may respectively correspond to the heating transistors.

[0202] Next, referring to operation 1106, a plurality of front-side metallization layers are formed over the first transistors, each front-side metallization layer including a plurality of interconnect structures embedded in the IMD / ILD. The interconnect structures may include a plurality of middle-end-of-line (MEOL) interconnect structures (e.g., MD, VD, VG) and a plurality of back-end-of-line (BEOL) interconnect structures (e.g., M0 tracks, V0, M1 tracks, etc.), as described above. Each interconnect structure may include one or more metal materials, such as tungsten (W), copper (Cu), gold (Au), cobalt (Co), ruthenium (Ru), or a combination thereof. The IMD / ILD in which the interconnect structures are embedded may include one or more of a low-k dielectric layer (i.e., a dielectric having a dielectric constant less than about 3.9), an ultra-low-k dielectric layer, or an oxide (e.g., silicon oxide).

[0203] Next, referring to the optional operation 1108, a plurality of second transistors may be formed in one or more of the front-side metallization layers. The second transistors formed in one or more of the front-side metallization layers are sometimes referred to as BEOL transistors. Some of the second transistors may be implemented as two-dimensional back-gate transistors (e.g., heating transistors 506, 606), which are operatively used as heating transistors. Some of the second transistors may be implemented as three-dimensional back-gate transistors (e.g., access transistor 604), which are operatively used as access transistors. Each BEOL transistor may have a channel structure formed of one or more semiconductor-exhibiting oxide materials or one or more 2D materials, where semiconductor-exhibiting oxides such as IGZO, InZnO, InSnO, SnO2, MgAlZnO, etc., and 2D materials such as transition metal dichalcogenide (TMD) materials, graphene.

[0204] Figure 12 According to various aspects of the present disclosure, shown are semiconductor devices 300 (e.g., Figure 3 ), semiconductor devices 400 (e.g., Figure 4 ), semiconductor devices 500 (e.g., Figure 5 ), semiconductor devices 500 (e.g., Figure 6Flowchart of an exemplary method 1200 of a semiconductor device 600), where each transistor consists of a fuse resistor, an access transistor, and at least one heating transistor. It should be noted that method 1200 is only an example and is not used to limit this disclosure. Therefore, it should be understood that additional operations can be provided before, during, and / or after method 1200, and some other operations may only be briefly described herein.

[0205] Method 1200 begins at operation 1202, where an electrofuse memory cell is provided. The electrofuse memory cell can consist of a fuse resistor, an access transistor, and at least one heating transistor. In various embodiments, operation 1202 can include some or all of the operations of method 1100( Figure 11 ). For example, an electrofuse memory cell (e.g., semiconductor devices 300, 400) can form its fuse resistor in the BEOL network while forming its access transistor and heating transistor in the FEOL network. In another example, an electrofuse memory cell (e.g., semiconductor device 500) can form its fuse resistor in the BEOL network while forming its access transistor and heating transistor in the FEOL network and the BEOL network, respectively. In another example, an electrofuse memory cell (e.g., semiconductor device 600) can form all of its fuse resistor, access transistor, and heating transistor in the BEOL network.

[0206] Method 1200 proceeds to operation 1204, where the fuse resistor is programmed, where the heating transistor heats the fuse resistor. Based on different configurations of the electrofuse memory cell, the temperature of the fuse resistor can be increased by propagating the heat accumulated by the heating transistor to the fuse resistor. In this way, the programming yield of the electrofuse memory cell can be advantageously improved. In Figures 3 to 4 the example, heat can be accumulated by the heating transistors 306 and 406 formed in the FEOL network. In Figures 5 to 6 the example, heat can be accumulated by the heating transistors 506 and 606 formed in the BEOL network.

[0207] Figure 13 An exemplary configuration of an antifuse memory cell 1300 is shown according to some embodiments. The antifuse memory cell 1300 can include components formed in the BEOL network. The antifuse memory cell 1300 can be Figure 1 one of the memory cells 103. The antifuse memory cell 1300 can be another form of OTP memory.

[0208] In Figure 13In the example of, the antifuse memory cell 1300 includes a programmed transistor 1302 and a read transistor 1304. The programmed transistor 1302 and the read transistor 1304 are electrically coupled in series with each other. In addition, one of the source / drain terminals of the programmed transistor 1302 is floating (e.g., not coupled to anything), the other source / drain terminal of the programmed transistor 1302 is connected to one of the source / drain terminals of the read transistor 1304, the gate terminal of the programmed transistor 1302 is coupled to the programmed word line (WLP); the gate terminal of the read transistor 1304 is coupled to the read word line (WLR), and the other source / drain terminal of the read transistor 1304 is coupled to the bit line (BL).

[0209] Figure 14 A cross-sectional view of a semiconductor device 1400 including one of the antifuse memory cells 1300 is shown according to some embodiments of the present disclosure. Each of the antifuse memory cells 1300 is composed of a programmed transistor and a read transistor (e.g., corresponding to Figure 13 the programmed transistor 1302 and the read transistor 1304 of). Figure 14 is simplified to show the relative spatial configuration of the above components. Therefore, it should be understood that the semiconductor device 1400 may include one or more other features / structures while still being within the scope of the present disclosure.

[0210] As shown, the semiconductor device 1400 includes a programmed transistor 1402 and a read transistor 1404 formed in a BEOL network above a substrate 1401. The programmed transistor 1402 and the read transistor 1404 can be operatively used as an antifuse memory cell, e.g., Figure 13 1300 of. In some embodiments, one or more transistors (e.g., GAA FETs) can be formed along the main surface 1401F of the substrate 1401, and these transistors can be operatively used as control circuits (e.g., driver circuits, control logic circuits, decoders, etc.) of the antifuse memory cells of the semiconductor device 1300, while both the programmed transistor 1402 and the read transistor 1404 are formed in one or more metallization layers disposed above the substrate 1401, such as M0, Ml, M2, M3, M4, M5, etc. For example, both the programmed transistor 1402 and the read transistor 1404 are formed in the metallization layer M2. In addition, in some embodiments, the programmed transistor 1402 can be configured as a two-dimensional back-gate transistor, and the read transistor 1404 can be configured as a three-dimensional back-gate transistor.

[0211] Figure 15 Another exemplary configuration of an antifuse memory cell 1500 is shown according to some embodiments. The antifuse memory cell 1500 may include components formed in a BEOL network. The antifuse memory cell 1500 may beFigure 1 One of the memory cells 103. The antifuse memory cell 1500 can be another form of OTP memory.

[0212] In Figure 15 In the example of, the antifuse memory cell 1500 includes a programmed transistor 1502, a first read transistor 1504, and a second read transistor 1506. The programmed transistor 1502 and the read transistors 1504, 1506 are electrically coupled in series with each other. In addition, one of the source / drain terminals of the programmed transistor 1502 is floating (e.g., not coupled to anything), and the other source / drain terminal is connected to one of the source / drain terminals of the first read transistor 1504. The gate terminal of the programmed transistor 1502 is coupled to a programmed word line (WLP). The gate terminal of the first read transistor 1504 is coupled to a first read word line (WLR1), and the other source / drain terminal of the first read transistor 1504 is coupled to one of the source / drain terminals of the second read transistor 1506; the gate terminal of the second read transistor 1506 is coupled to a second read bit line (WLR2), and the other source / drain terminal of the second read transistor 1506 is coupled to a bit line (BL).

[0213] Figure 16 A cross-sectional view of a semiconductor device 1600 including one of the antifuse memory cells 1500 is shown according to some embodiments of the present disclosure. Each antifuse memory cell is composed of a programmed transistor and two read transistors (e.g., corresponding to Figure 15 the programmed transistor 1502, the read transistors 1504 and 1506). Figure 16 is simplified to show the relative spatial configuration of the above components. Therefore, it should be understood that the semiconductor device 1600 may include one or more other features / structures while still being within the scope of the present disclosure.

[0214] As shown, the semiconductor device 1600 includes a programmed transistor 1602, a first read transistor 1604, and a second read transistor 1606 formed in a BEOL network above a substrate 1601. The programmed transistor 1602 and the read transistors 1604, 1606 can operate as an antifuse storage unit, for example Figure 15The semiconductor device 1500. In some embodiments, along the main surface 1601F of the substrate 1601, one or more transistors (e.g., GAA FETs) may be formed and operably used as a control circuit (e.g., driver circuit, control logic circuit, decoder, etc.) of the antifuse memory cell of the semiconductor device 1600, while the programmed transistor 1602 and the read transistors 1604, 1606 are all formed in one or more metallization layers disposed above the substrate 1601, such as M0, M1, M2, M3, M4, M5, etc. For example, the programmed transistor 1602 and the read transistors 1604, 1606 are both formed in the metallization layer M2. In addition, in some embodiments, the programmed transistor 1602 may be configured as a two-dimensional back-gate transistor, and the read transistors 1604 and 1606 may each be configured as three-dimensional back-gate transistors. Further, the programmed transistor 1602 and the read transistors 1604, 1606 may be disposed adjacent to each other laterally, where the read transistor 1604 is inserted between the programmed transistor 1602 and the read transistor 1606.

[0215] Figure 17 A cross-sectional view of another semiconductor device 1700 including one of the antifuse memory cells 1500 is shown according to some embodiments of the present disclosure. Each of the antifuse memory cells 1500 is composed of a programmed transistor and two read transistors (e.g., corresponding to Figure 15 1502, 1504, and 1506 respectively). Figure 17 is simplified to show the relative spatial configuration of the above components. Therefore, it should be understood that the semiconductor device 1700 may include one or more other features / structures while still being within the scope of the present disclosure.

[0216] As shown, the semiconductor device 1700 includes a programmed transistor 1702, a first read transistor 1704, and a second read transistor 1706 formed in a BEOL network above the substrate 1701. The programmed transistor 1702 and the read transistors 1704, 1706 may be operably used as antifuse memory cells, such as Figure 15Semiconductor device 1500. In some embodiments, one or more transistors (e.g., GAA FETs) may be formed along the main surface 1701F of the substrate 1701 and operably serve as control circuits (e.g., driver circuits, control logic circuits, decoders, etc.) of the antifuse memory cells of the semiconductor device 1700, while the programmed transistor 1702 and the read transistors 1704, 1706 are all formed in one or more metallization layers disposed above the substrate 1701, such as M0, M1, M2, M3, M4, M5, etc. For example, the programmed transistor 1702 and the read transistors 1704, 1706 are both formed in the metallization layer M2. Further, in some embodiments, the programmed transistor 1702 may be configured as a two-dimensional back-gate transistor, and the read transistors 1704 and 1706 may each be configured as three-dimensional back-gate transistors. Furthermore, the programmed transistor 1702 and the read transistors 1704, 1706 may be disposed adjacent to each other laterally, where the read transistor 1704 is inserted between the programmed transistor 1702 and the read transistor 1706.

[0217] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes memory cells. The memory cells include a first transistor, a second transistor, and a resistor. The first transistor and the second transistor are respectively operably coupled in series to the resistor. The second transistor is formed on one or more dielectric layers such that the second transistor is configured to accumulate heat and supply the accumulated heat to the resistor when programming the memory cell.

[0218] In some embodiments, a first transistor and a second transistor are both formed in a front-end-of-line (FEOL) network on a semiconductor substrate, and a resistor is formed in a back-end-of-line (BEOL) network on the FEOL network. In some embodiments, the first transistor includes a plurality of first channel structures vertically spaced from each other and a pair of first source / drain structures, and the second transistor includes a plurality of second channel structures vertically spaced from each other and a pair of second source / drain structures. In some embodiments, the first transistor includes a plurality of first channel structures vertically spaced from each other and a pair of first source / drain structures, and the second transistor includes a plurality of second channel structures vertically spaced from each other and a pair of second source / drain structures. In some embodiments, at least one of the second channel structures or the pair of second source / drain structures is coupled to the semiconductor substrate through a dielectric layer. In some embodiments, at least one of the first channel structures, the pair of first source / drain structures, the second channel structures, or the pair of second source / drain structures is coupled to the semiconductor substrate through a dielectric layer. In some embodiments, the second transistor is disposed directly below the resistor, and the first transistor is disposed laterally beside the second transistor. In some embodiments, the first transistor is formed in a front-end-of-line (FEOL) network on a semiconductor substrate, and the second transistor and the resistor are disposed in a back-end-of-line (BEOL) network on the FEOL network. In some embodiments, the second transistor includes a two-dimensional channel formed of a semiconductor-exhibiting oxide material. In some embodiments, the first transistor, the second transistor, and the resistor are formed in a back-end-of-line (BEOL) network on a front-end-of-line (FEOL) network on a semiconductor substrate. In some embodiments, the first transistor includes a three-dimensional channel formed of a first semiconductor-exhibiting oxide material, and the second transistor includes a two-dimensional channel formed of a second semiconductor-exhibiting oxide material. In some embodiments, the memory cell includes an electric fuse, and the electric fuse is configured to be programmable once.

[0219] In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a plurality of one-time-programmable (OTP) memory cells formed as a memory array. Each OTP memory cell includes a first transistor; a second transistor; and a metal resistor, wherein the first transistor and the second transistor are respectively operably serially coupled to the metal resistor.

[0220] In some embodiments, a first transistor and a second transistor are both formed in a front-end-of-line (FEOL) network on a semiconductor substrate, and a resistor is formed in a back-end-of-line (BEOL) network on the FEOL network. In some embodiments, the first transistor includes a plurality of first channel structures vertically spaced apart from each other and a pair of first source / drain structures, and the second transistor includes a plurality of second channel structures vertically spaced apart from each other and a pair of second source / drain structures. In some embodiments, at least one of the second channel structures or the pair of second source / drain structures is coupled to the semiconductor substrate through a dielectric layer. In some embodiments, the first transistor is formed in a front-end-of-line (FEOL) network on a semiconductor substrate, and the second transistor and the resistor are disposed in a back-end-of-line (BEOL) network on the FEOL network. In some embodiments, the first transistor, the second transistor, and the resistor are formed in a back-end-of-line (BEOL) network on a front-end-of-line (FEOL) network on a semiconductor substrate.

[0221] In another aspect of the present disclosure, a method for forming a memory is disclosed. The method includes forming a plurality of front-end-of-line (FEOL) transistors along a front surface of a substrate. The method includes forming a metal resistor in a first metallization layer among a plurality of metallization layers disposed above the front surface of the substrate. The first FEOL transistor is electrically coupled to the metal resistor, and the second FEOL transistor is thermally coupled to the metal resistor.

[0222] In some embodiments, the second FEOL transistor is formed on one or more dielectric layers, and one or more dielectric layers are inserted between the substrate and the second FEOL transistor such that the second FEOL transistor is configured to accumulate heat and provide the accumulated heat to the metal resistor.

[0223] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a memory cell. The memory cell includes a first transistor, a second transistor, and a resistor. The first transistor and the second transistor are respectively operably coupled in series to the resistor. The first transistor includes a three-dimensional channel formed of a first semiconductor manifestation oxide material, and the second transistor includes a two-dimensional channel formed of a semiconductor surface oxide material.

[0224] In some embodiments, the memory cell includes an electric fuse, and the electric fuse is configured to be programmable once.

[0225] As used herein, the term "about / approximately" generally indicates a given amount of a numerical value that can vary based on the particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" can represent a given amount of a numerical value that varies, for example, within a range of 10 - 30% of that numerical value (e.g., ±10%, ±20%, or ±30% of the numerical value).

[0226] The foregoing outlines features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations may be made therein within the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that, Comprising: A memory cell includes a first transistor, a second transistor, and a resistor; wherein the first transistor and the second transistor are each operatively serially coupled to the resistor; and wherein the second transistor is formed on one or more dielectric layers such that the second transistor is configured to accumulate heat and supply the accumulated heat to the resistor when the memory cell is programmed.

2. The semiconductor device according to claim 1, wherein wherein the first transistor and the second transistor are both formed in a front-end process network on a semiconductor substrate, and the resistor is formed in a back-end process network on the front-end process network.

3. The semiconductor device according to claim 2, wherein wherein the first transistor includes a plurality of first channel structures vertically spaced from each other and a pair of first source / drain structures, and the second transistor includes a plurality of second channel structures vertically spaced from each other and a pair of second source / drain structures.

4. The semiconductor device according to claim 3, wherein, wherein the second transistor is disposed directly below the resistor, and the first transistor is disposed laterally beside the second transistor.

5. The semiconductor device according to claim 1, wherein, wherein the first transistor is formed in a front-end process network on a semiconductor substrate, and the second transistor and the resistor are disposed in a back-end process network on the front-end process network.

6. A semiconductor device, characterized in that, Comprising: A plurality of one-time programmable memory cells are formed as a memory array, wherein each of the one-time programmable memory cells includes: A first transistor; A second transistor; and A metal resistor, wherein each of the first transistors and each of the second transistors are operatively serially coupled to the metal resistor.

7. The semiconductor device according to claim 6, wherein, wherein the first transistor and the second transistor are both formed in a front-end process network on a semiconductor substrate, and the resistor is formed in a back-end process network on the front-end process network.

8. The semiconductor device according to claim 7, wherein, wherein the first transistor includes a plurality of first channel structures vertically spaced from each other and a pair of first source / drain structures, and the second transistor includes a plurality of second channel structures vertically spaced from each other and a pair of second source / drain structures.

9. A semiconductor device, characterized in that, Comprising: A memory cell includes a first transistor, a second transistor, and a resistor; wherein the first transistor and the second transistor are each operatively serially coupled to the resistor; and wherein the first transistor includes a three-dimensional channel formed of a first semiconductor surface oxide material, and the second transistor includes a two-dimensional channel formed of a semiconductor surface oxide material.

10. The semiconductor device according to claim 9, wherein, wherein the memory cell includes an electric fuse, and the electric fuse is configured to be programmable once.

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