Integrated circuit device

Abstract

Various embodiments of the utility model relate to an integrated circuit device. Some embodiments relate to integrated circuit devices including etched recessed gate dielectric regions. The integrated circuit device includes: a substrate including a first upper surface; a gate dielectric region disposed at the first upper surface of the substrate and extending into the substrate; and a gate structure disposed on the gate dielectric region. The gate dielectric region includes a second upper surface and forms a recess extending below the second upper surface. The second upper surface includes a peripheral portion surrounding the recess. The gate structure completely covers the second upper surface of the gate dielectric region and extends into the recess.

Description

Technical Field

[0001] Embodiments of the present utility model relate to an integrated circuit device. Background Art

[0002] Mixed-signal integrated circuit (IC) devices combine analog (e.g., high-voltage) circuits and digital (e.g., logic) circuits on the same IC die. Considering the various design and manufacturing constraints (e.g., dielectric layer depth, active region pattern density and layout, metal pattern density and layout, etc.) typically imposed on the circuits of a particular IC device, regardless of the specific type of circuits used in the device, technological advancements in one IC technology (e.g., high-voltage circuits) may not be easily applicable to, or may have an adverse impact on, another IC technology (e.g., logic circuits) employed on the same die. Summary of the Utility Model

[0003] In some embodiments, an integrated circuit device includes: a substrate including a first upper surface; a gate dielectric region disposed at the first upper surface of the substrate and extending into the substrate, the gate dielectric region including a second upper surface and a recess extending below the second upper surface, the second upper surface including a peripheral portion surrounding the recess; and a gate structure disposed on the gate dielectric region, the gate structure completely covering the second upper surface of the gate dielectric region and extending into the recess.

[0004] In some embodiments, an integrated circuit device includes: a substrate; a gate dielectric region disposed within the substrate and extending onto the upper surface of the substrate, the gate dielectric region including one or more sidewalls forming a recess in the upper surface of the gate dielectric region; a diffusion barrier disposed on the gate dielectric region, extending into the recess, and spanning the entire gate dielectric region; a conductive gate material disposed on the diffusion barrier and extending into the recess, the diffusion barrier isolating the conductive gate material from the gate dielectric region; and a dielectric structure disposed on the substrate and laterally beside the diffusion barrier and the conductive gate material. Description of the Drawings

[0005] Aspects of the present utility model may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0006] Figure 1A Cross-sectional views of some embodiments of an IC device employing an etched recessed gate dielectric region in accordance with the present utility model are shown.

[0007] Figure 1B A plan view showing some embodiments of an IC device with an etched recessed gate dielectric region according to the present utility model is presented.

[0008] Figure 2 A cross-sectional view showing some additional embodiments of an IC device with an etched recessed gate dielectric region according to the present utility model is presented.

[0009] Figures 3 - 14 A cross-sectional view showing the semiconductor structure of an IC device with an etched recessed gate dielectric region at various stages of manufacturing for some embodiments is presented.

[0010] Figure 12A and Figure 12B A cross-sectional view showing the semiconductor structure of a mixed-signal IC device with an etched recessed gate dielectric region 108 at a specific manufacturing stage for some embodiments is presented.

[0011] Figure 15 A method of forming an IC device with an etched recessed gate dielectric region according to some embodiments is presented. Detailed Description

[0012] The present utility model provides many different embodiments or examples for implementing different features of the present utility model. The following describes specific examples of components and arrangements to simplify the present utility model. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present utility model may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself prescribe the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatial relative terms such as "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one component or feature to another as shown in the figures. In addition to the orientation depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptions used herein may be interpreted accordingly.

[0014] Hybrid signal IC devices that integrate high-voltage circuits and logic circuits on the same die are widely used in various applications, such as interface or device drivers, image sensor processors, power management devices, and BCD (Bipolar-CMOS-DMOS) devices. Historically, high-voltage circuits sometimes included relatively thick gate oxide regions to make the gate compatible with high-voltage signals (e.g., by causing an increase in the ultimate breakdown voltage of the gate oxide). However, using a thick gate oxide requires forming the corresponding gate conductor (e.g., metal, polysilicon, etc.) at a relatively high (vertical) location (e.g., closer to the upper first metal (M1) layer). Thus, in some hybrid signal IC devices, particularly in more advanced devices that use a thin interlayer dielectric (ILD) structure (e.g., devices associated with a 28 nanometer (nm) or smaller technology node), using a thick gate oxide can be problematic. Because while maintaining a satisfactory gate oxide breakdown voltage, the resulting reduced distance between the gate conductor and the M1 layer may reduce the M1-to-gate breakdown voltage below an acceptable level.

[0015] To address this issue, a recessed gate oxide region can be employed as an alternative to using a relatively thick gate oxide. For example, the substrate or other underlying layer can be etched to form a recess, and then a gate oxide layer can be grown to cover the recess and the surrounding area of the substrate, and then a gate structure can be formed on the recessed gate oxide. In other embodiments, the gate oxide layer can be formed by a local oxidation of silicon (LOCOS) process. The resulting gate oxide region can provide a greater gate oxide breakdown voltage while maintaining a sufficient M1-to-gate distance.

[0016] However, any of the above methods (e.g., growing a gate oxide on a recessed region of the substrate or LOCOS) typically results in a reduction in the thickness of the gate oxide in the peripheral or "corner" regions of the gate oxide surrounding the recessed region. This reduced thickness is caused by the inability of the substrate in the corner region to provide sufficient silicon atoms during the oxidation process to provide a thick enough oxide for the gate oxide in the corner region. In some instances, this effect may ultimately lead to an undesirable bimodal (e.g., "double-humped") subthreshold source current (ID) versus gate voltage (V G ) characteristic curve (e.g., when the applied bias (V bs ) is less than or equal to -0.5 volts (V)), thus having an adverse effect on the performance of the associated transistor. This bimodal curve is created by two threshold voltages (V t ) associated with the recessed gate oxide region: a first threshold voltage V t1Less than an independent second threshold voltage V associated with the recessed portion of the gate oxide region t2 .

[0017] To address these issues, some embodiments of the present utility model provide an IC device including an etched recessed gate dielectric region (e.g., an etched recessed gate oxide region). In some embodiments, a relatively thick gate dielectric is formed (e.g., grown) on a substrate on a first upper surface. In some embodiments, the first upper surface may include a substantially flat (e.g., non-recessed) region of the substrate. The gate dielectric is then etched to form a recessed gate dielectric region that does not exhibit thinning in the corner regions of the structure, and thus does not produce a bimodal I D versus V G curve. Additionally, in some embodiments, the etching of the thick gate dielectric can be performed during the etching operation of the associated logic region of the IC device (e.g., for a gate dielectric recess outside the logic region, by performing a logical operation on the logic region mask data to increase the opening in the mask), and thus, at least two actions are combined during the fabrication of the IC device, reducing the amount of time and other resources consumed during IC fabrication. Forming the gate dielectric to a relatively large thickness greater than a typical high-voltage gate dielectric avoids thinning of the gate dielectric along the outermost edge. Additionally, by etching the gate dielectric to form a recessed gate dielectric region, the gate dielectric does not have a thickness that negatively impacts the performance of the device. Thus, the disclosed gate dielectric region can avoid a bimodal curve without negatively impacting the performance of the resulting device.

[0018] Figure 1A A cross-sectional view of some embodiments of an IC device 100 (e.g., a mixed-signal IC device) employing an etched recessed gate dielectric region in accordance with the present utility model is shown. The IC device 100 may include a substrate 102 (e.g., a silicon substrate) having a first upper surface 103. A gate dielectric region 108 may be disposed at the first upper surface 103 of the substrate 102. In some embodiments, the gate dielectric region 108 may extend into the substrate 102. The gate dielectric region 108 may include a second upper surface 109 and may form a recess 110 extending below the second upper surface 109. In some embodiments, the second upper surface 109 includes a peripheral portion 112 surrounding the recess 110.

[0019] In some embodiments, the gate structure 116 may be disposed on the gate dielectric region 108. Additionally, in some embodiments, the gate structure 116 (e.g., a gate conductive material such as polysilicon, metal, and / or another conductor) may completely cover the second upper surface 109 and extend into the recess 110 of the gate dielectric region 108. In some embodiments, the gate structure 116 may have a laterally extending portion that extends beyond the upper flat surface 117 of the gate dielectric region 108. In some embodiments, a diffusion barrier 120 (e.g., tantalum nitride (TaN)) may be disposed on the gate dielectric region 108 to isolate the gate structure 116 from the gate dielectric region 108. Additionally, in some embodiments, a transition layer 118 may be formed between the gate structure 116 and the diffusion barrier 120 (e.g., as a result of forming the gate structure 116).

[0020] In some embodiments, the isolation region 104 (e.g., a shallow trench isolation (STI) region including trenches filled with silicon dioxide (SiO2)) may be laterally positioned near the gate dielectric region 108. For example, the isolation region 104 may be disposed at opposite sides of the gate dielectric region 108 (e.g., to electrically isolate the IC device 100 from other portions of the substrate 102 for other semiconductor components). Additionally, in some embodiments, one or more doped regions ( Figure 1A (not shown in the figure) may be disposed in the substrate 102 near the gate dielectric region 108 as part of a transistor or other semiconductor component of the IC device 100. During operation, the doped regions may cause a channel region 106 to be formed in the substrate 102 below the gate dielectric region 108.

[0021] Additionally, in some embodiments, a dielectric layer 114 (e.g., SiO2), such as an interlayer dielectric (ILD), may be laterally disposed on the substrate 102 adjacent to the gate structure 116 and / or the diffusion barrier 120, and may at least partially extend over one or more isolation regions 104. Thus, in some embodiments, the diffusion barrier 120 may isolate the gate structure 116 from the gate dielectric region 108, one or more isolation regions 104, and the dielectric layer 114.

[0022] In some embodiments, since the recess 110 is etched after forming the gate dielectric region 108 (as opposed to etching the substrate 102 first and then forming the gate dielectric region 108), the gate dielectric region 108 will not exhibit a thinning corner region (e.g., in the Figure 1A corner region 113) or the corresponding double-peaked I associated with other recessed gate dielectric regions D versus V GThe characteristic curve is as described above. Conversely, forming the gate dielectric region 108 before the etching operation may facilitate a sufficiently wide peripheral portion 112 to prevent a bimodal characteristic curve. Additionally, in some embodiments, as discussed in more detail below, the recess 110 of the gate dielectric region 108 may be etched simultaneously with other dielectric structures (e.g., in the logic region of the IC device 100) through a process, where a single mask and associated process operations are integrated.

[0023] Although a single gate dielectric region 108 and associated gate structure 116 are discussed above and below, in other embodiments the IC device 100 may include several or multiple such structures.

[0024] Figure 1B A plan view of some embodiments of an IC device 100 employing an etched recessed gate dielectric region 108 in accordance with the present invention is shown. As shown, Figure 1B This does not represent a strict plan view, but rather a plan view showing various features of the gate dielectric region 108 relative to the substrate 102, source / drain regions 107, and connection structures 220 of the IC device 100. In some embodiments, the source / drain regions 107 of the substrate 102 may generally be Figure 1B aligned left and right, while the connection structures 220 (e.g., polysilicon structures) disposed on the substrate 102 may generally be Figure 1B aligned up and down. In some embodiments, the connection structures 220 may include one or more metal structures (e.g., metal structures within a first metal layer "M1"). Thus, in some embodiments, the source / drain regions 107 and the connection structures 220 may extend laterally parallel to the first upper surface 103 of the substrate 102 and be perpendicular to each other, as Figure 1B shown.

[0025] In some embodiments, as shown in the plan view of Figure 1B , the gate dielectric region 108 may be located at the intersection of the source / drain regions 107 and the connection structures 220. Additionally, in some embodiments, a first lateral dimension 241 of the gate dielectric region 108 may substantially conform to a corresponding lateral dimension of the connection structures 220, and a second lateral dimension 242 of the gate dielectric region 108 may substantially conform to a corresponding lateral dimension of the source / drain regions 107. In some embodiments, the first lateral dimension 241 and the second lateral dimension 242 may be equal or unequal. In some embodiments, each of the first lateral dimension 241 and the second lateral dimension 242 may be greater than or equal to about 0.36 micrometers (μm), greater than or equal to about 0.5 μm, or other similar values.

[0026] In some embodiments, the recess 110 of the gate dielectric region 108 is in Figure 1BThe plan view may have a rectangular (e.g., square) shape, but other shapes (e.g., rounded rectangular shape, circular shape, etc.) are also possible. Additionally, in some embodiments, the peripheral portion 112 around the recess 110 may be presented as a rectangular (e.g., square) boundary or frame, where each of the four linear segments of the peripheral portion 112 may have a corresponding first width 231, second width 232, third width 233, and fourth width 234. In some embodiments, each of the widths 231 - 234 of the peripheral portion 112 may be equal to or unequal to each other. Additionally, in some embodiments, each of the widths 231 - 234 of the peripheral portion 112 may be in the range of about 0.04 μm to about 0.1 μm, in the range of about 0.06 μm to about 0.08 μm, or other similar ranges.

[0027] Figure 2 A cross - sectional view shows some additional embodiments of an IC device 200 employing an etched recessed gate dielectric region according to the present utility model.

[0028] The IC device 200 includes a gate dielectric region 108 disposed on a substrate 102 and laterally disposed between sidewalls of isolation regions 104 of the substrate 102. The gate dielectric region 108 includes a lower surface that contacts the substrate 102. The outermost edge of the lower surface is coupled to an angled surface, which causes the gate dielectric region 108 to slope upward along the opposite outermost lower edges of the gate dielectric region 108. In some embodiments, the angled surface may include a curved surface.

[0029] The gate dielectric region 108 may include an inner sidewall 262 of a recess 110 formed to extend into a second upper surface 109 of the gate dielectric region 108. The recess 110 is disposed within a central region of the gate dielectric region 108, which is surrounded by a peripheral region of the gate dielectric region 108. In some embodiments, the inner sidewall 262 and the outermost sidewall 264 of the gate dielectric region 108 may slope towards each other to form a trapezoidal shaped upper portion 250 of the peripheral region. The recess 110 reduces the thickness of the central region of the gate dielectric region 108, such that the gate dielectric region has a first thickness 252 within the central region and a second thickness 254 along the outermost edge facing the isolation region 104. In some embodiments, the second thickness 254 may be greater than or equal to the first thickness 252. In some embodiments, the second thickness 254 may be greater than the first thickness 252 by an amount in the range of about 2 nm to 3 nm.

[0030] A gate structure 116 is disposed on a gate dielectric region 108. The gate structure 116 may be separated from the gate dielectric region 108 by a diffusion barrier 120. In some embodiments, the diffusion barrier 120 may extend from the top of the gate dielectric region 108 to directly between the outermost sidewall of the gate dielectric region 108 and the sidewall of the isolation region 104.

[0031] An upper dielectric structure 258 is disposed on the gate structure 116. An interconnect 256 extends through the upper dielectric structure 258 to contact the gate structure 116. In some embodiments, the interconnect 256 may include an interconnect contact or an interconnect via.

[0032] In some embodiments, an enhanced second thickness 254 of the peripheral region of the gate dielectric region 108 may cause two threshold voltages of the subthreshold I D versus V G characteristic curve to be reduced to a single threshold voltage, thereby eliminating the bimodal nature of the curve and improving transistor performance.

[0033] Figures 3 - 14 A cross-sectional view of some embodiments of a semiconductor structure for an IC device 100 is shown, where the IC device 100 employs an etched recessed gate dielectric region at various stages of fabrication. Additionally, Figure 12A and Figure 12B A cross-sectional view of some embodiments of a semiconductor structure of a mixed-signal IC device (e.g., IC device 100) that employs an etched recessed gate dielectric region at a particular stage of fabrication is shown. Although Figures 3 - 14 described as a series of actions, it should be understood that these actions are not restrictive as the order of the actions may be changed in other embodiments and the disclosed method is also applicable to other structures. In other embodiments, some of the actions shown and / or described may be omitted in whole or in part.

[0034] Figure 3 A portion of a substrate 102 that can be used as an infrastructure is shown, on which additional processing operations as Figures 4 - 14 shown can be performed. The substrate 102 can be a p-doped silicon (p-Si) substrate, but other materials can be used in other embodiments. Additionally, the substrate 102 may have a first upper surface 103 through which at least some of the processing operations shown in Figures 4 - 14 can be performed. Moreover, in some embodiments, the substrate 102 serves as a semiconductor wafer. After processing is completed (e.g., as described below in connection with Figures 4 - 14 ), such a wafer can optionally be stacked with other wafers and then diced into individual dies corresponding to individual IC devices 100.

[0035] Figure 4Illustrates the creation of at least one isolation region 104. In some embodiments, at least one isolation region 104 may be formed by etching the substrate 102 and then filling the resulting trenches with a material that forms at least one isolation region 104. In some embodiments, at least one isolation region 104 may include a dielectric (e.g., silicon dioxide (SiO2), silicon nitride (Si3N4), etc.). Although Figure 4 a cross-sectional view shows multiple isolation regions 104, two or more isolation regions 104 may be interconnected to form a single isolation region 104. In some embodiments, at least one isolation region 104 may limit or prevent leakage current passing through it during operation. Additionally, after forming at least one isolation region 104, chemical mechanical planarization (CMP) may be performed on the corresponding surface (e.g., the first upper surface 103 surface) of the substrate 102 including at least one isolation region 104. After creating the isolation region 104, one or more active (e.g., doped) regions ( Figure 4 not shown in

[0036] Figure 5 e.g., after forming at least one isolation region 104) may be formed within the substrate 102 via the first upper surface 103. As used herein, a doped (or active) region may be any active semiconductor region of the substrate 102, such as a doped n-region or p-region for transistor source and drain. Additionally, during operation, one or more channels (e.g., the channel region 106 of FIG. 1) may be formed due to the doped regions. Figure 7 shows a barrier structure 502 (e.g., silicon nitride (SiN)) being formed on one or more portions of the first upper surface 103 of the substrate 102. In some embodiments, the barrier structure 502 may be used as a sacrificial chemical barrier to isolate a portion of the substrate 102 from subsequent operations performed thereafter. More specifically, in some embodiments, portions of the first upper surface 103 of the substrate 102 (e.g., including one or more isolation regions 104) may be covered by the barrier structure 502 while allowing the region allocated for the gate dielectric region (e.g.,

[0037] Figure 6A gate dielectric region 108 is shown as being formed at a first upper surface 103 of a substrate (e.g., between one or more isolation regions 104), and the gate dielectric region 108 extends into the substrate 102. In some embodiments, the portion of the first upper surface 103 where the gate dielectric region 108 is formed is substantially flat to facilitate a generally flat second upper surface 109 of the gate dielectric region 108. In some embodiments, the gate dielectric region 108 can be grown at the first upper surface 103 of the substrate 102 through one or more oxidation processes, including wet (e.g., oxygen plus water vapor) and / or dry (e.g., oxygen only) oxidation techniques. As a result of one or more oxidation processes, the gate dielectric region 108 can obtain a thickness 602 sufficient to be subsequently etched while remaining capable of withstanding an expected high gate voltage (e.g., 4V to 35V, depending on the specific application). Additionally, in some embodiments, a majority of the thickness 602 of the gate dielectric region 108 extends downward into the substrate 102 (e.g., below the first upper surface 103).

[0038] In some embodiments, to grow the gate dielectric region 108, a wet thermal oxidation temperature of 900 to 950 degrees Celsius (°C) can be used. At such a temperature, in some examples, an oxidation treatment time of 50 to 70 minutes can produce a thickness 602 of 250 to 300 angstroms which may be suitable for a maximum expected gate voltage of 4 to 8V. In other examples, an oxidation treatment time of 200 to 240 minutes at the above temperature can produce a thickness 602 of 1000 to 1200 Å, which may be suitable for a maximum expected gate voltage of 20 to 35V. Depending on the needs of the specific application of the IC device 100, other combinations of oxidation temperature and treatment time can produce different thicknesses 602. In some embodiments, the thickness 602 corresponding to Figure 2 a second thickness 254 of the shown peripheral region can be positively correlated with the maximum expected gate voltage across the gate dielectric region.

[0039] Figure 7 It is shown that a barrier structure 502 is removed from the first upper surface 103 of the substrate 102, thereby exposing a relevant portion of the first upper surface 103 for further processing. In some embodiments, the removal of the barrier structure 502 can involve applying a chemical solution or reagent (e.g., a solvent) and subsequent rinsing, which removes the barrier structure 502 without affecting the remaining structures, such as one or more isolation regions 104 of the substrate 102 and the first upper surface 103.

[0040] Figure 8Illustrated is the formation (e.g., deposition and subsequent selective removal) of a sacrificial structure 802 (e.g., a polysilicon structure) over the entire second upper surface 109 of the gate dielectric region 108 and possibly further laterally extending (over a portion of one or more isolation regions 104). In some embodiments, the sacrificial structure 802 may be deposited over the entire first upper surface 103, substrate 102, and gate dielectric region 108 and then patterned (e.g., by etching, lift-off processing, or other processing) to selectively remove various portions of the sacrificial structure 802, such as those not covering the gate dielectric region 108.

[0041] Figure 9 Illustrated is the formation (e.g., deposition) of a dielectric layer 114 (e.g., SiO2) over the portion of the substrate 102 not occupied by the sacrificial structure 802. In some embodiments, such formation results in filling the regions in the substrate 102 not occupied by the sacrificial structure 802. In some embodiments, the dielectric layer 114 may be referred to as the interlayer dielectric zero (ILD0) since it is the first ILD of one or more ILDs to be formed over the substrate 102. Thereafter, in some embodiments, the upper surface, dielectric layer 114, and sacrificial structure 802 may be planarized (e.g., via chemical mechanical planarization (CMP)).

[0042] Figure 10 Illustrated is the removal of the sacrificial structure 802 from the first upper surface 103 of the substrate 102 and the second upper surface 109 of the gate dielectric region 108. In some embodiments, such removal may be accomplished via a lithography process, an etching process, a lift-off process, etc. In other embodiments, the removal of the sacrificial structure 802 may be achieved by applying a chemical solution or reagent (e.g., a solvent) and then rinsing, which removes the sacrificial structure 802 without affecting the remaining structures, such as the dielectric layer 114, one or more isolation regions 104, and the gate dielectric region 108.

[0043] Figure 11 Illustrated is the selective formation (e.g., deposition and patterning) of a mask layer 1102 (e.g., a photoresist layer, a hard mask layer, etc.). In some embodiments, the mask layer 1102 may include a photoresist layer that is deposited onto Figure 11 the structure shown and then masked ( Figure 12(not shown in the figure) is selectively patterned. In some embodiments, the mask layer 1102 can be a positive photoresist that becomes more soluble when irradiated with ultraviolet (UV) light (e.g., facilitated through holes or windows in the mask). In such embodiments, the portions of the mask layer 1102 formed on parts of the gate dielectric region 108 that will subsequently be etched can be irradiated and then removed by a solvent. Thus, in some embodiments, the remaining portions of the mask layer 1102 cover the peripheral portion 112 of the gate dielectric region 108 as well as at least one isolation region 104 and the dielectric layer 114.

[0044] Figure 12 The formation (e.g., etching) of the recess 110 in the gate dielectric region 108 is shown. In some embodiments, the etching is performed through a dry or wet etchant 1104 to remove the exposed portions of the gate dielectric region 108 (e.g., the portion of the gate dielectric region 108 inside the peripheral portion 112), thereby forming the recess 110. In some embodiments, the resulting recess 110 can extend below the level of the first upper surface 103 of the substrate 102 and / or can extend more than half of the thickness of the gate dielectric region 108. Etching the gate dielectric region 108 in this manner reduces or eliminates the possibility of thinning of the corner region 113 (shown in FIG. 1) of the gate dielectric region 108, which might otherwise result in a bimodal I D versus V G characteristic curve, as described above, thereby improving the performance of the gate dielectric region 108. For example, even if the gate dielectric region 108 has angled lower corners that cause the outer edge of the gate dielectric region 108 to extend into the substrate 102 to a shallower depth than the central region of the gate dielectric region 108, the gate dielectric region 108 is formed to a sufficient thickness such that the angled lower corners are not thin enough to cause an undesirable bimodal (e.g., "double-hump") subthreshold drain current (I D ) versus gate voltage (V G ) characteristic curve.

[0045] Figure 12A and 12B FIG. shows a cross-sectional view of some embodiments of a semiconductor structure of a mixed-signal IC device employing an etched recessed gate dielectric region at a particular manufacturing stage. More specifically, Figure 12A FIG. shows the mask layer 1102 employed in a mixed-signal IC device including a logic portion 1212 and a high-voltage portion 1214. The high-voltage portion 1214 includes a gate dielectric region 108 having a mask layer 1102 before being patterned (as Figure 11 shown), while the logic portion 1212 can include logic circuits ( Figure 12AAlthough not explicitly shown in the figure, it also includes the state before the patterning of the mask layer 1102. In some embodiments, a mask 1204 is used to perform subsequent patterning of the mask layer 1102 in both the logic portion 1212 and the high-voltage portion 1214.

[0046] In some embodiments, mask data for a logic input / output (IO) positive resist mask (RM) can be used to create the mask 1204. More specifically, in some embodiments, the mask data can initially specify a first opening 1208 to pattern the mask layer 1102 in the logic portion 1212, as well as other openings associated with the logic portion 1212. In some embodiments, the first opening 1208 can be associated with a connection, via, or other conductive connection to be formed within the dielectric layer 114, such as for a transistor or other components for a logic function (e.g., a control function for a high-voltage circuit coupled to the high-voltage portion 1214). Additionally, the mask data can be modified (e.g., through one or more logical operations) prior to creating the mask to include a second opening 1210 to pattern the shielding layer 1102 over the gate dielectric region 108, as Figure 11 shown.

[0047] Figure 12B shows the removal (e.g., etching by means of an etchant 1104) of the gate dielectric region 108 after patterning and removing portions of the mask layer 1102 associated with Figure 12A the first opening 1208 and the second opening 1210. Thus, in some embodiments, the creation of the recess 110 in the gate dielectric region 108 can be performed simultaneously with the creation of one or more voids or trenches in the logic portion 1212 of the mixed-signal IC device, resulting in process integration in the manufacture of the IC device, thereby potentially reducing the time and cost of such manufacture.

[0048] Figure 13 shows the formation (e.g., via conformal deposition) of a diffusion barrier 120 (e.g., tantalum nitride (TaN)) over the gate dielectric region 108. In some embodiments, the diffusion barrier 120 conformally contacts the recess 110 and the peripheral portion 112 of the gate dielectric region 108, one or more isolation regions 104, and possibly the sidewall 1302 of the dielectric layer 114 facing the gate dielectric region 108.

[0049] Figure 14Illustrated is the formation (e.g., deposition) of a gate structure 116 (e.g., polysilicon, metal, or other conductor) on a diffusion barrier 120. In some embodiments, the diffusion barrier 120 isolates the gate structure 116 from the gate dielectric region 108 and may isolate the gate structure 116 from at least one isolation region 104 and dielectric layer 114. In some embodiments, the formation of the gate structure 116 may cause the formation of a transition layer 118 between the gate structure 116 and the diffusion barrier 120, which may include materials from both the gate structure 116 and the diffusion barrier 120. Additionally, in some embodiments, a CMP process may be performed after depositing the gate structure 116 to planarize the upper surface provided by the gate structure 116, the diffusion barrier 120, and the dielectric layer 114, thereby providing an upper planar surface 117 for the gate structure 116. Thereafter, in some embodiments, additional dielectric layers (e.g., dielectric layers (ILD1, ILD2, etc.) and associated metal layers (M1, M2, etc.)) may be formed on the Figure 14 structure shown.

[0050] Figure 15 Illustrated is a method 1500 for forming an IC device with an etched recessed gate dielectric region according to some embodiments. Although this method and other methods shown and / or described herein are shown as a series of actions or events, it should be understood that the present invention is not limited to the shown order or actions. Thus, in some embodiments, these actions may be performed in an order different from the shown order and / or may be performed simultaneously. Additionally, in some embodiments, the shown actions or events may be subdivided into multiple actions or events, which may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some of the shown actions or events may be omitted and other actions or events not shown may be included.

[0051] In some embodiments, acts 1502 to 1514 may correspond to, for example, the structure previously shown in Figures 3 to 15 . At act 1502, for example, a substrate (e.g., substrate 102 of FIG. 1) may be provided. Figure 3 Illustrated is a cross-sectional view of some embodiments corresponding to act 1502.

[0052] At act 1504, at least one isolation region (e.g., at least one isolation region 104) may be formed in the substrate at a first upper surface of the substrate (e.g., the first upper surface 103 of FIG. 1). Figure 4 Illustrated is a cross-sectional view of some embodiments corresponding to act 1504.

[0053] At act 1506, a gate dielectric region (e.g., gate dielectric region 108 of FIG. 1) is formed at the first upper surface of the substrate. Figure 5 、 Figure 6 andFigure 7 A cross-sectional view corresponding to some embodiments of operation 1506 is shown.

[0054] In operation 1508, a dielectric layer (e.g., dielectric layer 114 of FIG. 1) is formed on a substrate at least in a logic region separated from the gate dielectric region. Figure 8 , 9 , FIGS. 10 and 12A show cross-sectional views corresponding to some embodiments of operation 1508.

[0055] In operation 1510, a recess (e.g., recess 110) is etched in a second upper surface of the gate dielectric region (e.g., second upper surface 109 of FIG. 1). In some embodiments, as described above, the etching of the recess can be performed simultaneously with the etching of the dielectric layer in the logic region through the same mask. Figure 12 and 12B Cross-sectional views corresponding to some embodiments of operation 1510 are shown.

[0056] In operation 1512, a diffusion barrier (e.g., diffusion barrier 120) is formed on the gate dielectric region. Figure 13 A cross-sectional view corresponding to some embodiments of operation 1512 is shown.

[0057] In operation 1514, a gate structure (e.g., gate structure 116) can be formed on the diffusion barrier. Figure 14 A cross-sectional view corresponding to some embodiments of operation 1514 is shown.

[0058] Some embodiments relate to an integrated circuit device. The integrated circuit device includes a substrate having a first upper surface, a gate dielectric region disposed at the first upper surface of the substrate and extending into the substrate, and a gate structure disposed on the gate dielectric region. The gate dielectric region includes a second upper surface and a recess extending below the second upper surface. The second upper surface includes a peripheral portion surrounding the recess. The gate structure completely covers the second upper surface of the gate dielectric region and extends into the recess.

[0059] In some embodiments, the gate structure includes an upper flat surface that extends laterally beyond the upper surface of the gate dielectric region. In some embodiments, it further includes: a diffusion barrier disposed on the gate dielectric region, the diffusion barrier isolating the gate structure from the gate dielectric region. In some embodiments, the substrate further includes: at least one isolation region adjacent to the gate dielectric region. In some embodiments, the gate structure extends onto the at least one isolation region. In some embodiments, it further includes: a diffusion barrier disposed on the gate dielectric region, the diffusion barrier laterally separating the gate structure from the gate dielectric region and the at least one isolation region. In some embodiments, it further includes: at least one isolation region adjacent to the gate dielectric region; and a dielectric structure disposed on the at least one isolation region. In some embodiments, the gate dielectric region has a first thickness in a central region of the gate dielectric region and a second thickness in a peripheral region of the gate dielectric region, the first thickness being less than the second thickness. In some embodiments, when viewed from a plan view of the gate dielectric region, the recess has a rectangular shape; and the peripheral portion includes a rectangular boundary, the rectangular boundary including four linear segments, each of the four linear segments having the same width. In some embodiments, the thickness of the peripheral portion of the gate dielectric region is positively correlated with the maximum expected gate voltage across the gate dielectric region. In some embodiments, the recess extends downward into the gate dielectric region below the first upper surface of the substrate.

[0060] Some embodiments relate to another integrated circuit device. The integrated circuit device includes a substrate, and a gate dielectric region disposed within the substrate and extending on the upper surface of the substrate. The gate dielectric region has one or more sidewalls that form a recess in the upper surface of the gate dielectric region. The integrated circuit device further includes a diffusion barrier disposed on the gate dielectric region, extending into the recess, and spanning the entire gate dielectric region. The integrated circuit device further includes a conductive gate material disposed on the diffusion barrier and extending into the recess. The diffusion barrier isolates the conductive gate material from the gate dielectric region. The integrated circuit device further includes a dielectric structure disposed on the substrate and laterally beside the diffusion barrier and the conductive gate material.

[0061] In some embodiments, it further includes: at least one isolation region disposed in the substrate adjacent to the gate dielectric region. In some embodiments, the conductive gate material and the diffusion barrier extend from above the top of the gate dielectric region to directly between the sidewalls of the gate dielectric region.

[0062] Some embodiments relate to a method of manufacturing an integrated circuit device. The method includes providing a substrate and forming a gate dielectric region at a first upper surface of the substrate. The gate dielectric region extends into the substrate. The method further includes etching a recess in a second upper surface of the gate dielectric region. The second upper surface includes a peripheral portion surrounding the recess. The method further includes forming a gate structure over the gate dielectric region. The gate structure completely covers the second upper surface of the gate dielectric region and extends into the recess.

[0063] In some embodiments, it further includes: before forming the gate dielectric region, forming at least one isolation region in the substrate via the first upper surface, and the gate dielectric region is adjacent to the at least one isolation region. In some embodiments, it further includes: before forming the gate dielectric region, forming an active region in the substrate, and the gate dielectric region is disposed on the active region. In some embodiments, it further includes: before forming the gate structure, forming a diffusion barrier over the gate dielectric region, and the diffusion barrier isolates the gate dielectric region from the gate structure. In some embodiments, it further includes: forming a dielectric layer at least on the substrate in a logic region separate from the gate dielectric region; and after forming the dielectric layer, etching the dielectric layer using a mask, wherein the recess is etched out using the mask. In some embodiments, etching the dielectric layer and etching out the recess are performed simultaneously.

[0064] It should be understood that in this written description and the appended claims, the terms "first", "second", "second", "third", etc. are merely general identifiers used for convenience in description to distinguish different terms. Elements of a figure or a series of figures. In and of themselves, these terms do not imply any chronological order or structural similarity of these devices, and are not intended to describe corresponding devices in different illustrated embodiments and / or unillustrated embodiments. For example, the "first dielectric layer" described in connection with the first figure may not necessarily correspond to the "first dielectric layer" described in connection with another figure, and may not necessarily correspond to the "first dielectric layer" in an unillustrated embodiment.

[0065] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand various aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of the present invention.

Claims

1. An integrated circuit device, characterized in that, Comprising: A substrate, including a first upper surface; A gate dielectric region, disposed at the first upper surface of the substrate and extending into the substrate, the gate dielectric region including a second upper surface, and a recess extending below the second upper surface, the second upper surface including a peripheral portion surrounding the recess; And A gate structure, disposed on the gate dielectric region, the gate structure completely covering the second upper surface of the gate dielectric region and extending into the recess.

2. The integrated circuit device according to claim 1, wherein The gate structure includes a laterally extending upper flat surface beyond the gate dielectric region.

3. The integrated circuit device according to claim 1, characterized in that, Further comprising: A diffusion barrier, disposed on the gate dielectric region, the diffusion barrier isolating the gate structure from the gate dielectric region.

4. The integrated circuit device according to claim 1, characterized in that, The substrate further includes: At least one isolation region, adjacent to the gate dielectric region.

5. The integrated circuit device according to claim 4, wherein The gate structure extends onto the at least one isolation region.

6. The integrated circuit device according to claim 1, wherein Further comprising: At least one isolation region, adjacent to the gate dielectric region; And A dielectric structure, disposed on the at least one isolation region.

7. The integrated circuit device according to claim 6, wherein The gate dielectric region has a first thickness in a central region of the gate dielectric region and a second thickness in a peripheral region of the gate dielectric region, the first thickness being less than the second thickness.

8. The integrated circuit device according to claim 1, wherein Viewed from a plan view of the gate dielectric region, the recess has a rectangular shape; and The peripheral portion includes a rectangular boundary, the rectangular boundary including four linear segments, each of the four linear segments having the same width.

9. The integrated circuit device according to claim 1, wherein The recess extends downward into the gate dielectric region below the first upper surface of the substrate.

10. An integrated circuit device, characterized in that, Comprising: A substrate; A gate dielectric region, disposed within the substrate and extending onto the upper surface of the substrate, the gate dielectric region including one or more sidewalls forming a recess within the upper surface of the gate dielectric region; A diffusion barrier, disposed on the gate dielectric region, extending into the recess, and spanning the entire gate dielectric region; A conductive gate material, disposed on the diffusion barrier and extending into the recess, the diffusion barrier isolating the conductive gate material from the gate dielectric region; And A dielectric structure, disposed on the substrate and laterally beside the diffusion barrier and the conductive gate material.

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