Semiconductor device

Abstract

A semiconductor device includes a first fin, a second fin, and a hybrid fin between the first fin and the second fin. The hybrid fin is shaped to include a base and a corner extending from the base on a side proximate to the second fin. An n-type epitaxial structure is supported by the first fin, and a p-type epitaxial structure is supported by the second fin. A slit fill or etch stop material is located between the hybrid fin and the second fin of the p-type epitaxial structure. The structure forms an additional space to increase the size of the n-type epitaxial structure, improve device efficiency, and reduce or eliminate leakage paths that may occur when the position of a metal contact is improperly displaced.

Description

Technical Field

[0001] The present disclosure generally relates to a semiconductor device. Background Art

[0002] Integrated circuits are made of a large number of transistors. A field-effect transistor typically consists of a substrate on which a conductive gate electrode controls the flow of current between a source electrode and a drain electrode. An electrically insulating gate dielectric layer separates the gate electrode from the source and drain electrodes. A semiconductor layer bridges the source and drain electrodes and contacts the gate dielectric layer. Summary of the Invention

[0003] Some aspects of the present disclosure relate to a semiconductor device that includes a substrate, at least one first fin, at least one second fin, and a hybrid fin. At least one first fin is on the substrate and supports an n-type epitaxial feature. At least one second fin is also on the substrate and supports a p-type epitaxial feature. The hybrid fin is located between at least one first fin and at least one second fin. The hybrid fin includes a base and a corner extending upward from the base on a side closer to at least one second fin.

[0004] Another semiconductor device is also disclosed herein, which includes a substrate, at least one first fin, at least one second fin, and a hybrid fin. At least one first fin is on the substrate and supports an n-type epitaxial feature. At least one second fin is also on the substrate and supports a p-type epitaxial feature. The hybrid fin has a base and a corner, wherein the hybrid fin is located between the n-type epitaxial feature and the p-type epitaxial feature.

[0005] Another semiconductor device is also disclosed herein, which includes a substrate, at least one first fin, at least one second fin, and a hybrid fin. At least one first fin is on the substrate and supports an n-type epitaxial feature. At least one second fin is also on the substrate and supports a p-type epitaxial feature. The hybrid fin is located between at least one first fin and at least one second fin. The hybrid fin includes a base and a corner, wherein the width of the corner is less than the width of the base. Brief Description of the Drawings

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A A Y-axis cross-sectional view showing a first exemplary embodiment of a semiconductor device according to some embodiments; in this embodiment, there is one n-type epitaxial structure located between two p-type epitaxial structures;

[0008] Figure 1B An enlarged view of a part of the semiconductor device;

[0009] Figure 1C The X-axis cross-sectional view of a first exemplary embodiment of line C-C passing through Figure 1A ;

[0010] Figure 2A The Y-axis cross-sectional view of a second exemplary embodiment of a semiconductor device according to some embodiments; in this embodiment, there are two n-type epitaxial structures located between two p-type epitaxial structures;

[0011] Figure 2B The Y-axis cross-sectional view of a third exemplary embodiment of a semiconductor device according to some embodiments; in this embodiment, a single n-type epitaxial structure and a single p-type epitaxial structure are each grown on two adjacent fins;

[0012] Figure 3 A flowchart depicting a method for forming a semiconductor device according to some embodiments; the various steps of this method are shown in Figures 4 to 17 ;

[0013] Figure 4 The Y-axis cross-sectional view after a processing step;

[0014] Figure 5 The Y-axis cross-sectional view after a processing step;

[0015] Figure 6 The Y-axis cross-sectional view after a processing step;

[0016] Figure 7 The Y-axis cross-sectional view after a processing step;

[0017] Figure 8 The Y-axis cross-sectional view after a processing step;

[0018] Figure 9 The Y-axis cross-sectional view after a processing step;

[0019] Figure 10 The Y-axis cross-sectional view after a processing step;

[0020] Figure 11 The Y-axis cross-sectional view after a processing step;

[0021] Figure 12 The Y-axis cross-sectional view after a processing step;

[0022] Figure 13 The Y-axis cross-sectional view after a processing step;

[0023] Figure 14 The Y-axis cross-sectional view after a processing step;

[0024] Figure 15 is the Y-axis cross-sectional view after the processing step;

[0025] Figure 16 is the Y-axis cross-sectional view after the processing step;

[0026] Figure 17 is the Y-axis cross-sectional view after the processing step.

[0027]

Symbol Explanation

[0028] 101: Semiconductor device

[0029] 102: Semiconductor device

[0030] 110: Substrate

[0031] 120: First fin

[0032] 125: Height

[0033] 128: n-type epitaxial structure

[0034] 129: Height

[0035] 130: Second fin

[0036] 135: Height

[0037] 138: p-type epitaxial structure

[0038] 139: Height

[0039] 140: Hybrid fin

[0040] 142: Base

[0041] 143: Height

[0042] 145: Width

[0043] 146: Corner

[0044] 147: Height

[0045] 149: Width

[0046] 150: Dielectric layer

[0047] 152: Gap-fill layer or etch stop layer

[0048] 154: Capping dielectric layer

[0049] 155: Through hole

[0050] 156: Metal contact

[0051] 157: Electric contact resistance reduction layer

[0052] 158: Conductive metal plug

[0053] 160: Gate oxide layer

[0054] 162: Gate electrode

[0055] 164: Metal contact

[0056] 166: Vertical dielectric gate spacer

[0057] 170: Hybrid fin

[0058] 172: Trench

[0059] 174: Secondary dielectric layer

[0060] 180: Level

[0061] 182: Gap

[0062] 185: Width

[0063] 187: Width

[0064] 300: Method

[0065] 305: Step

[0066] 310: Step

[0067] 315: Step

[0068] 320: Step

[0069] 325: Step

[0070] 330: Step

[0071] 335: Step

[0072] 340: Step

[0073] 345: Step

[0074] 350: Step

[0075] 355: Step

[0076] 360: Step

[0077] 365: Step

[0078] 370: Step

[0079] 375: Step

[0080] 380: Step

[0081] 385: Step

[0082] C-C: Line Detailed Implementation Manner

[0083] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features do not directly contact. Additionally, this disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not itself specify a relationship between the various embodiments and / or configurations discussed.

[0084] Furthermore, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one component or feature to another component or feature as depicted in the figures. In addition to the orientation depicted in the figures, spatially relative terms are intended to encompass different orientations of the device during use or operation. The device may be oriented otherwise (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0085] The numerical values in the specification and claims of this application should be understood to include the same numerical values when reduced to the same significant figures, and numerical values that differ from the stated values by less than the experimental error of the conventional measurement techniques of the type described in this application for determining that value. All ranges disclosed herein include the recited endpoints.

[0086] The term "about" may be used to include any numerical value that can vary without changing the basic function of that value. When used in conjunction with a range, "about" also discloses the range defined by the absolute values of the two endpoints, for example, "about 2 to about 4" also discloses the range "from 2 to 4". The term "about" may refer to plus or minus 10% of the indicated number.

[0087] This disclosure is about a structure made of different layers. When the terms "on", "above", or "over" are used to refer to two different layers (including the substrate), they only indicate that one layer is on or above another layer. These terms do not require the two layers to be in direct contact with each other, and allow other layers to be between the two layers. For example, all layers of a structure can be considered to be "on" the substrate, even if they do not directly contact the substrate. The term "directly" can be used to indicate that two layers are in direct contact with each other with no layer in between.

[0088] This disclosure relates to various methods and structures for improving device performance and reducing capacitance.

[0089] Figure 1A A Y-axis cross-sectional view showing a first exemplary embodiment of a semiconductor device 101 in accordance with some embodiments of the present disclosure and depicting some features. Figure 1B An enlarged view of a portion of the semiconductor device showing additional features. Figure 1C For passing through Figure 1A An X-axis cross-sectional view of a first exemplary embodiment of line C-C.

[0090] First referring to Figure 1A , the structure includes a substrate 110 having fins rising from the surface of the substrate. Generally, the fins are made of the same material as the substrate. Three fins are illustrated herein, a first fin 120 or a central fin, and two second fins 130 or outer fins. Each first fin 120 supports an n-type epitaxial structure 128, and each second fin 130 supports a p-type epitaxial structure 138. These fins 120, 130 are made of semiconductor material.

[0091] Hybrid fins 140 are located between each n-type epitaxial structure 120 and p-type epitaxial structure 130. The hybrid fins 140 are on a dielectric layer 150. The hybrid fins 140 themselves are made of a dielectric material and act as insulators to reduce or eliminate junction leakage between the n-type epitaxial structure 120 and the p-type epitaxial structure 130. The dielectric material constituting the hybrid fins 140 generally has a dielectric constant greater than that of the dielectric layer 150. In a particular embodiment, the dielectric layer 150 is made of silicon dioxide (SiO2), which has a dielectric constant of 3.9.

[0092] Each hybrid fin 140 includes a base 142 and a corner 146 extending upward from the base 142 on a side of the base closer to the second fin 130 or p-type epitaxial structure 138. A gap-fill layer or etch-stop layer 152 is present between the hybrid fin 140 and the second fin 130 or p-type epitaxial structure 138. A gap-fill layer or etch-stop layer 152 may also be present between the hybrid fin 140 and the first fin 120 or n-type epitaxial structure 128 and is illustrated in this manner, but this is not necessary.

[0093] Next, a capping dielectric layer 154 is applied over the hybrid fins 140, the n-type epitaxial structure 128, and the p-type epitaxial structure 138. This capping layer may also be referred to as a pre-metal dielectric (PMD) layer. Metal contacts 156 extend through the capping dielectric layer 154 and down to each of the n-type epitaxial structure 128 and the p-type epitaxial structure 138. Each metal contact includes a contact resistance reducing layer 157 and a conductive metal plug 158. The contact resistance reducing layer 157 is located between the epitaxial structures 128, 138 and the metal plug 158 and is used to reduce the electrical contact resistance.

[0094] Now referring Figure 1B , the gap-fill layer or etch stop layer 152 and the capping dielectric layer 154 are removed to show additional aspects of the structure. The first fin 120 has a measured height 125 to the base of the n-type epitaxial structure 128. The n epitaxial structure 128 itself has a height 129. Similarly, the second fin 130 has a measured height 135 to the base of the p epitaxial structure 138. The p-type epitaxial structure 138 itself has a height 139. In some embodiments, the volume of the n-type epitaxial structure is greater than the volume of the p-type epitaxial structure.

[0095] The base 142 of the hybrid fin 140 has a height 143 and a width 145. The corner 146 of the hybrid fin also has a height 147 and a width 149. The width 149 of the corner is less than the width 145 of the base. In certain embodiments, the height 143 of the base 142 is from about 20 nanometers to about 30 nanometers. In certain embodiments, the width 145 of the base 142 is from about 10 nanometers to about 20 nanometers. In certain embodiments, the height 147 of the corner 146 is from about 5 nanometers to about 10 nanometers. In certain embodiments, the width 149 of the corner 146 is from about 3 nanometers to about 8 nanometers. However, other values and ranges of these heights and widths are also within the scope of this disclosure.

[0096] The ratio of the corner height 147 to the base height 143 is typically from about 1:3 to about 1:1, or in other words, the corner height 147 is about 25% to about 50% of the base height 143. The ratio of the corner width 149 to the base width 145 is typically from about 1:3 to about 1:1, or in other words, the corner width 149 is about 25% to about 50% of the base width 145. Other values and ranges of these ratios are also within the scope of this disclosure.

[0097] In some specific embodiments, the height 143 of the base 142 of the hybrid fin is approximately equal to the height 135 of the second fin 130, that is, about 95% to about 100% of the height of the second fin. Other values and ranges are also within the scope of this disclosure.

[0098] As depicted herein, the corner 146 of the hybrid fin 140 extends upward and is located between the n-type epitaxial feature 128 and the p-type epitaxial feature 138. In a particular embodiment, the corner 146 extends upward to approximately half of the height 139 of the p-type epitaxial feature 138. In a particular embodiment, the corner extends upward approximately 30% to approximately 50% of the height 139 of the p-type epitaxial feature 138.

[0099] Referring now to Figure 1C the X-axis cross-sectional view of, additional portions of the semiconductor device are visible. Initially, a second fin 130 and two p-type epitaxial structures 138 on opposite ends of the second fin are shown. Metal contacts 156 extend downward through the capping dielectric layer 154 to each p-type epitaxial structure 138. Between the two p-type epitaxial structures 138, a gate oxide layer 160 contacts the second fin. A gate electrode 162 contacts the gate oxide layer 160. Another metal contact 164 extends through the capping dielectric layer 154 to the gate electrode 162. Optionally, if desired, vertical dielectric gate spacers 166 may be located near the gate electrode to further separate it from the two p-type epitaxial structures 138.

[0100] Figure 2A FIG. is a side cross-sectional view showing a second exemplary embodiment of the semiconductor device 102 according to some embodiments. In this embodiment, there are two n-type epitaxial structures between two p-type epitaxial structures.

[0101] In this embodiment, four fins are depicted, two first fins 120 or center fins and two second fins 130 or outer fins. Each first fin 120 supports an n-type epitaxial structure 128, and each second fin 130 supports a p-type epitaxial structure 138. Three hybrid fins 140, 170 are present between each set of fins. It should be noted that the hybrid fin 170 between the two n-type epitaxial structures 128 does not have a corner like the other two hybrid fins 140.

[0102] Figure 2B FIG. is a side cross-sectional view showing a third exemplary embodiment of the semiconductor device 102 according to some embodiments. In this embodiment, on the left side, a single p-type epitaxial structure 138 is supported by two adjacent second fins 130. Similarly, a single n-type epitaxial structure 128 is supported by two adjacent first fins 120. On the right side, a single p-type epitaxial structure 138 is supported by one second fin 130, and a single n-type epitaxial structure 128 is supported by one first fin 120. Generally, any number of fins can be used to support the epitaxial structures as needed. Hybrid fins 140 having corners and bases are located between each n-type epitaxial feature 128 and p-type epitaxial feature 138.

[0103] Figure 3FIG. 300 is a flowchart depicting a method for fabricating a semiconductor device according to some embodiments. Some steps of the method are also illustrated in Figures 4 to 16 These figures provide different perspectives for better understanding. Although the method steps may be discussed below in terms of a single or multiple fins or structures, this discussion should also be interpreted broadly as applying to multiple or single fins or structures, respectively.

[0104] It should be noted that some conventional steps are not explicitly described in the following discussion. For example, forming a pattern / structure in a given layer may be accomplished by applying a photoresist layer, patterning the photoresist layer, developing the photoresist layer, and then etching.

[0105] Generally, a photoresist layer may be applied, for example, by spin coating, or by spraying, roll coating, dip coating, or extrusion coating. Typically, in spin coating, the substrate is placed on a rotating platen, which may include a vacuum chuck that holds the substrate in the platen. Then, the photoresist composition is applied to the center of the substrate. Next, the speed of the rotating platen is increased to spread the resist uniformly from the center of the substrate to the periphery of the substrate. Then, the rotational speed of the platen is fixed, which can control the thickness of the final photoresist layer.

[0106] Next, the photoresist composition is baked or cured to remove the solvent and harden the photoresist layer. In some specific embodiments, the baking is performed at a temperature of about 90 °C to about 110 °C. The baking may be performed using a hot plate or an oven or similar equipment. Thus, a photoresist layer is formed on the substrate.

[0107] Next, the photoresist layer is patterned by exposure to radiation. The radiation may be any light wavelength carrying the desired mask pattern. In a specific embodiment, EUV light having a wavelength of about 13.5 nm is used for patterning because this allows for obtaining smaller feature sizes. This results in some portions of the photoresist layer being exposed to the radiation, and some portions of the photoresist not being exposed to the radiation. Such exposure causes some portions of the photoresist to become soluble in the developer, and other portions of the photoresist to remain insoluble in the developer.

[0108] An additional photoresist baking step (post-exposure bake, or PEB) may occur after exposure to radiation. For example, this may help release acid leaving groups (ALGs) or other molecules that are significant in chemically amplified photoresists.

[0109] Next, the photoresist layer is developed using a developer. The developer can be an aqueous solution or an organic solution. During the development step, the soluble portion of the photoresist layer dissolves and is washed away, leaving a photoresist pattern. An example of a common developer is an aqueous solution of tetramethylammonium hydroxide (TMAH). Other developers can include 2-heptanone, n-butyl acetate, isoamyl acetate, cyclohexanone, 5-methyl-2-hexanone, methyl-2-hydroxyisobutyrate, ethyl lactate, or propylene glycol monomethyl ether acetate, n-amyl acetate, n-butyl propionate, n-hexyl acetate, n-butyl butyrate, isobutyl butyrate, 2,5-dimethyl-4-hexanone, 2,6-dimethyl-4-heptanone, isopropyl isobutyrate, or isobutyl propionate. Generally, any suitable developer can be used. Sometimes, a post-development bake or "hard bake" can be performed to stabilize the photoresist pattern after development, so as to obtain optimal performance in subsequent steps.

[0110] Next, a portion of the layer underlying the patterned photoresist layer is now exposed. Etching transfers the photoresist pattern to the layer underlying the patterned photoresist layer.

[0111] Generally, any etching step used herein can be performed using a wet etching, dry etching, or plasma etching process, such as reactive ion etching (RIE) or inductively coupled plasma (ICP), or a combination thereof, as appropriate. The etching can be anisotropic. Depending on the material, the etchant can include carbon tetrafluoride (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), trifluoromethane (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), trifluoromethane (CHF3), fluorocarbon, nitrogen (N2), hydrogen (H2), oxygen (O2), argon (Ar), xenon (Xe), xenon difluoride (XeF2), helium (He), carbon monoxide (CO), carbon dioxide (CO2), fluorine (F2), chlorine (Cl2), oxygen (O2), hydrogen bromide (HBr), hydrofluoric acid (HF), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), boron trichloride (BCl3), ammonia (NH3), bromine (Br2), nitrogen trifluoride (NF3), etc., or a combination thereof in various ratios. For example, hydrofluoric acid and ammonium fluoride can be used for wet etching of silicon dioxide. Alternatively, various mixtures of CHF3, O2, CF4, and / or H2 can be used for dry etching of silicon dioxide.

[0112] Next, Figure 4 shown at Figure 3 the starting state before the method steps of. As shown here, the substrate 110 has a plurality of semiconductor fins formed thereon. The substrate and the fins are made of the same material. AtFigure 1A Thereafter, a first fin 120 and two second fins 130, also referred to as a center fin and two outer fins, are illustrated herein. Grooves 172 are present between each pair of adjacent fins.

[0113] The substrate is typically a wafer made of semiconductor material. Such materials may include silicon, for example, in the form of crystalline Si or polycrystalline Si. In alternative embodiments, the substrate may be made of other elemental semiconductors such as germanium, or may include compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium carbide, gallium phosphide, indium arsenide (InAs), indium phosphide (InP), silicon germanium, silicon carbide germanium, gallium arsenide phosphide, or gallium indium phosphide. In a particular embodiment, the wafer substrate is silicon.

[0114] The substrate is then shaped to form fins 120, 130. Typically, one or more hard mask layers are applied to the substrate. A mandrel is then formed on the hard mask layer above the substrate. This can be done by depositing a mandrel material layer, forming a photoresist layer on the mandrel material layer, exposing the photoresist layer to radiation and developing the photoresist layer to form a mandrel pattern, and then etching the mandrel material layer to form a mandrel. If desired, the mandrel is used as a mask, and the hard mask layer and the substrate are etched through to form fins. Alternatively, in a process called self-aligned double patterning (SADP), spacers are formed on the sidewalls of the mandrel, and then the mandrel is removed. The spacers are then used as a mask, and the hard mask layer and the substrate are etched through to form fins. Self-aligned quadruple patterning (SAQP) is a similar process and can also be used to form fins.

[0115] Next, in Figure 3 step 305, as Figure 5 shown, a dielectric layer 150 is formed on fins 120, 130 and substrate 110. In a typical embodiment, the dielectric layer is formed of silicon dioxide (SiO2), which has a dielectric constant of 3.9. However, any suitable dielectric material can be used. The dielectric layer can be formed by thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), oxidation, or other suitable deposition techniques or growth techniques. The dielectric layer conforms to the surfaces of the fins and the substrate, and the grooves 172 still exist between the fins.

[0116] Next, in Figure 3 step 310 and as Figure 6As shown, a second dielectric material is deposited into the trenches to form a second dielectric layer 174. The dielectric constant of the second dielectric material is greater than the dielectric coefficient of the dielectric layer 150. In some specific embodiments, the second dielectric material has a dielectric constant greater than 3.9 (i.e., the dielectric coefficient of SiO2). Examples of suitable materials may include silicon carbonitride (SiCN, k = 4 to 7.0), aluminum oxide (Al2O3, k = 8 to 10), silicon nitride (SiN, k ~ 8 to 10), hafnium silicate (HfSi x O y , k ~ 11) or zirconium silicate (ZrSi x O y , k ~ 13). As shown herein, the second dielectric material fills the trenches and forms a layer on top of the substrate and above the fins 120, 130. However, it is not necessary to form such a layer above the fins.

[0117] Next, in Figure 3 optional step 315 and as Figure 7 shown, the substrate is planarized to remove the second dielectric layer from above the fins 120, 130. Planarization can be performed, for example, using a chemical mechanical polishing (CMP) process. The hybrid fins 140 are thus formed by the second dielectric layer between the fins 120, 130.

[0118] Generally, CMP is performed using a rotating platen with an attached polishing pad. The substrate is attached to a rotating carrier. A slurry or solution containing various chemicals and abrasives is dispensed onto the polishing pad or the wafer substrate. During polishing, both the polishing pad and the carrier rotate, which has a mechanical and chemical effect on the surface of the wafer substrate, thereby removing the unwanted material and forming a highly planar surface on the wafer. A post-CMP cleaning step is then performed using a rotating scrubber brush and a cleaning solution to clean one or both sides of the wafer substrate.

[0119] Next, in Figure 3 step 320, the hybrid fins 140 are etched back so that they are not higher than the fins 120, 130, or in other words, the height of the hybrid fins is reduced. In Figure 3 step 325, the portion of the dielectric layer 150 between the hybrid fins 140 and the fins 120, 130 is etched away. The resulting structure is shown in Figure 8 . Each hybrid fin 140 is on the dielectric layer 150. In this view, a structure is formed on the substrate, which includes a first fin 120, a second fin 130, and a hybrid fin 140 located between the first fin and the second fin.

[0120] Next, in Figure 3In step 330, the first fin 120 and the hybrid fin 140 are etched to change the shape of the hybrid fin 140. The resulting structure is shown in Figure 9 . In this illustration, two hybrid fins 140 on each side of the first fin 120 are etched to form recesses in each hybrid fin. The hybrid fin 140 can now be described as having a base 142 and corners 146. The corners 146 extend upward from the base 142 on the side of the base closer to the second fin 140. After etching, the first fin 120 and the base 142 extend to the same level (indicated by reference numeral 180). The height of the first fin is reduced compared to before this etching step. After this step, the height 135 of the second fin 130 is greater than the height 125 of the first fin 120.

[0121] Next, in Figure 3 step 335 and as shown in Figure 10 , an n-type epitaxial structure 128 is formed on the first fin 120. This can be accomplished by depositing multiple crystal layers. The epitaxial structure can grow vertically and / or horizontally to form facets that can correspond to the crystal planes of the material used for the substrate. Suitable epitaxial growth methods can include CVD, ALD, or molecular beam epitaxy (MBE). Suitable materials for the n-type epitaxial structure can include Si, SiP, SiC, or SiCP. As discussed with respect to Figure 2B , this epitaxial structure can be formed on any number of adjacent fins as needed.

[0122] Next, in Figure 3 step 340 and as shown in Figure 11 , the second fin 130 is recessed by etching. It can be etched to the same level or height as the first fin 120 was etched to (see Figure 9 ), which is a level below the corners 146 of the hybrid fin 140.

[0123] Then, in Figure 3 step 355 and as shown in Figure 12 , a p-type epitaxial structure 138 is formed on each second fin 130. This can be done in the same manner as previously described for the n-type epitaxial structure. Suitable materials for the p-type epitaxial structure can include Si, SiGe, or Ge, which can be doped with boron. Again, this epitaxial structure can be formed on any number of adjacent fins as needed.

[0124] It should be noted that one reason for shaping the hybrid fin to include a lower height on the side closer to the n-type epitaxial structure 128 is to allow the n-type epitaxial tissue 128 to have a larger volume than the p-type epitaxial structure 138. This improves the electrical performance of these semiconductor devices. The height 129 of the n-type epitaxial structure 128 and the height 139 of the p-type epitaxial structure 138 can independently be from about 15 nm to about 25 nm.

[0125] Next, in Figure 3 step 360 of Figure 13 and as shown in , a third dielectric material is deposited. The third dielectric material desirably fills any gaps 182 (marked by dashed lines) between the hybrid fin 140 and the second fin 130 / p-type epitaxial feature 138, and can thus also be regarded as a gap-fill layer or an etch-stop layer 152. As shown here, the third dielectric material also fills the gap 182 between the hybrid fin 140 and the first fin 120 / n-type epitaxial feature 128, also covers the base 142 of the hybrid fin 140, and also forms a thin layer on the epitaxial feature itself, but this is not necessary. Suitable dielectric materials have been described previously. In a particular embodiment, the third dielectric material is a material different from the hybrid fin 140. In a further particular embodiment, the third dielectric material is silicon nitride (SiN). It should be noted that if there is no first fin 120 / n-type epitaxial feature 128 between a given second fin 130 / p-type epitaxial feature 138 and the hybrid fin 140, then that second fin 130 / p-type epitaxial feature is regarded as being close to the hybrid fin 140.

[0126] It should be noted that the width 185 between the hybrid fin base 142 and the second fin 130 is greater than the width 187 between the hybrid fin corner 146 and the p-type epitaxial structure 138. The width 187 depends on the height of the hybrid fin corner 146, and if the corner is too high, it is difficult to fill the gap with the third dielectric material. Controlling the height of the corner allows the gap to be completely filled.

[0127] In Figure 3 optional step 365 of Figure 14 and as shown in , the third dielectric material is etched as needed to expose the n-type epitaxial feature 128 and the p-type epitaxial feature 138.

[0128] Then, in Figure 3 step 370 of Figure 15 and as shown in , a capping dielectric layer 154 is deposited on the n-type epitaxial feature 128 and the p-type epitaxial feature 138. The capping dielectric layer 154 is made of a suitable dielectric material. Other high-k dielectric materials that can be used in this layer in addition to those described previously can include hafnium dioxide (HfO2, k~25), zirconium dioxide (ZrO2, k = 22 to 47, depending on the crystal structure / amorphous), hafnium oxynitride (HfOx N y , where k = 14 to 21) or zirconium oxynitride (ZrO x N y , where k ~ 27).

[0129] Next, in Figure 3 step 375 of, the vias 155 are etched through the capping dielectric layer 154 to reach each n-type epitaxial feature 128 and p-type epitaxial feature 138. The resulting structure is shown in Figure 16 .

[0130] Next, in Figure 3 step 380 of, an electrical contact resistance reducing layer is applied to the vias. This contact resistance reducing layer reduces the electrical contact resistance that may occur. Examples of suitable materials may include Ti, Co, In, Ga, or alloys thereof, but other materials are within the scope of this disclosure. In a particular embodiment, the electrical contact resistance reducing layer is formed of Ti, Co, or an alloy thereof. This layer can be applied by ALD, sputtering, or other suitable processes. The resulting structure is shown in Figure 17 .

[0131] Finally, in Figure 3 step 385 of, the vias are filled with a conductive material that forms the plugs 158. The combination of the contact resistance reducing layer 157 and the plugs 158 can be regarded as the metal contacts 156. The contact resistance reducing layer 157 separates the epitaxial features 128, 138 from the plugs 158. In a particular embodiment, the plugs 158 are formed of a metal such as aluminum (Al), tungsten (W), Cu, Au, Fe, Ru, Ir, Pt, Co, Rh, Pd, Ti, Ta, or an alloy thereof, but other materials are within the scope of this disclosure. In a particular embodiment, the plugs are formed of tungsten (W). The plugs can be formed by PVD, CVD, or other processes such as sputtering. The resulting structure is shown in Figures 1A to 1C .

[0132] Figure 2A and Figure 2B The second exemplary embodiment of is made in a substantially similar manner to the manner described in Figure 3 and Figures 4 to 6 . The main difference is that two adjacent fins are designated as the first fin or the central fin 120, and n-type epitaxial features 128 will be formed on the first fin or the central fin. In addition, in the etching step 330 for forming the corners 146, due to the corners 146 being located in the central region of the etching rather than on the edge, the hybrid fins 170 located between two n-type epitaxial structures 128 do not have corners and are substantially only reduced in height.

[0133] The above discussion and Figures 4 to 6The illustration is about the formation of the n-type epitaxial feature 128 and the p-type epitaxial feature 138, but does not describe the formation of other features of the semiconductor device shown in the X-axis view of Figure 1C the semiconductor device.

[0134] Now referring to Figure 1C and Figure 3 , the gate oxide layer 160 and the gate electrode 162 are typically deposited after the second fin 130 is recessed in step 340 and before the gap filling in step 360. Their deposition and formation are indicated in Figure 3 step 345 of

[0135] The gate oxide layer can be any dielectric material, such as silicon dioxide, hafnium silicate, zirconium silicate, hafnium dioxide, or zirconium dioxide. The gate oxide layer can be formed, for example, by thermal oxidation at a temperature of about 850 °C to about 950 °C in the presence of water or oxygen (O2). As another example, the gate oxide layer can be formed by a chemical vapor deposition (CVD) process, such as using O2 and silane (SiH4) or dichlorosilane (SiH2Cl2), or by using tetraethyl orthosilicate (TEOS) at a high temperature above about 600 °C. As another example, the gate oxide layer can be formed by decomposing TEOS at a temperature of about 600 °C to about 650 °C, or by plasma-enhanced CVD at a lower temperature.

[0136] The gate electrode can be any conductive material as previously described. The gate electrode can be any conductive material, such as aluminum, polysilicon (doped or undoped), tungsten, metal silicides such as TiSi or MoSi2 or TaSi or WSi2, or conductive metals or alloys such as TiN, Pt, Co, Rh, Pd, Ti, Ta, TaN, Nb, WN, or WN / RuO2. The gate electrode can be formed by PVD or CVD or other processes such as sputtering.

[0137] In optional step 350, a gate spacer 166 is formed near the gate electrode 162. The gate spacer acts as an electrical insulator and can be made of any suitable dielectric material, such as silicon dioxide (which can be doped with fluorine or carbon). The gate spacer can be formed by a deposition process (such as PVD or CVD) over the entire surface, followed by applying a patterned mask and etching to remove the material from the non-desired locations.

[0138] During steps 375 and 380, vias / metal contacts 164 leading to the gate electrode 162, and vias and metal contacts 156 for the n-type epitaxial feature 128 and the p-type epitaxial feature 138 can also be formed.

[0139] The resulting semiconductor device can be used in a variety of applications. For example, it can be used as an inverter, which is used in applications such as ring oscillators and static random access memories (SRAMs). A ring oscillator is composed of an odd number of inverters in a ring, and its output oscillates between two voltage levels. The inverters are connected in series with each other, and the output of the last inverter is fed back to the first inverter. A ring oscillator can be used to generate a voltage or current signal with a specific frequency, which is useful for computational processes in synchronous digital systems; or can be used as part of a hardware random number generator; or to measure the effects of voltage and temperature on the wafer. In an SRAM, a pair of cross-coupled inverters is used to store a bit.

[0140] The methods and resulting structures of the present disclosure have several advantages. First, since the hybrid fins are shaped to have corners on a base with a reduced height, additional space is created, allowing the volume of the n-type epitaxial structure to be increased. At the same time, the insulating properties of the hybrid fins are maintained. This improves electrical performance and reduces capacitance. In addition, the vias / metal contacts ideally only contact the n-type epitaxial structure or the p-type epitaxial structure. However, at the smaller dimensions currently used to form integrated circuits, the critical dimension (CD) can be such that the vias / metal contacts shift to one side of the epitaxial structure. It is not expected that metal material is deposited between the hybrid fins and the epitaxial structure. The reduced height of the hybrid fins allows the gap-fill / etch-stop material to more easily fill the volume between the hybrid fins and the epitaxial structure, preventing the metal material from entering this volume. This reduces or eliminates leakage paths that may form when unwanted shifting of the metal contacts occurs.

[0141] Accordingly, some aspects of the present disclosure relate to a method of fabricating a semiconductor device. A structure including a first fin, a second fin, and a hybrid fin located between the first fin and the second fin is formed on a substrate. The first fin and the hybrid fin are then etched such that the hybrid fin includes a base and a corner extending from the base on a side closer to the second fin.

[0142] In some embodiments, the corners of the hybrid fin have a height of from about 5 to about 10 nanometers. In some embodiments, the base of the hybrid fin has a height of from about 20 to about 30 nanometers. In some embodiments, the corners of the hybrid fin have a width of from about 3 to about 8 nanometers. In some embodiments, the base of the hybrid fin has a width of from about 10 to about 20 nanometers. In some embodiments, the height of the second fin is approximately equal to the height of the base of the hybrid fin. In some embodiments, the first fin is etched simultaneously with the hybrid fin. In some embodiments, the first fin and the second fin are formed from a substrate; and the hybrid fin is formed from a dielectric material having a dielectric constant greater than 3.9. In some embodiments, the method of fabricating a semiconductor device further comprises the steps of: forming an n-type epitaxial feature on the first fin; forming a p-type epitaxial feature on the second fin; and depositing a gap-fill material to fill a plurality of gaps between the hybrid fin and the second fin. In some embodiments, the corners of the hybrid fin extend up to about half the height of the p-type epitaxial feature. In some embodiments, the ratio of the height of the p-type epitaxial feature to the height of the corners of the hybrid fin is from about 2:1 to about 3:1. In some embodiments, the volume of the n-type epitaxial feature is greater than the volume of the p-type epitaxial feature. In some embodiments, the method of fabricating a semiconductor device further comprises the steps of: depositing a capping dielectric layer over the n-type epitaxial feature and the p-type epitaxial feature; and forming a plurality of metal contacts through the capping dielectric layer to the n-type epitaxial feature and the p-type epitaxial feature. In some embodiments, each metal contact comprises an electrical contact resistance reducing layer and a metal plug.

[0143] In various embodiments, there is also disclosed a semiconductor device including a substrate, at least one first fin, at least one second fin, and a hybrid fin. The at least one first fin is on the substrate and supports an n-type epitaxial feature. The at least one second fin is also on the substrate and supports a p-type epitaxial feature. The hybrid fin is on the substrate between the at least one first fin and the at least one second fin. The hybrid fin includes a base and corners extending upward from the base on a side proximate to the at least one second fin.

[0144] In some embodiments, the semiconductor device further includes a gap-fill material between the hybrid fin and the at least one second fin. In some embodiments, the semiconductor device further includes a capping dielectric layer over the n-type epitaxial feature and the p-type epitaxial feature; and a plurality of metal contacts through the capping dielectric layer to the n-type epitaxial feature and the p-type epitaxial feature. In some embodiments, the corners of the hybrid fin extend up to about half the height of the p-type epitaxial feature.

[0145] This document also discloses a method of fabricating a semiconductor device. A structure is formed on a substrate, the substrate including at least one central fin between two hybrid fins and two outer fins on sides of the two hybrid fins opposite to the at least one central fin. Then, the at least one central fin and the two hybrid fins are etched such that each hybrid fin includes a base and a corner extending from the base on a side close to the outer fin. An n-type epitaxial feature is formed on the at least one central fin. A p-type epitaxial feature is formed on each of the two outer fins. A gap filling material is deposited to fill a plurality of gaps between each hybrid fin and a second fin close to each hybrid fin. Then, metal contacts are formed to the n-type epitaxial feature and the p-type epitaxial feature. In a particular embodiment, there are two central fins.

[0146] This document also discloses another semiconductor device, which includes a substrate, at least one first fin, at least one second fin, and a hybrid fin. The at least one first fin is on the substrate and supports an n-type epitaxial feature. The at least one second fin is also on the substrate and supports a p-type epitaxial feature. The hybrid fin is on the substrate between the at least one first fin and the at least one second fin. The hybrid fin has a base and a corner, where the hybrid fin is located between the n-type epitaxial feature and the p-type epitaxial feature.

[0147] This document also discloses yet another semiconductor device, which includes a substrate, at least one first fin, at least one second fin, and a hybrid fin. The at least one first fin is on the substrate and supports an n-type epitaxial feature. The at least one second fin is also on the substrate and supports a p-type epitaxial feature. The hybrid fin is on the substrate between the at least one first fin and the at least one second fin. The hybrid fin includes a base and a corner, where the width of the corner is less than the width of the base.

[0148] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that, Comprising: At least one first fin on a substrate, supporting an n-type epitaxial feature; At least one second fin on the substrate, supporting a p-type epitaxial feature; And A hybrid fin located between the at least one first fin and the at least one second fin, the hybrid fin comprising a base and a corner extending upward from the base on a side closer to the at least one second fin.

2. The semiconductor device according to claim 1, wherein Further comprising a gap filling material between the hybrid fin and the at least one second fin.

3. The semiconductor device according to claim 1, wherein, Further comprising: A capping dielectric layer over the n-type epitaxial feature and the p-type epitaxial feature; And A plurality of metal contacts passing through the capping dielectric layer to the n-type epitaxial feature and the p-type epitaxial feature.

4. The semiconductor device according to claim 1, wherein Wherein the corner of the hybrid fin extends up to about half of the height of the p-type epitaxial feature.

5. A semiconductor device, characterized in that, Comprising: At least one first fin on a substrate, supporting an n-type epitaxial feature; At least one second fin on the substrate, supporting a p-type epitaxial feature; And A hybrid fin having a base and a corner, wherein the hybrid fin is located between the n-type epitaxial feature and the p-type epitaxial feature.

6. The semiconductor device according to claim 5, characterized in that, Further comprising a gap filling material between the hybrid fin and the at least one second fin.

7. The semiconductor device according to claim 5, wherein Further comprising: A capping dielectric layer over the n-type epitaxial feature and the p-type epitaxial feature; And A plurality of metal contacts passing through the capping dielectric layer to the n-type epitaxial feature and the p-type epitaxial feature.

8. The semiconductor device according to claim 5, wherein, Wherein the corner of the hybrid fin extends up to about half of the height of the p-type epitaxial feature.

9. A semiconductor device, characterized in that, Comprising: At least one first fin on a substrate, supporting an n-type epitaxial feature; At least one second fin on the substrate, supporting a p-type epitaxial feature; And A hybrid fin located between the at least one first fin and the at least one second fin, the hybrid fin comprising a base and a corner, wherein the width of the corner is less than the width of the base.

10. The semiconductor device according to claim 9, characterized in that, Further comprising a gap filling material between the hybrid fin and the at least one second fin.

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