Substrate and semiconductor device

Abstract

The utility model provides a substrate and a semiconductor device. The substrate comprises a base layer; the thickness of the top semiconductor layer is smaller than that of the substrate layer; the supporting dielectric layer and the stress buffer layer are arranged between the substrate layer and the top semiconductor layer in a stacked mode, the substrate layer and the top semiconductor layer are connected through the supporting dielectric layer and the stress buffer layer, and the rigidity of the supporting dielectric layer is larger than that of the stress buffer layer. According to the scheme, the supporting dielectric layer and the stress buffer layer are formed between the base layer and the top semiconductor layer, the stress buffer layer is used for relieving stress, the supporting dielectric layer can effectively improve the hardness and rigidity of the substrate, and then the bending degree value of the substrate is improved; meanwhile, the heat conductivity coefficient of the supporting dielectric layer and / or the stress buffer layer is larger than that of silicon oxide, and the heat dissipation efficiency of the substrate can be effectively improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a substrate and a semiconductor device. Background Art

[0002] Silicon-On-Insulator (SOI) technology introduces an insulating layer between the bottom silicon layer and the top silicon layer, and active components are formed in the top silicon layer. When a semiconductor film layer is formed on the insulating layer of the SOI substrate, due to the formation of the insulating layer, device isolation of components in the integrated circuit can be achieved, and the parasitic latch-up effect in the bulk silicon complementary metal oxide semiconductor (CMOS) circuit can be completely eliminated. At the same time, the integrated circuit using the SOI substrate process also has the advantages of small parasitic capacitance, high integration density, high speed, simple process, small short-channel effect, and being suitable for low-voltage and low-power circuits.

[0003] The heat generated by the active components in the top silicon layer during the current conduction process will be transferred downward. However, in the related art, the insulating layer of the SOI substrate generally uses a silicon oxide layer, and the thermal conductivity of silicon oxide is very poor, resulting in the heat of the top silicon layer not being effectively released, and further leading to poor heat dissipation performance of the substrate.

[0004] At the same time, the bow value of the SOI substrate is poor, and the difference in the bow value between the center and the edge of the substrate is large, which will affect the morphology of each film layer formed in the subsequent process, and the process monitoring of each film layer is inaccurate, thereby increasing the process time and cost. Summary of the Utility Model

[0005] A series of simplified concepts are introduced in the Summary of the Utility Model section, which will be further described in detail in the Detailed Implementation section. The Summary of the Utility Model section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the protection scope of the claimed technical solution.

[0006] To at least partially solve the above technical problems, on the one hand, this application provides a substrate, including:

[0007] A base layer;

[0008] A top semiconductor layer, the thickness of the top semiconductor layer being less than the thickness of the base layer;

[0009] A support medium layer and a stress buffer layer are stacked between the base layer and the top semiconductor layer and connect the base layer and the top semiconductor layer. Among them, the stiffness of the support medium layer is greater than that of the stress buffer layer, and the thermal conductivity of the support medium layer and / or the stress buffer layer is greater than that of silicon oxide.

[0010] Exemplarily, the support medium layer includes a boron nitride layer.

[0011] Exemplarily, the stress buffer layer includes an aluminum nitride layer.

[0012] Exemplarily, the support medium layer includes a first support medium layer, and the stress buffer layer includes a first stress buffer layer, where the first stress buffer layer is located between the first support medium layer and the base layer.

[0013] Exemplarily, the stress buffer layer further includes a second stress buffer layer, and the second stress buffer layer is located between the first support medium layer and the top semiconductor layer.

[0014] Exemplarily, a first trap-rich layer is further included between the first stress buffer layer and the base layer.

[0015] Exemplarily, a second trap-rich layer is further included between the second stress buffer layer and the top semiconductor layer.

[0016] Exemplarily, the support medium layer further includes a second support medium layer, and the second support medium layer is located between the second stress buffer layer and the top semiconductor layer.

[0017] Exemplarily, the base layer includes a silicon layer or an SiC layer, and the top semiconductor layer includes a silicon layer or an SiC layer.

[0018] On the other hand, the present application further provides a semiconductor device, and the semiconductor device includes the above-mentioned substrate.

[0019] In the substrate and the semiconductor device of the present application, a support medium layer and a stress buffer layer are formed between the base layer and the top semiconductor layer. The stress buffer layer is used to relieve stress, and the support medium layer can effectively improve the hardness and stiffness of the substrate, thereby improving the bending value of the substrate. At the same time, the thermal conductivity of the support medium layer and / or the stress buffer layer is greater than that of silicon oxide, which can effectively improve the heat dissipation efficiency of the substrate. Description of the Drawings

[0020] The following drawings of the present application are used as a part of the present application to understand the present application. The embodiments and descriptions of the present application are shown in the drawings to explain the principles of the present application.

[0021] In the drawings:

[0022] Figure 1 Shows a cross-sectional schematic view of a substrate according to an exemplary embodiment of the present application;

[0023] Figures 2A - 2E Shows a cross-sectional schematic view of a substrate obtained by successively implementing a method for manufacturing a substrate according to an exemplary embodiment of the present application;

[0024] Figure 3 Shows a cross-sectional schematic view of a substrate according to another exemplary embodiment of the present application;

[0025] Figure 4 Shows a cross-sectional schematic view of a substrate according to another exemplary embodiment of the present application;

[0026] Figure 5 Shows a cross-sectional schematic view of a substrate according to another exemplary embodiment of the present application;

[0027] Figure 6 Shows a cross-sectional schematic view of a substrate according to another exemplary embodiment of the present application;

[0028] Figure 7 Shows a cross-sectional schematic view of a substrate according to another exemplary embodiment of the present application;

[0029] Figure 8 Shows a cross-sectional schematic view of a substrate according to another exemplary embodiment of the present application;

[0030] Figure 9 Shows a cross-sectional schematic view of a substrate according to another exemplary embodiment of the present application;

[0031] Figure 10 Shows a cross-sectional schematic view of a substrate according to another exemplary embodiment of the present application;

[0032] Figure 11 Shows a cross-sectional schematic view of a substrate according to another exemplary embodiment of the present application;

[0033] Figures 12A - 12E Shows a cross-sectional schematic view of a substrate obtained by successively implementing a method for manufacturing a substrate according to another exemplary embodiment of the present application. Detailed implementation manners

[0034] Next, the present application will be described more fully with reference to the accompanying drawings, in which embodiments of the present application are shown. However, the present application can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. Like reference numerals throughout the drawings denote like elements.

[0035] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, a first element, component, region, layer or portion discussed below may be denoted as a second element, component, region, layer or portion without departing from the teachings of the present application.

[0036] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0037] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0038] Embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application. As such, variations from the shapes as illustrated, for example due to manufacturing techniques and / or tolerances, are to be expected. Accordingly, embodiments of the present application should not be limited to the particular shapes of regions shown herein but should include shape deviations resulting, for example, from manufacturing. For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions shown in the figures are substantially schematic in nature, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to limit the scope of the present application.

[0039] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It will also be understood that terms such as those defined in commonly used dictionaries should be understood to have a meaning that is consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0040] To fully understand the present application, detailed structures will be set forth in the following description in order to illustrate the technical solutions proposed by the present application. Preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may have other embodiments.

[0041] Accordingly, in view of the existence of the foregoing technical problems, the present application provides a substrate, comprising:

[0042] A base layer;

[0043] A top semiconductor layer, the thickness of the top semiconductor layer being less than the thickness of the base layer;

[0044] A support dielectric layer and a stress buffer layer are stacked between the base layer and the top semiconductor layer and connect the base layer and the top semiconductor layer. Among them, the stiffness of the support dielectric layer is greater than that of the stress buffer layer.

[0045] For the substrate of the present application, a support dielectric layer and a stress buffer layer are formed between the base layer and the top semiconductor layer. The stress buffer layer is used to relieve stress. The support dielectric layer can effectively improve the hardness and stiffness of the substrate, thereby improving the bending value of the substrate. At the same time, the support dielectric layer and the stress buffer layer can also effectively improve the heat dissipation efficiency of the substrate.

[0046] Example 1

[0047] Next, refer to Figure 1 、 Figure 2E 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 and Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 and Figure 12E to describe the substrate in the embodiments of the present application.

[0048] In one example, the substrate of the present application includes a base layer, a top semiconductor layer, a support dielectric layer, and a stress buffer layer, where: the thickness of the top semiconductor layer is less than that of the base layer. The top semiconductor layer serves as the functional layer of the substrate, and active components are formed on the side where the top semiconductor layer is located. The support dielectric layer and the stress buffer layer are stacked between the base layer and the top semiconductor layer and connect the base layer and the top semiconductor layer. Among them, the stiffness of the support dielectric layer is greater than that of the stress buffer layer, and the thermal conductivity coefficient of the support dielectric layer and / or the stress buffer layer is greater than that of silicon dioxide.

[0049] In one example, the substrate of the present application is a SOI substrate, where the support dielectric layer and the stress buffer layer serve as the composite buried layer of the SOI substrate. Exemplarily, the top semiconductor layer includes a silicon layer or a SiC layer, and the base layer includes a silicon layer or a SiC layer, where the SiC layer has better heat dissipation performance.

[0050] In one example, the support dielectric layer has high stiffness and hardness, which can effectively improve the overall stiffness and hardness of the substrate, making the substrate not easily bend, thereby improving the bending degree value of the substrate. Among them, the stress buffer layer plays a role in relieving stress; at the same time, the support dielectric layer and the stress buffer layer also have high thermal conductivity, which can effectively improve the heat dissipation efficiency of the substrate. Exemplarily, the support dielectric layer includes a boron nitride layer (this boron nitride layer can include various forms of boron nitride, such as cubic boron nitride C-BN, wurtzite boron nitride W-BN, etc.), and the stress buffer layer includes an aluminum nitride layer. Among them, the boron nitride material has high stiffness and hardness (the hardness of the boron nitride material is about 6 times that of single-crystalline silicon, and the stiffness is about 9 times that of single-crystalline silicon), which can effectively improve the overall stiffness and hardness of the substrate; and both the boron nitride material and the aluminum nitride material have high thermal conductivity (the thermal conductivity is about 200-300 times that of silicon oxide), which can effectively improve the heat dissipation efficiency of the substrate.

[0051] In one example, as Figure 1 shown, the support dielectric layer includes a first support dielectric layer 131, and the stress buffer layer includes a first stress buffer layer 141. Among them, the first stress buffer layer 141 is located between the first support dielectric layer 131 and the base layer 110, and the first support dielectric layer 131 and the first stress buffer layer 141 connect the base layer 110 and the top semiconductor layer 120. Exemplarily, the first stress buffer layer 141 is used to relieve the stress between the first support dielectric layer 131 and the base layer 110.

[0052] In one example, as Figure 2E shown, the stress buffer layer further includes a second stress buffer layer 142, and the second stress buffer layer 142 is located between the first support dielectric layer 131 and the top semiconductor layer 120. Exemplarily, the second stress buffer layer 142 is used to relieve the stress between the first support dielectric layer 131 and the top semiconductor layer 120.

[0053] In one example, as Figure 3As shown, the substrate of the present application further includes a first trap-rich layer 151 located between the first stress buffer layer 141 and the base layer 110. Exemplarily, the first trap-rich layer 151 can be formed by an ion implantation process or an electron beam irradiation process. For example, polysilicon is first deposited, and then the polysilicon layer is subjected to ion implantation or electron beam irradiation (for example, using an electron beam gun to irradiate high-energy electron beams onto the polysilicon surface) to form defects in the polysilicon, thereby forming the first trap-rich layer 151. Among them, in the ion implantation process, appropriate ions (such as oxygen, protons, etc.) and energy should be selected for ion implantation. Exemplarily, since defects can capture and release charges, electrons and holes will be trapped in the defects, making the first trap-rich layer 151 have a relatively high resistance, which can block the diffusion of ions in the first stress buffer layer 141 to the base layer 110 (taking the first stress buffer layer 141 as an aluminum nitride layer as an example, the first trap-rich layer 151 is used to block the diffusion of aluminum ions in the first stress buffer layer 141 to the base layer 110), thereby isolating the leakage current effect of the first stress buffer layer 141 on the base layer 110. Exemplarily, the first trap-rich layer 151 can also relieve the stress of the first support dielectric layer 131 on the base layer 110, and further relieve the overall stress of the substrate.

[0054] In one example, as Figure 4 shown, as a combined embodiment of the above examples, the substrate of the present application may include a base layer 110, a first trap-rich layer 151, a first stress buffer layer 141, a first support dielectric layer 131, a second stress buffer layer 142, and a top semiconductor layer 120 stacked from bottom to top.

[0055] In one example, as Figure 5As shown, it further includes a second trap-rich layer 152 located between the second stress buffer layer 142 and the top semiconductor layer 120. Exemplarily, the second trap-rich layer 152 can be formed by an ion implantation process or an electron beam irradiation process. For example, polysilicon is first deposited, and then the polysilicon layer is subjected to ion implantation or electron beam irradiation (for example, using an electron beam gun to irradiate a high-energy electron beam onto the polysilicon surface) to form defects in the polysilicon, thereby forming the second trap-rich layer 152. Among them, in the ion implantation process, appropriate ions (such as oxygen, protons, etc.) and energy should be selected for ion implantation. Exemplarily, since defects can capture and release charges, electrons and holes will be captured in the defects, making the second trap-rich layer 152 have a relatively high resistance, capable of blocking the diffusion of ions in the second stress buffer layer 142 to the top semiconductor layer 120 (taking the second stress buffer layer 142 as an aluminum nitride layer as an example, the second trap-rich layer 152 is used to block the diffusion of aluminum ions in the second stress buffer layer 142 to the top semiconductor layer 120), thereby isolating the leakage current effect of the second stress buffer layer 142 on the top semiconductor layer 120. Further, the second trap-rich layer 152 can isolate the leakage current effect of the second stress buffer layer 142 on the active components in the top semiconductor layer 120. Exemplarily, the second trap-rich layer 152 can also relieve the stress of the first support dielectric layer 131 on the top semiconductor layer 120, and further relieve the overall stress of the substrate.

[0056] In one example, as Figure 6 shown, as a combined embodiment of the above examples, the substrate of the present application may include a base layer 110, a first trap-rich layer 151, a first stress buffer layer 141, a first support dielectric layer 131, a second stress buffer layer 142, a second trap-rich layer 152, and a top semiconductor layer 120 that are stacked from bottom to top.

[0057] In one example, as Figure 7 shown, the support dielectric layer further includes a second support dielectric layer 132, and the second support dielectric layer 132 is located between the second stress buffer layer 142 and the top semiconductor layer 120. Exemplarily, the second support dielectric layer 132 is used to further improve the heat dissipation efficiency on the side of the top semiconductor layer 120, and further improve the overall heat dissipation performance of the substrate. Exemplarily, the first support dielectric layer 131 and the second support dielectric layer 132 can further improve the stiffness and hardness of the substrate.

[0058] In one example, as Figure 8 shown, as a combined embodiment of the above examples, the substrate of the present application may include a base layer 110, a first trap-rich layer 151, a first stress buffer layer 141, a first support dielectric layer 131, a second stress buffer layer 142, a second support dielectric layer 132, and a top semiconductor layer 120 that are stacked from bottom to top.

[0059] In one example, as Figure 9 shown, as a combined embodiment of the above examples, the substrate of the present application may include a base layer 110, a first stress buffer layer 141, a first support dielectric layer 131, a second stress buffer layer 142, a second support dielectric layer 132, a second trap-rich layer 152, and a top semiconductor layer 120 that are stacked from bottom to top.

[0060] In one example, as Figure 10 shown, as a combined embodiment of the above examples, the substrate of the present application may include a base layer 110, a first stress buffer layer 141, a first support dielectric layer 131, a second stress buffer layer 142, a second trap-rich layer 152, a second support dielectric layer 132, and a top semiconductor layer 120 that are stacked from bottom to top.

[0061] In one example, as Figure 11 shown, as a combined embodiment of the above examples, the substrate of the present application may include a base layer 110, a first trap-rich layer 151, a first stress buffer layer 141, a first support dielectric layer 131, a second stress buffer layer 142, a second support dielectric layer 132, a second trap-rich layer 152, and a top semiconductor layer 120 that are stacked from bottom to top.

[0062] In one example, as Figure 12E shown, as a combined embodiment of the above examples, the substrate of the present application may include a base layer 110, a first trap-rich layer 151, a first stress buffer layer 141, a first support dielectric layer 131, a second stress buffer layer 142, a second trap-rich layer 152, a second support dielectric layer 132, and a top semiconductor layer 120 that are stacked from bottom to top.

[0063] In summary, for the substrate of the present application, a support dielectric layer and a stress buffer layer are formed between the base layer and the top semiconductor layer. The stress buffer layer is used to relieve stress, and the support dielectric layer can effectively improve the hardness and stiffness of the substrate, thereby improving the curvature value of the substrate. At the same time, the support dielectric layer and the stress buffer layer can also effectively improve the heat dissipation efficiency of the substrate. Exemplarily, a trap-rich layer is also formed, which can prevent ions in the stress buffer layer from diffusing to the base layer and / or the top semiconductor layer, thereby isolating the leakage current influence of the stress buffer layer on the base layer and / or the top semiconductor layer.

[0064] Embodiment 2

[0065] Next, with reference to Figures 2A - 2E and Figures 12A - 12E the manufacturing process of the substrate of a specific embodiment of the present application will be described.

[0066] First, with reference to Figures 2A - 2EDescribe the manufacturing process of the substrate in a specific embodiment of the present application:

[0067] In one example, as Figure 2A shown, provide a base layer 110, and sequentially form a first stress buffer layer 141 and a first sub-supporting dielectric layer 1311 on the base layer 110. Among them, common deposition processes in the art can be used to sequentially form the first stress buffer layer 141 and the first sub-supporting dielectric layer 1311, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc. The present application does not limit this.

[0068] Next, as Figure 2B shown, provide a top semiconductor layer 120, and sequentially form a second stress buffer layer 142 and a second sub-supporting dielectric layer 1312 on the top semiconductor layer 120. Among them, common deposition processes in the art can be used to sequentially form the second stress buffer layer 142 and the second sub-supporting dielectric layer 1312, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc. The present application does not limit this.

[0069] Next, as Figure 2C shown, perform an ion implantation process on the top semiconductor layer 120 to form an ion implantation layer 160 in the top semiconductor layer 120 at a predetermined depth. The ion implantation layer 160 is spaced apart from the second stress buffer layer 142. Among them, the implanted ions in the ion implantation process include hydrogen ions.

[0070] Next, as Figure 2D shown, bond the side of the base layer 110 with the first sub-supporting dielectric layer 1311 and the side of the top semiconductor layer with the second sub-supporting dielectric layer 1312. The first sub-supporting dielectric layer 1311 and the second sub-supporting dielectric layer 1312 constitute a first supporting dielectric layer 131. Exemplarily, conventional bonding processes in the art can be used to perform the above bonding steps.

[0071] Finally, as Figure 2E shown, perform annealing treatment: first perform a first annealing treatment at a first temperature (such as 400°C - 600°C) to cause the top semiconductor layer 120 to break at the ion implantation layer 160; then, perform a second annealing treatment at a second temperature (such as 1100°C) to expel the implanted ions (such as hydrogen ions). Exemplarily, the thickness of the remaining top semiconductor layer 120 is less than the thickness of the base layer 110. Exemplarily, it further includes a step of planarizing the annealed top semiconductor layer 120, for example, performing chemical mechanical polishing (CMP, Chemical Mechanical Polishing) on the annealed top semiconductor layer 120.

[0072] Next, with reference to Figures 12A - 12E the manufacturing process of the substrate of another specific embodiment of the present application will be described:

[0073] First, as Figure 12A shown, a base layer 110 is provided, and a first trap-rich layer 151, a first stress buffer layer 141, and a first sub-supporting dielectric layer 1311 are sequentially formed on the base layer 110. Among them, common deposition processes in the art can be used to form the first stress buffer layer 141 and the first sub-supporting dielectric layer 1311, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc., and the present application does not limit this. Exemplarily, the first trap-rich layer 151 can be formed by an ion implantation process or an electron beam irradiation process. For example, polysilicon is first deposited, and then the polysilicon layer is subjected to ion implantation or electron beam irradiation (for example, using an electron beam gun to irradiate the polysilicon surface with high-energy electron beams) to form defects in the polysilicon, thereby forming the first trap-rich layer 151; among them, in the ion implantation process, appropriate ions (such as oxygen, protons, etc.) and energies should be selected for ion implantation.

[0074] Next, as Figure 12B shown, a second supporting dielectric layer 132, a second trap-rich layer 152, a second stress buffer layer 142, and a second sub-supporting dielectric layer 1312 are sequentially formed on the top semiconductor layer 120. Among them, common deposition processes in the art can be used to form the second supporting dielectric layer 132, the second stress buffer layer 142, and the second sub-supporting dielectric layer 1312, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc., and the present application does not limit this. Exemplarily, the second trap-rich layer 152 can be formed by an ion implantation process or an electron beam irradiation process. For example, polysilicon is first deposited, and then the polysilicon layer is subjected to ion implantation or electron beam irradiation (for example, using an electron beam gun to irradiate the polysilicon surface with high-energy electron beams) to form defects in the polysilicon, thereby forming the second trap-rich layer 152; among them, in the ion implantation process, appropriate ions (such as oxygen, protons, etc.) and energies should be selected for ion implantation.

[0075] Next, as Figure 12C shown, an ion implantation process is performed on the top semiconductor layer 120 to form an ion implantation layer 160 in the top semiconductor layer 120 at a predetermined depth, and the ion implantation layer 160 is spaced apart from the second supporting dielectric layer 132. Among them, the implanted ions in the ion implantation process include hydrogen ions.

[0076] Next, as Figure 12DAs shown, bond the side of the base layer 110 where the first sub-supporting dielectric layer 1311 is formed and the side of the top semiconductor layer where the second sub-supporting dielectric layer 1312 is formed. The first sub-supporting dielectric layer 1311 and the second sub-supporting dielectric layer 1312 constitute the first supporting dielectric layer 131. Exemplarily, a conventional bonding process in the art can be used to perform the above bonding step.

[0077] Finally, as Figure 12E shown, perform an annealing process: first perform a first annealing process at a first temperature (e.g., 400°C - 600°C) such that the top semiconductor layer 120 breaks at the ion implantation layer 160; then, perform a second annealing process at a second temperature (e.g., 1100°C) to expel the implanted ions (e.g., hydrogen ions). Exemplarily, the thickness of the remaining top semiconductor layer 120 is less than the thickness of the base layer 110. Exemplarily, it further includes a step of planarizing the annealed top semiconductor layer 120, for example, performing chemical mechanical polishing on the annealed top semiconductor layer 120.

[0078] The manufacturing process of the substrate in two specific embodiment modes of the present application is described above by way of example. The manufacturing process of the substrate in other embodiment modes of the present application can refer to the above steps and will not be elaborated herein.

[0079] Embodiment 3

[0080] In another embodiment of the present application, a semiconductor device is further provided. The semiconductor device includes the substrate of the foregoing embodiment. Exemplarily, the semiconductor device may further include other components, for example, active components located on the substrate, etc., which will not be elaborated herein in the present application.

[0081] The semiconductor device of the embodiment of the present application has better performance due to the use of the above substrate.

[0082] Although multiple embodiments are described herein, it should be understood that those skilled in the art can conceive of various other modifications and embodiments, and they will all fall within the spirit and scope of the concept disclosed in the present application. More particularly, various modifications and changes can be made in the arrangement and / or components of the combination arrangement of the subject matter within the scope of the present application disclosure, the drawings, and the appended claims. In addition to the modifications and changes in the components and / or arrangement, the use of alternative means is also an obvious choice for those skilled in the art.

Claims

1. A substrate, characterized in that, Comprising: Base layer; Top semiconductor layer, the thickness of the top semiconductor layer being less than the thickness of the base layer; Supporting dielectric layer and stress buffer layer, stacked between the base layer and the top semiconductor layer and connecting the base layer and the top semiconductor layer, wherein the stiffness of the supporting dielectric layer is greater than the stiffness of the stress buffer layer, and the thermal conductivity of the supporting dielectric layer and / or the stress buffer layer is greater than the thermal conductivity of silicon oxide.

2. The substrate according to claim 1, characterized in that The supporting dielectric layer includes a boron nitride layer.

3. The substrate according to claim 1, wherein The stress buffer layer includes an aluminum nitride layer.

4. The substrate according to claim 1, wherein The supporting dielectric layer includes a first supporting dielectric layer, and the stress buffer layer includes a first stress buffer layer, wherein the first stress buffer layer is located between the first supporting dielectric layer and the base layer.

5. The substrate according to claim 4, characterized in that, The stress buffer layer further includes a second stress buffer layer, and the second stress buffer layer is located between the first supporting dielectric layer and the top semiconductor layer.

6. The substrate according to claim 4, wherein It further includes a first trap-rich layer located between the first stress buffer layer and the base layer.

7. The substrate according to claim 5, characterized in that, It further includes a second trap-rich layer located between the second stress buffer layer and the top semiconductor layer.

8. The substrate according to claim 5, characterized in that The supporting dielectric layer further includes a second supporting dielectric layer, and the second supporting dielectric layer is located between the second stress buffer layer and the top semiconductor layer.

9. The substrate according to claim 1, wherein The base layer includes a silicon layer or a SiC layer, and the top semiconductor layer includes a silicon layer or a SiC layer.

10. A semiconductor device, characterized in that, The semiconductor device includes the substrate according to any one of claims 1-9.

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