Multicolor micro-display chip

Abstract

The utility model relates to a multicolor micro display chip, which comprises a mother pixel, a driving wafer and at least two pixel layers, the mother pixel comprises at least four sub-pixels, at least two sub-pixels in the mother pixel have different light emitting colors, the sub-pixels have red light emitting colors, and the sub-pixels have red light emitting colors. The number of the sub-pixels of which the light emitting color is red is not less than 50% of the number of all the sub-pixels in the mother pixel; the sub-pixels are electrically connected with the driving wafer; all the pixel layers are sequentially stacked on the driving wafer in the Z direction, at least one sub-pixel is arranged in each pixel layer, the sub-pixels in the same pixel layer have the same light emitting color, and the sub-pixels in the two adjacent pixel layers have different light emitting colors. According to the utility model, the number of the red sub-pixels is effectively increased, so that the attenuation of red light in the mother pixels can be effectively controlled, and an ideal color display effect is further ensured.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a multi-color micro-display chip. Background Art

[0002] In the field of LEDs, color displays are mainly composed of RGB three-color sub-pixels to form a mother pixel and perform color mixing with different ratios. In theory, all colors on the spectrum can be generated by matching the three primary colors of red (R), green (G), and blue (B). Our perception of a certain color of an object is determined by the physical stimulation characteristics of the external object to the human eye on the one hand, and the visual characteristics of the human eye in processing the stimulation on the other hand. However, the final calibration of color must conform to the visual laws of the human eye. The human eye retina has two types of photoreceptor cells, namely cone cells and rod cells. Rod cells are used to perceive light intensity and mainly work in low-light environments. Cone cells are used to perceive colors and mainly work in high-light environments. Cone cells are further divided into three types: blue cone cells, green cone cells, and red cone cells. In order to enable the human eye retina to better perceive the corresponding colors, when performing color mixing on an LED display screen, the brightness of the three primary colors or two primary colors needs to reach a specific ratio. For example, three-primary-color pixels with a brightness ratio of 3 (red): 6 (green): 1 (blue) or 2 (red): 7 (green): 1 (blue) can be selected to achieve white light synthesis. At this time, a color pixel layout mode such as RGB, RGGB, or RGBW can generally be selected.

[0003] However, in the field of micro-displays, such as in the field of Micro-LED displays, the chip size is greatly reduced compared to conventional LED chips. With the reduction of the size, the brightness attenuation of red pixels is relatively serious. According to the conventional color pixel layout mode, it is difficult to reach a specific brightness ratio, so that an ideal color display effect cannot be achieved, and the production and use requirements cannot be met. Summary of the Utility Model

[0004] Therefore, the technical problem to be solved by the utility model is to overcome the defect of poor color display effect of micro-display chips in the prior art.

[0005] To solve the above technical problem, the utility model provides a multi-color micro-display chip, including,

[0006] A mother pixel, the mother pixel includes at least four sub-pixels, at least two sub-pixels in the mother pixel have different light-emitting colors, and there is a sub-pixel with a light-emitting color of red, and the number of sub-pixels with a light-emitting color of red is not less than 50% of the total number of all sub-pixels in the mother pixel;

[0007] A driving wafer, all the sub-pixels are electrically connected to the driving wafer;

[0008] At least two pixel layers, and all the pixel layers are sequentially stacked in the Z direction on the driving wafer. All the sub-pixels of the mother pixel are respectively arranged in the corresponding pixel layers. At least one sub-pixel is arranged in each pixel layer. The light-emitting colors of each sub-pixel in the same pixel layer are the same, and the light-emitting colors of the sub-pixels in two adjacent pixel layers are different.

[0009] In an embodiment of the present invention, the projections of all the sub-pixels in the mother pixel on the driving wafer do not overlap.

[0010] In an embodiment of the present invention, the sub-pixels are trapezoidal or cylindrical.

[0011] In an embodiment of the present invention, an anode contact and a cathode contact are arranged on the driving wafer. Each pixel layer includes an insulating body. The sub-pixels in the pixel layer are all coated inside the insulating body. A bonding metal part is arranged on one side of each sub-pixel close to the driving wafer. The bonding metal part is electrically connected to the corresponding anode contact. An insulating passivation layer is coated outside each sub-pixel. The bonding metal part is located inside the insulating passivation layer. An opening is formed in the upper part of the insulating passivation layer. A common cathode layer is coated outside the insulating passivation layer. The sub-pixel is electrically connected through the opening and the common cathode layer. The common cathode layer is used for being electrically connected to the cathode contact.

[0012] In an embodiment of the present invention, each sub-pixel includes a P-type semiconductor layer, an active layer, and an N-type semiconductor layer that are sequentially arranged in the Z direction. The bonding metal part is arranged on one side of the P-type semiconductor layer close to the driving wafer. The N-type semiconductor layer is electrically connected to the common cathode layer through the opening.

[0013] In an embodiment of the present invention, the bonding metal parts of the sub-pixels in the upper pixel layer are electrically connected to the corresponding anode contacts through the anode connecting parts passing through the lower pixel layer.

[0014] In an embodiment of the present invention, an anode hole corresponding to the anode connecting part is formed on the interface between two adjacent pixel layers. The anode hole is filled with an anode connecting part. The top surface of the anode connecting part filled in the anode hole is lower than the interface to form a recessed part. The bonding metal part of the sub-pixel in the pixel layer is embedded into the recessed part of the corresponding anode hole in the adjacent lower pixel layer to be in electrical contact with the anode connecting part; or,

[0015] The top surface of the anode connecting part filled in the anode hole is higher than the interface to form a protruding part. The bonding metal part of the sub-pixel in the pixel layer is fitted with the protruding part of the corresponding anode connecting part in the adjacent lower pixel layer.

[0016] In an embodiment of the present utility model, it includes at least three layers of the pixel layer. In the pixel layers of the third layer and above, the bonding metal parts of the sub-pixels are electrically connected to the corresponding anode contacts by a plurality of anode connectors connected in sequence along the Z direction below. Each of the anode connectors connected in sequence along the Z direction is located in a different pixel layer. Adjacent two of the anode connectors connected in sequence along the Z direction are in direct contact with each other, or a conductive metal part is provided between adjacent two of the anode connectors.

[0017] In an embodiment of the present utility model, cathode holes are formed on the interface between adjacent two pixel layers. The cathode holes are filled with cathode connectors, and the cathode connectors are all electrically connected to the cathode contacts. The common cathode layers in the upper pixel layer are all electrically connected to the cathode contacts through the cathode connectors and cathode contacts in the lower pixel layer.

[0018] In an embodiment of the present utility model, the interface between adjacent two pixel layers is also covered with the insulating passivation layer. The upper part of the insulating passivation layer at the interface is also covered with the common cathode layer, and a metal mesh grid layer is provided on the upper part of the common cathode layer.

[0019] In an embodiment of the present utility model, the light emitted by the sub-pixels in the lower pixel layer exits through the first notch in the upper pixel layer. The first notch is formed on the metal mesh grid layer, and the length of the first notch in the X direction is greater than the top surface length of the corresponding sub-pixels in the lower layer, wherein the X direction is perpendicular to the Z direction.

[0020] In an embodiment of the present utility model, the light emitted by the sub-pixels in the lower pixel layer exits after passing through the second notch and the first notch in the upper pixel layer in sequence. The second notch is formed on the common cathode layer, and the length of the second notch in the X direction is greater than the top surface length of the corresponding sub-pixels in the lower layer.

[0021] In an embodiment of the present utility model, the anode connector in the bottom pixel layer penetrates through an auxiliary pixel and is electrically connected to the corresponding anode contact on the driving wafer; the auxiliary pixel is located in the bottom pixel layer and between two adjacent sub-pixels in the X direction, wherein the X direction is perpendicular to the Z direction.

[0022] In an embodiment of the present utility model, at least one lens is connected to the upper part of the pixel layer at the top layer, and the lens corresponds to each mother pixel, or each lens corresponds to each sub-pixel.

[0023] The above technical solutions of the present utility model have the following advantages compared with the prior art:

[0024] The multi-color microdisplay chip described in the present utility model effectively increases the number of red sub-pixels, thereby effectively controlling the attenuation of red light in the mother pixel, and further ensuring an ideal color display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to make the content of the present utility model easier to be clearly understood, the following further details the present utility model according to specific embodiments of the present utility model in conjunction with the accompanying drawings.

[0026] Figure 1 is the brightness curve diagram of a multi-color microdisplay chip of the present utility model;

[0027] Figure 2 is the first pixel distribution schematic diagram of the multi-color microdisplay chip of the present utility model;

[0028] Figure 3 is the second pixel distribution schematic diagram of the multi-color microdisplay chip of the present utility model;

[0029] Figure 4 is the comparison schematic diagram of trapezoidal sub-pixels and hemispherical sub-pixels;

[0030] Figure 5 is the overall structure diagram (top view) of the multi-color microdisplay chip of the present utility model;

[0031] Figure 6 is Figure 5 the partial enlarged view at A in

[0032] Figure 7 is the internal structure diagram of the first mother pixel of the present utility model;

[0033] Figure 8 is Figure 7 the layout schematic diagram of the bottom pixel layer in

[0034] Figure 9 is the internal structure diagram of the second mother pixel of the present utility model;

[0035] Figure 10 is the internal structure diagram of the third mother pixel of the present utility model;

[0036] Figure 11 is Figure 10 the layout schematic diagram of the bottom pixel layer in

[0037] Figure 12 is the internal structure diagram of the fourth mother pixel of the present utility model;

[0038] Figure 13 is Figure 12 the partial enlarged view at Q in

[0039] Figure 14 is the internal structure diagram of the fifth type of mother pixel of the present utility model;

[0040] Figure 15 is Figure 14 the partial enlarged view at S in

[0041] Figure 16 is the internal structure diagram of the sixth type of mother pixel of the present utility model;

[0042] Figure 17 is the third pixel distribution schematic diagram of the present utility model;

[0043] Figure 18 is the internal structure diagram of the seventh type of mother pixel of the present utility model;

[0044] Figure 19 is Figure 18 the preparation flow chart of the structure shown;

[0045] Figure 20 is the internal structure diagram of the eighth type of mother pixel of the present utility model;

[0046] Figure 21 is the partial preparation flow chart of the chip of the present utility model;

[0047] Figure 22 is Figure 7 the preparation flow chart of the structure shown;

[0048] Explanation of the reference numerals in the drawings of the specification:

[0049] 10. Mother pixel;

[0050] 20. Sub-pixel; 201. P-type ohmic contact layer; 202. P-type semiconductor layer; 203. Active layer; 204. N-type semiconductor layer; 205. N-type ohmic contact layer;

[0051] 30. Pixel layer; 301. Insulating body; 302. Bonding layer; 3021. Bonding metal part; 3022. Conductive metal part; 303. Insulating passivation layer; 3031. Opening; 304. Common cathode layer; 3041. Second notch; 3042. Auxiliary hole; 305. Metal mesh grid layer; 3051. First notch; 306. Anode hole; 3061. Depressed part; 307. Anode connecting part; 3071. Protruding part; 308. Cathode hole; 309. Cathode connecting part;

[0052] 40. Interface;

[0053] 50. Driving wafer; 501. Anode contact; 502. Cathode contact;

[0054] 60. Compound semiconductor; 601. Substrate; 70. Pixel array region; 80. Peripheral common cathode region;

[0055] 90. Auxiliary pixel; 100. Lens. Detailed implementation manner

[0056] The present utility model will be further described below in conjunction with the accompanying drawings and specific embodiments, so that those skilled in the art can better understand the present utility model and be able to implement it, but the specific embodiments cited do not limit the present utility model.

[0057] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "vertical", "upper", "lower", "top", "side", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present utility model. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present utility model, unless otherwise specified, the meaning of "a plurality" is two or more.

[0058] Refer to Figures 1 - 22 , this embodiment discloses a multi-color microdisplay chip, including a mother pixel 10, a driving wafer 50, and at least two layers of pixel layers 30;

[0059] The mother pixel 10 includes at least four sub-pixels 20. At least two sub-pixels 20 in the mother pixel 10 have different light-emitting colors, and there is a sub-pixel with a light-emitting color of red. The number of sub-pixels with a light-emitting color of red is not less than 50% of the total number of sub-pixels in the mother pixel 10;

[0060] The sub-pixels 20 are all electrically connected to the driving wafer 50. The driving wafer 50 has a driving circuit to control the light emission of the sub-pixels 20 by using the driving circuit; the driving wafer 50 can adopt a CMOS driving wafer;

[0061] At least two layers of pixel layers 30 are stacked in sequence along the Z direction on the driving wafer 50. All the sub-pixels 20 of the mother pixel 10 are respectively arranged in the corresponding pixel layers 30. At least one sub-pixel 20 is arranged in each pixel layer 30. The light-emitting colors of each sub-pixel 20 in the same pixel layer 30 are the same, and the light-emitting colors of the sub-pixels 20 in two adjacent pixel layers 30 are different.

[0062] Further, the number of sub-pixels with a red light-emitting color can be 50% to 90% of the total number of sub-pixels in the mother pixel 10; specifically, it can also be 60%, 65%, 70%, 75%, 85%, etc.

[0063] It should be noted that which pixel layer the sub-pixels of different colors are specifically located in can be selected according to needs and is not limited here;

[0064] In the above structure, by making the mother pixel include at least four sub-pixels and making the number of sub-pixels with a red light-emitting color greater than or equal to 50% of the total number of sub-pixels in the mother pixel, the number of red sub-pixels is effectively increased, thereby effectively controlling the attenuation of red light in the mother pixel, so that the brightness ratios of various colors can be maintained at a specific ratio, thus achieving an ideal color display effect.

[0065] Among them, each sub-pixel 20 includes a P-type semiconductor layer 202, an active layer 203, and an N-type semiconductor layer 204 arranged in sequence along the Z direction. Among them, the active layer 203 is used for emitting light. The P-type semiconductor layer 202 is arranged close to the driving wafer 50. A P-type ohmic contact layer 201 is also arranged on the side of the P-type semiconductor layer 202 close to the driving wafer 50. The P-type semiconductor layer 202 is used to connect to the anode of the driving wafer 50 to achieve anode connection, and the N-type semiconductor layer 204 is used to connect to the cathode of the driving wafer 50 to achieve cathode connection.

[0066] It should be noted that for the convenience of description, in the present invention, the microdisplay chip has a Z direction, an X direction, and a Y direction, and the three directions are perpendicular to each other in pairs. Among them, the Z direction is generally the direction away from the driving wafer. In the present invention, "up" and "down" are relative in the Z direction. Similarly, "top", "bottom", or "high", "low" are also relative in the Z direction. The top pixel layer refers to the uppermost pixel layer, and the bottom pixel layer refers to the lowermost pixel layer. Among them, the bottom pixel layer is also called the first pixel layer, and the pixel layers stacked successively above are the second layer, the third layer, etc. and so on.

[0067] The following will combine Figures 1 - 22 , and make a further specific description of the structure of the multi-color microdisplay chip of this embodiment.

[0068] Embodiment 1

[0069] Refer to Figures 1 - 6 , this embodiment discloses a multi-color microdisplay chip, including a mother pixel 10, a driving wafer 50, and three pixel layers 30;

[0070] Among them, the mother pixel 10 includes at least four sub-pixels 20. The light-emitting colors of at least two sub-pixels 20 in the mother pixel 10 are different, and there is a sub-pixel with a light-emitting color of red. The number of sub-pixels with a light-emitting color of red is not less than 50% of the total number of sub-pixels in the mother pixel 10.

[0071] The sub-pixels 20 are all electrically connected to the driving wafer 50 to control the sub-pixels 20 to emit light by using the driving wafer 50.

[0072] The three pixel layers 30 are stacked in sequence along the Z direction. All the sub-pixels 20 of the mother pixel 10 are respectively arranged in the corresponding pixel layers 30. At least one sub-pixel 20 is arranged in each pixel layer 30. The light-emitting colors of each sub-pixel 20 in the same pixel layer 30 are the same, and the light-emitting colors of the sub-pixels 20 in two adjacent pixel layers 30 are different.

[0073] For the convenience of description, the sub-pixel 20 with a light-emitting color of red is called a red sub-pixel, the sub-pixel 20 with a light-emitting color of green is called a green sub-pixel, and the sub-pixel 20 with a light-emitting color of blue is called a blue sub-pixel.

[0074] There are three sub-pixels with different light-emitting colors in the above-mentioned mother pixel, namely a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. The above three types of sub-pixels are respectively located in different pixel layers. The red sub-pixel can be arranged in the first pixel layer (the bottom pixel layer), the green sub-pixel can be arranged in the second pixel layer, and the blue sub-pixel can be arranged in the third pixel layer (the top pixel layer). In actual working conditions, which pixel layer the sub-pixels of different colors are specifically located in can be selected according to needs and is not limited here.

[0075] For example, as Figure 2 and Figure 3 shown, the mother pixel 10 includes four sub-pixels 20. Among the four sub-pixels 20, there are a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. The red sub-pixel R is used to emit red light, the green sub-pixel G is used to emit green light, and the blue sub-pixel B is used to emit blue light. The microdisplay chip includes a plurality of mother pixels 10. The four sub-pixels 20 in each mother pixel 10 can be arranged in the RGRB manner shown in Figure 2 shown, with one green sub-pixel G and one blue sub-pixel B each, and two red sub-pixels R distributed diagonally, or arranged in the RRGB manner shown in Figure 3 shown, with one green sub-pixel G and one blue sub-pixel B each, and two red sub-pixels R arranged in a column in the Y direction; if the four sub-pixel combination still cannot meet the light distribution requirement of red light, the surrounding sub-red sub-pixels can be continuously called for light distribution. For example, in Figure 2 shown, the mother pixel located in the lower right corner can call one red sub-pixel from the upper mother pixel for light distribution, or in Figure 3Among them, the mother pixel located at the lower left corner can call two red sub-pixels in the right mother pixel for light distribution.

[0076] Figure 1 is the brightness curve of the mother pixel 10. Figure 1 In [figure], "G" represents the brightness curve of the green sub-pixel, "B" represents the brightness curve of the blue sub-pixel, "R75%" represents the brightness curve of all red sub-pixels with a quantity ratio of 75% in the mother pixel, "R50%" represents the brightness curve of all red sub-pixels with a quantity ratio of 50% in the mother pixel, and "R25%" represents the brightness curve of all red sub-pixels with a quantity ratio of 25% in the mother pixel. It can be seen from the brightness curves shown in Figure 1 that when the number of red sub-pixels in the mother pixel is 50% or 75%, compared with 25%, the brightness curve moves upward and the overall brightness increases, thus effectively controlling the attenuation of red light and being more conducive to ensuring the stability of light distribution, so as to achieve an ideal color display effect.

[0077] It can be understood that the number of sub-pixels 20 in the mother pixel 10 can also be greater than four, and the specific number is not limited here.

[0078] Furthermore, the projections of all sub-pixels 20 in the mother pixel 10 on the driving wafer 50 do not overlap, so as to avoid the light crosstalk between sub-pixels 20 or the color phenomenon caused by photoexcitation to the greatest extent, thereby more precisely controlling the light combining effect.

[0079] Figure 5 is the top view of the microdisplay chip. Each microdisplay chip includes a plurality of mother pixels 10 arranged in an array to form a pixel array region 70, and a peripheral common cathode region 80 is provided on the periphery. Figure 6 is Figure 5 the partial enlarged view at A in [figure], showing the situation of a mother pixel and its surrounding partial common cathode region. Figure 7 is Figure 6 the cross-sectional view of the structure in [figure] along the path a1 - a2; the cross-sectional views of subsequent mother pixels, such as Figures 8 - 16 , Figure 18 , Figure 20 etc. are also the cross-sectional views along this path;

[0080] In one implementation, as shown in Figure 7 , the sub-pixel 20 is trapezoidal or cylindrical. Compared with pixels with a hemispherical structure or a semi-ellipsoidal structure, the trapezoidal or cylindrical sub-pixel can effectively increase the pixel light-emitting area, thereby increasing the light-emitting intensity; generally, an active layer 203 is provided in the sub-pixel 20 to emit light. From Figure 4It can be seen that, when the bottom size of the sub-pixels is the same, the area of the active layer 203 in the trapezoidal sub-pixels (the entire shaded part) is larger than the area of the active layer of the hemispherical sub-pixels (the shaded part inside the hemisphere), thereby effectively increasing the luminous intensity. Similarly, compared with the hemispherical sub-pixels, the cylindrical sub-pixels can also increase the area of the active layer, thereby effectively increasing the luminous intensity.

[0081] Further, the inclination angle θ of the side wall of the sub-pixel 20 relative to the driving wafer 50 is 45° to 135°; it can be understood that the side wall of the sub-pixel 20 here refers to the wall surface between the top surface and the bottom surface of the sub-pixel 20;

[0082] The above inclination angle can reduce total internal reflection and is more conducive to light extraction. Beyond this range, the light extraction efficiency will be reduced; in addition, due to limited horizontal space, a certain space needs to be reserved for subsequent processes. When the inclination angle is too small, the bottom surface of the pixel occupies too much horizontal space, which will increase the difficulty of pixel pitch layout.

[0083] Preferably, the inclination angle θ of the side wall of the sub-pixel 20 relative to the driving wafer 50 is 75° to 105°, which has the best light extraction efficiency and the best pixel pitch design.

[0084] In one of the embodiments, an anode contact 501 and a cathode contact 502 are provided on the driving wafer 50. Each pixel layer 30 includes an insulating body 301. The sub-pixels 20 in the pixel layer 30 are all coated inside the insulating body 301. A bonding metal part 3021 is provided on one side of each sub-pixel 20 close to the driving wafer 50, that is, each sub-pixel 20 has a bonding metal part 3021, and the bonding metal part 3021 is electrically connected to the corresponding anode contact 501;

[0085] Each sub-pixel 20 is externally coated with an insulating passivation layer 303. The bonding metal part 3021 is located inside the insulating passivation layer 303. The upper part of the insulating passivation layer 303 has an opening 3031. The outside of the insulating passivation layer 303 is coated with a common cathode layer 304. The sub-pixel 20 is electrically connected through the opening 3031 and the common cathode layer 304, and the common cathode layer 304 is used to be electrically connected to the cathode contact 502.

[0086] Understandably, the sub-pixel 20 includes a P-type ohmic contact layer 201, a P-type semiconductor layer 202, an active layer 203, and an N-type semiconductor layer 204 arranged sequentially upward along the Z direction. The P-type semiconductor layer 202 is provided with a bonding metal part 3021 on the side close to the driving wafer 50, and a P-type ohmic contact layer 201 is arranged between the P-type semiconductor layer 202 and the bonding metal part 3021 to achieve ohmic contact between the P-type semiconductor layer 202 and the bonding metal part 3021. Eventually, the P-type semiconductor layer 202 is electrically connected to the corresponding anode contact 501 through the bonding metal part 3021. The N-type semiconductor layer is exposed at the opening 3031, and the exposed part is electrically connected to the common cathode layer 304. The insulating passivation layer 303 is used to insulate and isolate the N-type semiconductor layer 204 and the P-type semiconductor layer 202 in the sub-pixel 20 to avoid short circuit.

[0087] The bonding metal parts 3021 can correspond to the anode contacts 501 one by one, or multiple anode contacts 501 can correspond to one bonding metal part 3021.

[0088] In some embodiments, as Figure 22 shown in stage d, the height D of the sub-pixel 20 in the Z direction is 0.3 um to 5 um; preferably, D is 0.3 um to 1.5 um; wherein, the height of the sub-pixel 20 is the distance between its P-type semiconductor layer 202 and N-type semiconductor layer 204 (including the thicknesses of the P-type semiconductor layer 202 and N-type semiconductor layer 204 themselves).

[0089] In some embodiments, the thickness of the P-type ohmic contact layer 201 is 10 nm to 300 nm, and its material can be a transparent conductive thin film such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., or a metal alloy thin film such as AuBe, AnZn, etc.

[0090] In some embodiments, the thickness d1 of the insulating passivation layer 303 is 30 nm to 500 nm to preferably ensure the insulation and passivation capabilities.

[0091] In some embodiments, the thickness d2 of the common cathode layer 304 is 50 nm to 500 nm to increase its transmittance as much as possible while ensuring the current spreading ability. The thicker the common cathode layer 304, the better the current spreading, but the lower the transmittance, which will cause greater light loss and also increase the processing difficulty. If the thickness is too thin, it will affect the metal current spreading ability.

[0092] In one embodiment, the bonding metal part 3021 carried by the sub-pixel 20 in the upper pixel layer 30 is electrically connected to the corresponding anode contact 501 through the anode connection part 307 passing through the lower pixel layer 30. An anode hole 306 corresponding to the anode connection part 307 is provided in each pixel layer 30 except the top layer. The anode hole 306 is filled with an anode metal material to form the anode connection part 307, so as to realize the anode connection between the upper sub-pixel 20 and the driving wafer 50 through the anode connection part 307.

[0093] It can be understood that the sub-pixels in the bottom pixel layer can be directly connected to the corresponding anode contacts through the bonding metal parts.

[0094] In one embodiment, the top length (X direction) of the anode hole 306 is greater than the bottom length.

[0095] In one embodiment, as Figure 8 shown, the angle φ between the inner wall of the anode hole 306 and the top surface of the driving wafer 50 is 90° to 120°.

[0096] Furthermore, the anode hole 306 can be trapezoidal; it can also be Y-shaped.

[0097] In some embodiments, as Figure 8 shown, in the Z direction, the distance H between the top surface of the insulating body 301 of each pixel layer 30 and the common cathode layer 304 at the top of the sub-pixels in this layer is not less than 100 nm to prevent interlayer leakage caused by insulation abnormalities.

[0098] In one embodiment, an anode hole 306 corresponding to the anode connection part 307 is provided on the interface 40 between two adjacent pixel layers. The anode hole 306 is filled with the anode connection part 307. As Figures 7 - 9 shown, the top surface of the anode connection part 307 filled in the anode hole 306 is lower than the interface 40 to form a recessed part 3061. The bonding metal part 3021 of the sub-pixel 20 in the pixel layer is embedded in the recessed part 3061 of the corresponding anode hole 306 in the adjacent lower pixel layer to be in electrical contact with the anode connection part 307;

[0099] Or, as Figures 10 - 11As shown, the top surface of the anode connection member 307 filled in the anode hole 306 is higher than the interface 40 to form a convex portion 3071. The bonding metal member 3021 of the sub-pixel 20 in the pixel layer is fitted with the convex portion 3071 of the corresponding anode connection member 307 in the adjacent pixel layer below. By this fitting method, bonding voids can be avoided between the bonding metal member 3021 and the anode connection member 307. Bonding voids will cause poor electrical transmission. Through the above-mentioned convex-concave fitting method, the above problems can be effectively avoided, ensuring excellent electrical transmission effects, and at the same time effectively increasing the connection stability and connection strength between the bonding metal member 3021 and the anode connection member 307.

[0100] Further, as Figure 8 shown, the height h1 of the concave portion 3061 is 10 nm to 300 nm. As Figure 11 shown, the height h2 of the convex portion 3071 is 10 nm to 300 nm to better avoid bonding voids and ensure electrical transmission effects. The above height should not be too large. If the height is too large, it will easily lead to an increase in process difficulty. If the height is too small, the electrical transmission effects cannot be better ensured.

[0101] In one of the embodiments, the microdisplay core includes three layers of pixel layers 30. The bottom pixel layer is also called the first pixel layer, and the pixel layers stacked above are the second layer, the third layer, and so on in sequence. Then, the bonding metal members 3021 of the sub-pixels in the pixel layers of the third layer and above can be electrically connected to the corresponding anode contacts 501 by a plurality of anode connection members 307 connected in sequence along the Z direction below. Each of the anode connection members 307 connected in sequence along the Z direction is located in different pixel layers 30;

[0102] Among them, as Figure 16 shown, two adjacent anode connection members 307 along the Z direction are in direct contact. This method does not retain the bonding metal members and other components between two adjacent anode connection members. This method is more conducive to avoiding the phenomenon of poor electrical transmission caused by bonding voids.

[0103] Or, as Figure 14 shown, a conductive metal member 3022 can also be provided between two adjacent anode connection members 307 along the Z direction. This method retains the bonding metal member of the two anode connection members 307 as the conductive metal member 3022, and the processing technology is simpler.

[0104] In one of the embodiments, the length of the top end of the anode connection member 307 in the X direction is greater than the length of the bottom end, that is, it has a structure form with a wider top and a narrower bottom. When the length of the bottom end is the same, compared with the structure with a narrower top and a wider bottom, this shape of the structure can obtain a thicker anode connection member, thereby enhancing the anode electrical transmission ability.

[0105] In one embodiment, cathode holes 308 are provided in all pixel layers 30 except the top layer. The cathode holes 308 are filled with cathode connectors 309, and the cathode connectors 309 are all electrically connected to cathode contacts 502. The common cathode layers 304 in the upper pixel layer are all electrically connected through the cathode connectors 309 and cathode contacts 502 in the lower pixel layer.

[0106] It can be understood that in specific arrangements, the common cathode layer 304 of the pixel layer in the third layer is electrically connected to the cathode contacts 502 through the cathode connectors 309 in the second and first layers in sequence. The common cathode layer 304 of the pixel layer in the second layer is electrically connected to the cathode contacts 502 through the cathode connectors 309 in the first layer in sequence. The common cathode layer 304 of the pixel layer in the first layer can be directly electrically connected to the cathode contacts 502; or, the cathode connector 309 in the second layer can be directly connected to the cathode contacts 502. In this case, the common cathode layer 304 of the pixel layer in the third layer can also be directly electrically connected to the cathode contacts 502 through the cathode connectors 309 in the second layer. That is, the common cathode layer 304 in each pixel layer can be electrically connected to the cathode contacts 502 through multiple cathode connectors 309 in the lower pixel layer in sequence, or can be directly electrically connected to the cathode contacts 502 through the pixel layer in the adjacent lower layer.

[0107] Furthermore, cathode holes 308 are also provided on the interface 40 between two adjacent pixel layers 30. The top surface of the cathode connector 309 filled in the cathode hole 308 is lower than the interface 40 to form a recessed portion, or the top surface of the cathode connector 309 filled in the cathode hole 308 is higher than the interface 40 to form a protruding portion. This is similar to the setting method of the anode connector 307 and will not be elaborated here.

[0108] In one embodiment, as Figure 12 and Figure 14 shown, the interface 40 between two adjacent pixel layers 30 is also covered by an insulating passivation layer 303. The upper part of the insulating passivation layer 303 at the interface is covered by the common cathode layer 304, and a metal mesh grid layer 305 is provided on the upper part of the common cathode layer 304 to achieve the effect of enhancing the cathode current through the metal mesh grid layer 305.

[0109] Furthermore, the metal mesh grid layer 305 can be made of one or more of Cr, Pt, Ti, Au, Al, Cu, TiN, and TaN.

[0110] In one embodiment, the thickness d3 of the metal mesh grid layer 305 is 100 nm to 5000 nm. This thickness is relatively thin, which increases the distance between the metal mesh grid layer 305 and the upper bonding metal part 3021, enabling sufficient space to fill the insulating body 301 between the metal mesh grid layer 305 and the upper bonding metal part 3021. Thus, the risk of short circuit between the metal mesh grid layer 305 and the upper bonding metal part 3021 is effectively avoided, resulting in better insulation and higher safety.

[0111] In one embodiment, as Figures 12 - 13 shown, the light emitted from the sub-pixel 20 in the lower pixel layer exits through the first notch 3051 in the upper pixel layer. The first notch 3051 is formed in the metal mesh grid layer 305, and the length L1 of the first notch 3051 in the X direction is greater than the top surface length L2 of the corresponding sub-pixel 20 in the lower layer, so that the light emitted from the lower sub-pixel 20 can exit through the first notch 3051 to the greatest extent, improving the light extraction efficiency of the pixel.

[0112] It can be understood that the "corresponding sub-pixel" here refers to the sub-pixel 20 whose emitted light passes through the first notch 3051. If the sizes of all sub-pixels in this layer are the same, then the length L1 of the first notch 3051 in the X direction is greater than the top surface length L2 of each sub-pixel in this layer.

[0113] By opening the first notch 3051 in the metal mesh grid layer 305 at the interface 40 between two adjacent pixel layers 30, that is, removing the metal mesh grid material in the first notch 3051, the above method reduces the occlusion of the metal mesh grid in the original notch on the light emitted from the bottom sub-pixel, enabling the light emitted from the sub-pixel in the lower pixel layer to not have to exit through the metal mesh grid layer 305, reducing light loss and making the bottom sub-pixel have a higher light extraction efficiency.

[0114] The above method can set notches only on the metal mesh grid layer 305, without setting notches on the common cathode layer 304.

[0115] The number of the above first notches 3051 opened can be determined according to the number of the lower sub-pixels 20.

[0116] In addition, a large notch can also be opened in the metal mesh grid layer 305 of the top pixel layer, such that the length of the large notch in the X direction is greater than the sum of the top surface lengths of all sub-pixels whose emitted light exits through this place in the following two layers.

[0117] Wherein, the metal mesh grid layer 305 in each pixel layer 30 is an integral body, and the first notch 3051 is equivalent to a hole opened in the metal mesh grid layer 305.

[0118] In one embodiment, asFigures 14 - 15 As shown, the light emitted by the sub-pixel 20 in the lower pixel layer passes through the second notch 3041 and the first notch 3051 in the upper pixel layer in sequence and then exits. The second notch 3041 is formed in the common cathode layer 304, and the length L3 of the second notch 3041 in the X direction is greater than the top surface length L2 of the corresponding sub-pixel in the lower layer.

[0119] It can be understood that the "corresponding sub-pixel" here refers to the sub-pixel 20 whose emitted light passes through the second notch 3041 and the first notch 3051 in sequence. If the sizes of all sub-pixels in this layer are the same, then the length of the second notch 3041 in the X direction is greater than the top surface length of each sub-pixel in this layer.

[0120] By forming the second notch 3041 in the common cathode layer 304 at the interface 40 between two adjacent pixel layers 30 as described above, that is, removing the common cathode material in the second notch 3041, the light emitted by the sub-pixel 20 in the lower pixel layer 30 does not need to pass through the common cathode to exit, further reducing light loss and enabling the bottom sub-pixel to have a higher light extraction efficiency.

[0121] The number of the second notches 3041 formed can be determined according to the number of the sub-pixels 20 in the lower layer, and the second notches 3041 and the first notches 3051 can correspond to each other one by one.

[0122] Among them, the common cathode layer 304 in each pixel layer 30 is an integral body, and the second notch 3041 is equivalent to a hole formed in the common cathode layer 304.

[0123] The anode connecting member 307 in the bottom pixel layer 30 can be arranged in the following two ways:

[0124] In one way, a space is separately left between two adjacent sub-pixels 20 in the X direction in the bottom pixel layer to arrange the anode connecting member 307, where the X direction and the Z direction are perpendicular to each other;

[0125] In another way, the original sub-pixel 20 is retained as an auxiliary pixel 90 between two adjacent sub-pixels 20 in the X direction in the bottom pixel layer, so that the anode connecting member 307 in the bottom pixel layer passes through an auxiliary pixel 90 and is electrically connected to the corresponding anode contact 501 on the driving wafer 50. This way can avoid re-preparing the bottom pixel layer and can directly use the original single-layer monochromatic product, that is, the pixel layers of the second layer and above can be directly stacked on the original single-layer product for use, and the preparation method is more rapid, which can reduce the cost of separately preparing the bottom pixel layer.

[0126] It should be noted that after the auxiliary pixel 90 is penetrated by the anode connecting member 307, the auxiliary pixel 90 cannot emit light normally and only serves as a connecting member.

[0127] Understandably, the anode connection member 307 needs to pass through the common cathode layer 304 outside the auxiliary pixel 90 and the insulation passivation layer 303 in sequence and then be electrically connected to the anode contact 501 of the driving wafer 50. To avoid contact between the anode connection member 307 and the common cathode layer 304 outside the auxiliary pixel 90, an auxiliary hole 3042 is provided on the common cathode layer 304 for the anode connection member 307 to pass through, as shown in Figure 19 In stage a of [the figure], the length L4 of the auxiliary hole 3042 in the X direction is greater than the length L5 of the opening 3031 of the top insulation passivation layer 303 of the auxiliary pixel 90.

[0128] In one embodiment, at least one lens 100 is connected to the upper part of the pixel layer located at the top layer. When arranging the lens 100, the following two methods can be adopted. One is that the lens 100 corresponds to the mother pixel 10 one by one, and the other is that each lens 100 corresponds to the sub-pixel 20 one by one. This method can better collimate the outgoing light of each sub-pixel 20 and further reduce the light interference within the mother pixel;

[0129] This embodiment also discloses a method for manufacturing a microdisplay chip, including,

[0130] Step M1, manufacturing the driving wafer 50;

[0131] Step M2, stacking and arranging three pixel layers 30 on the driving wafer 50 in the Z direction in sequence, so that all the sub-pixels 20 in the mother pixel 10 are respectively arranged in the corresponding pixel layers 30. At least one sub-pixel 20 is arranged in each pixel layer 30. The outgoing light colors of each sub-pixel 20 in the same pixel layer are the same, and the outgoing light colors of the sub-pixels 20 in two adjacent pixel layers are different. And the sub-pixels 20 are all electrically connected to the driving wafer 50 to drive the sub-pixels 20 to emit light by using the driving wafer 50.

[0132] In one embodiment, when manufacturing the driving wafer 50, an anode contact 501 and a cathode contact 502 need to be manufactured on the driving wafer 50; and when manufacturing the pixel layer 30, the sub-pixels 20 in the pixel layer 30 are all coated inside the insulating body 301. A bonding metal part 3021 is arranged on one side of each sub-pixel 20 close to the driving wafer 50, so that the bonding metal part 3021 is electrically connected to the corresponding anode contact 501. The outside of each sub-pixel 20 is coated with an insulation passivation layer 303. The bonding metal part 3021 is located inside the insulation passivation layer 303. The upper part of the insulation passivation layer 303 has an opening 3031. The outside of the insulation passivation layer 303 is coated with a common cathode layer 304. The sub-pixel 20 is electrically connected to the common cathode layer 304 through the opening 3031. The common cathode layer 304 is used to be electrically connected to the cathode contact 502.

[0133] During specific manufacturing, step M2 includes:

[0134] Step M21: Bond a compound semiconductor 60 onto a driving wafer 50;

[0135] As Figure 21 shown, the above-mentioned compound semiconductor 60 includes a P-type ohmic contact layer 201, a P-type semiconductor layer 202, an active layer 203, an N-type semiconductor layer 204, and a substrate 601 that are sequentially arranged in a direction away from the driving wafer. After bonding the compound semiconductor 60 onto the driving wafer 50, the substrate 601 needs to be removed to expose the N-type semiconductor layer 204; after removing the substrate 601, an N-type ohmic contact layer 205 can also be provided on the N-type semiconductor layer 204;

[0136] Furthermore, the thickness of the N-type ohmic contact layer 205 is in the range of 10 nm to 300 nm. Its material can be a transparent conductive thin film such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., or a metal alloy thin film such as gold germanium alloy (AuGe), gold nickel alloy (AuNi), etc.

[0137] Preferably, the thickness of the N-type ohmic contact layer 205 is 10 nm to 100 nm to ensure ohmic contact while also having a high transmittance, thereby reducing light loss.

[0138] Among them, the compound semiconductor 60 can be bonded onto the driving wafer 50 through a bonding layer 302, and the bonding alignment accuracy can be 10 to 500 μm.

[0139] Step M22: Pattern-etch the compound semiconductor 60 to obtain at least one sub-pixel 20, so that the sub-pixel 20 is electrically connected to the corresponding anode contact 501 through the bonding layer 302; the bonding layer 302 includes a plurality of bonding metal parts 3021, so that each sub-pixel 20 corresponds to a bonding metal part 3021, and the sub-pixel 20 is electrically connected to the corresponding anode contact 501 through the corresponding bonding metal part 3021;

[0140] Among them, each bonding metal part 3021 is obtained by etching the bonding layer 302; here, the anode contacts 501 and the sub-pixels 20 are in one-to-one correspondence, or multiple anode contacts 501 can correspond to one sub-pixel 20; Step M23: Deposit an insulating passivation layer 303 outside the sub-pixel 20, and set an opening 3031 on the upper part of the insulating passivation layer 303 to expose the N-type semiconductor layer 204 or the N-type ohmic contact layer 205 of the sub-pixel 20;

[0141] Step M24: Deposit a common cathode layer 304 outside the insulating passivation layer 303, so that the sub-pixel 20 is electrically connected to the common cathode layer 304 through the opening 3031, and the common cathode layer 304 is used to be electrically connected to the cathode contact 502. Refer toFigure 22 In the d stage;

[0142] That is, the N-type semiconductor layer 204 of the sub-pixel 20 is electrically connected through the common cathode layer 304 and the cathode contact 502 to achieve cathode connection;

[0143] Among them, only one cathode contact 502 can be provided on the driving wafer 50, or the number of cathode contacts 502 can be determined according to needs.

[0144] Step M25, fill the insulating body 301 outside the common cathode layer 304 so that all the sub-pixels 20 are located inside the insulating body 301, thereby obtaining a pixel layer 30, see Figure 22 In the e stage;

[0145] It can be understood that the insulating passivation layer 303 and the common cathode layer 304 outside the sub-pixel 20 are also located inside the insulating body 301.

[0146] Step M26, bond another compound semiconductor 60 to the top of the previous pixel layer through the bonding layer 302, and perform steps M22 - M25 to obtain the next pixel layer, see Figure 22 In the f stage;

[0147] Step M27, repeat step M26 until the preparation of all pixel layers 30 is completed, see Figure 22 In the g stage;

[0148] Among them, the light-emitting colors of each sub-pixel in the same pixel layer are the same, and the light-emitting colors of the sub-pixels in two adjacent pixel layers are different.

[0149] It can be understood that the bonding metal part 3021 between adjacent anode connectors in the Z direction can be directly used as the conductive metal part 3022. It can be understood that since the light-emitting colors of the sub-pixels in two adjacent pixel layers are different, the materials of the compound semiconductors 60 used in the preparation of two adjacent pixel layers are also different, so that the light-emitting colors of the compound semiconductors 60 used are different; when preparing each pixel layer 30, the light-emitting color of the selected compound semiconductor 60 is determined according to the actual situation. If it is necessary to prepare sub-pixels with a light-emitting color of red, a compound semiconductor with a light-emitting color of red is selected.

[0150] Among them, the compound semiconductor 60 uses inorganic compound materials. For example, the compound semiconductor corresponding to the blue light pixel layer uses InGaN material, the compound semiconductor corresponding to the green light pixel layer uses InGaN material, and the compound semiconductor corresponding to the red light pixel layer uses InGaN or AlGaInP material.

[0151] In practical applications, the film layers of compound semiconductors will be more complex, or there may be cross - use of materials. A typical compound semiconductor structure mainly includes a P - type semiconductor layer, an N - type semiconductor layer, an active layer (MQW active quantum well) sandwiched between the two, and other functional layers. For the film layer materials of red compound semiconductors, please refer to Table 1, and for the film layer materials of green and blue compound semiconductors, please refer to Table 2;

[0152] Table 1 Film Layer Materials of Compound Semiconductor (R)

[0153] Layer Name Material Material Material Material Material Material P - type Semiconductor Layer GaP GaAs GaAs GaN GaN GaN MQW Active Quantum Well AlGaInP AlGaInP AlGaAs InGaN InGaN InGaN N - type Semiconductor Layer GaAs AlGaAs GaAs GaN GaN GaN Substrate GaAs GaAs GaAs GaN Si Sapphire

[0154] Table 2 Film Layer Materials of Compound Semiconductor (G / B)

[0155] Layer Name Material Material Material P - type Semiconductor Layer GaN GaN GaN MQW Active Quantum Well InGaN InGaN InGaN N - type Semiconductor Layer GaN GaN GaN Substrate GaN Si Sapphire

[0156] In one of the embodiments, the insulating passivation layer 303 can be made of one or more of alumina, silica, and silicon nitride.

[0157] In one of the embodiments, the insulating body 301 can be made of one or more of silicon oxide, silicon nitride, silicon carbide (SiC), silicon carbonitride (SiCN), phosphate glass (PSG), and borophosphosilicate glass (BPSG).

[0158] In one of the embodiments, the common cathode layer 304 includes one or more of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum - doped zinc oxide (AZO), aluminum - doped indium tin oxide, silver - doped indium tin oxide, and gold - doped indium tin oxide;

[0159] In one of the embodiments, the metal mesh grid layer 305 can be made of one or more of Cr, Pt, Ti, Au, Al, Cu, TiN, and TaN materials.

[0160] In one of the embodiments, the material of the anode connection member 307 can be one or more of aluminum, copper, and tungsten.

[0161] Further, the material of the cathode connection member 309 can be the same as that of the anode connection member, as long as it is a conductive material.

[0162] In one of the embodiments, the material of the bonding metal member 3021 can be one of Al, Au, and Cu, or a laminated structure of Ni, Au, Cu, etc. and Sn, or a bonding laminate of Au and In, Ge, or a bonding laminate of Au and Si.

[0163] Further, the bonding metal part 3021 may adopt the following structural form: Cr 2nm / Pt 50nm / Ti 10nm / Pt 50nm / Au 100nm / Sn 150nm / Au 50nm. Among them, Cr is the adhesion layer, and Pt / Ti / Pt is the barrier layer.

[0164] Further, after the preparation of all pixel layers is completed in step M2, referring to Figure 22 in stage h, a dielectric layer is further deposited on the upper part of the pixel layer located at the top layer, and the dielectric layer is patterned and etched to form a lens 100, so that the lens 100 corresponds to the mother pixel 10 one by one, that is, one mother pixel 10 corresponds to one lens 100; or, each lens 100 corresponds to the sub-pixel 20 one by one, that is, each sub-pixel 20 corresponds to one lens 100 separately, so as to better collimate the outgoing light of each sub-pixel 20 and further reduce the light interference within the mother pixel.

[0165] In one of the embodiments, when preparing the pixel layers other than the top layer, an anode hole 306 is further opened on the insulating body 301, and an anode metal material is filled in the anode hole 306 to form an anode connecting part 307, so that the bonding metal part 3021 of the sub-pixel 20 in the pixel layer 30 is electrically connected to the corresponding anode contact 501 through the anode connecting part 307 passing through the lower pixel layer 30.

[0166] After the insulating body 301 is prepared, CMP planarization can be performed first, and then the above-mentioned anode hole 306 can be prepared by patterned dry etching on the insulating body 301.

[0167] Further, when specifically preparing the anode connecting part 307, an anode hole 306 is first opened on the interface 40 between two adjacent pixel layers, and then an anode metal material is filled in the anode hole 306 to form an anode connecting part 307, and finally the top surface of the anode connecting part 307 filled in the anode hole 306 is lower than the interface 40 to form a recessed part 3061; or,

[0168] An anode metal material is filled in the anode hole 306 to form an anode connecting part 307, so that the top surface of the anode connecting part 307 filled in the anode hole 306 is higher than the interface 40 to form a protruding part 3071.

[0169] In some embodiments, when preparing the bottom pixel layer, an auxiliary pixel 90 is also prepared, such that the anode connection member 307 in the bottom pixel layer corresponds to the auxiliary pixel 90. A through anode hole 306 needs to be prepared in the auxiliary pixel 90, and an anode metal material is filled in the anode hole 306 to form the anode connection member 307, so that the anode connection member 307 located in the bottom pixel layer is electrically connected to the corresponding anode contact 501 on the driving wafer 50 after passing through the corresponding auxiliary pixel 90.

[0170] Through this embodiment, a chip structure with three pixel layers 30 can be prepared. The light-emitting colors of each pixel layer 30 are different. The three pixel layers 30 can be respectively configured as the layer where the red sub-pixels are located, the layer where the green sub-pixels are located, and the layer where the blue sub-pixels are located to achieve the configuration of the three primary colors.

[0171] In one of the embodiments, a pixel structure corresponding to a plurality of micro-display chips can be arranged on each driving wafer 50. Each micro-display chip can correspond to an independent bonding layer 302. That is, before preparing the pixels of the micro-display chip, a plurality of discontinuous and independent bonding layers 302 can be prepared on the driving wafer 50 first, so that the bonding layer at this time corresponds to the subsequent micro-display chips one by one. During the subsequent preparation process of the micro-display chip, the bonding layer can be further etched to form a plurality of bonding metal parts 3021.

[0172] An insulating dielectric layer can be filled between the discontinuous bonding layers 302; the above discontinuous bonding layers can better improve the bonding warping and control the metal cost; in each micro-display chip, the four sides of the bonding layer 302 extend outward more than the peripheral common cathode region 80, and the outward extension width is at least 50 um. Further, the outward extension width is between 50 um and 500 um.

[0173] It can be understood that if necessary, more pixel layers can be continuously stacked on the basis of the above three pixel layers.

[0174] Embodiment 2

[0175] As Figures 17 - 20 shown, the main difference between this embodiment and Embodiment 1 is that the multi-color micro-display chip in this embodiment includes a mother pixel 10, a driving wafer 50, and two pixel layers 30 to achieve a two-color configuration:

[0176] Among them, the mother pixel 10 includes at least four sub-pixels 20. At least two sub-pixels 20 in the mother pixel 10 have different light-emitting colors, and there is a sub-pixel with a light-emitting color of red. The number of sub-pixels with a light-emitting color of red is not less than 50% of the total number of sub-pixels in the mother pixel 10;

[0177] Each sub-pixel 20 is electrically connected to the driving wafer 50 to control the light emission of the sub-pixel 20 by using the driving wafer 50;

[0178] Two pixel layers 30 are stacked in sequence along the Z direction. All the sub-pixels 20 of the mother pixel 10 are respectively arranged in the corresponding pixel layers 30. At least one sub-pixel 20 is arranged in each pixel layer 30. The light-emitting colors of each sub-pixel 20 in the same pixel layer 30 are the same, and the light-emitting colors of the sub-pixels 20 in two adjacent pixel layers 30 are different.

[0179] There are two sub-pixels 20 with different light-emitting colors in the above-mentioned mother pixel 10, namely the red sub-pixel R and the green sub-pixel. The above two sub-pixels 20 are respectively located in different pixel layers 30. The red sub-pixels can be arranged in the first pixel layer (the bottom pixel layer), and the green sub-pixels can be arranged in the second pixel layer. In actual working conditions, which pixel layer the sub-pixels of different colors are specifically located in can be selected according to needs and is not limited here;

[0180] Specifically, the mother pixel 10 includes four sub-pixels 20. The four sub-pixels 20 in each mother pixel 10 can be arranged in the Figure 17 way of RGRR as shown, having three red sub-pixels R and one green sub-pixel G. When specifically arranging, as Figure 18 shown, three red sub-pixels can be arranged in the first pixel layer, and one green sub-pixel can be arranged in the second pixel layer; or as Figure 20 shown, one green sub-pixel can be arranged in the first pixel layer, and three red sub-pixels can be arranged in the second pixel layer.

[0181] Furthermore, the projections of all the sub-pixels 20 in the mother pixel 10 on the driving wafer 50 do not overlap, so as to avoid the light crosstalk between sub-pixels or the color mixing phenomenon caused by photoexcitation to the greatest extent, thereby more precisely controlling the light combining effect.

[0182] In one of the embodiments, the cathode connecting member 309 in the bottom pixel layer can also pass through an auxiliary pixel 90 and then be electrically connected to the corresponding cathode contact 502 on the driving wafer 50. This way can avoid the re-preparation of the bottom pixel layer, and the original single-layer monochromatic product can be directly used, that is, the second and higher pixel layers can be directly stacked on the original single-layer product for use, and the preparation method is faster, and the cost of separately preparing the bottom pixel layer can be reduced. It can be understood that the cathode connecting member 309 in the first embodiment can also adopt this setting method of passing through the bottom auxiliary pixel 90 and will not be elaborated here.

[0183] In this embodiment, the sub-pixel colors in the two pixel layers can also be the red sub-pixel and the blue sub-pixel respectively, or the red sub-pixel and other color sub-pixels, which can be selected according to actual needs here.

[0184] In this embodiment, the preparation method of the microdisplay chip is referred to Figure 19 , and its preparation method is basically the same as that of the first embodiment, except that the number of stacked pixel layers is two, and the specific preparation method will not be elaborated here.

[0185] The microdisplay chips and their preparation methods in the above embodiments effectively increase the number of red sub-pixels, thereby effectively controlling the attenuation of red light in the mother pixel, so that the brightness ratios of various colors can be maintained at a specific ratio, and thus an ideal color display effect can be ensured.

[0186] All the above optional technical solutions can be combined arbitrarily to form optional embodiments of the present invention, that is, any number of embodiments can be combined to meet the requirements of different application scenarios, and all are within the protection scope of this application, which will not be elaborated one by one here.

[0187] It should be noted that the above embodiments are only examples for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims

1. A multicolor microdisplay chip, characterized in that: including a mother pixel, the mother pixel includes at least four sub-pixels, at least two sub-pixels in the mother pixel have different light-emitting colors, and there is a sub-pixel with a light-emitting color of red, and the number of sub-pixels with a light-emitting color of red is not less than 50% of the total number of sub-pixels in the mother pixel; a driving wafer, and all the sub-pixels are electrically connected to the driving wafer; at least two layers of pixel layers, all the pixel layers are sequentially stacked along the Z direction on the driving wafer, all the sub-pixels of the mother pixel are respectively arranged in the corresponding pixel layers, at least one sub-pixel is arranged in each pixel layer, the light-emitting colors of each sub-pixel in the same pixel layer are the same, and the light-emitting colors of sub-pixels in adjacent two pixel layers are different.

2. The multicolor microdisplay chip according to claim 1, wherein: The projections of all the sub-pixels in the mother pixel on the driving wafer do not overlap.

3. The multi-color microdisplay chip according to claim 1, wherein: The sub-pixels are trapezoidal or cylindrical.

4. The multi-color microdisplay chip according to claim 1, wherein: An anode contact and a cathode contact are arranged on the driving wafer, each pixel layer includes an insulating body, the sub-pixels in the pixel layer are all coated inside the insulating body, a bonding metal part is arranged on one side of each sub-pixel close to the driving wafer, the bonding metal part is electrically connected to the corresponding anode contact, an insulating passivation layer is coated outside each sub-pixel, the bonding metal part is located inside the insulating passivation layer, an opening is formed in the upper part of the insulating passivation layer, a common cathode layer is coated outside the insulating passivation layer, the sub-pixel is electrically connected through the opening and the common cathode layer, and the common cathode layer is used for being electrically connected to the cathode contact.

5. The multi-color microdisplay chip according to claim 4, wherein: Each sub-pixel includes a P-type semiconductor layer, an active layer and an N-type semiconductor layer which are sequentially arranged along the Z direction, the bonding metal part is arranged on one side of the P-type semiconductor layer close to the driving wafer, and the N-type semiconductor layer is electrically connected to the common cathode layer through the opening.

6. The multi-color microdisplay chip according to claim 4, characterized in that: The bonding metal parts of the sub-pixels in the upper pixel layer are electrically connected to the corresponding anode contacts by anode connecting parts passing through the lower pixel layer.

7. The multicolor microdisplay chip according to claim 6, wherein: An anode hole corresponding to the anode connecting part is formed on the interface between adjacent two pixel layers, the anode hole is filled with an anode connecting part, the top surface of the anode connecting part filled in the anode hole is lower than the interface to form a recessed part, and the bonding metal part of the sub-pixel in the pixel layer is embedded into the recessed part of the corresponding anode hole in the adjacent lower pixel layer to be in electrical contact with the anode connecting part; or the top surface of the anode connecting part filled in the anode hole is higher than the interface to form a protruding part, and the bonding metal part of the sub-pixel in the pixel layer is fitted with the protruding part of the corresponding anode connecting part in the adjacent lower pixel layer.

8. The multi-color microdisplay chip according to claim 7, wherein: including at least three layers of the pixel layers, the bonding metal parts of the sub-pixels in the third layer and above pixel layers are electrically connected to the corresponding anode contacts by a plurality of anode connecting parts sequentially connected along the Z direction, each of the anode connecting parts sequentially connected along the Z direction is located in a different pixel layer, adjacent two of the anode connecting parts sequentially connected along the Z direction are in direct contact, or a conductive metal part is arranged between adjacent two of the anode connecting parts.

9. The multi-color microdisplay chip according to claim 4, wherein: Cathode holes are formed on the interface between two adjacent pixel layers. The cathode holes are filled with cathode connectors, and the cathode connectors are electrically connected to cathode contacts. The common cathode layer in the upper pixel layer is electrically connected to the cathode contacts through the cathode connectors and cathode contacts in the lower pixel layer.

10. The multi-color microdisplay chip according to claim 4, characterized in that: The insulating passivation layer also covers the interface between two adjacent pixel layers. The common cathode layer also covers the upper part of the insulating passivation layer of the interface. A metal mesh grid layer is provided on the upper part of the common cathode layer.

11. The multicolor microdisplay chip according to claim 10, wherein: The light emitted from the sub-pixels in the lower pixel layer exits through the first notch in the upper pixel layer. The first notch is formed on the metal mesh grid layer. The length of the first notch in the X direction is greater than the top surface length of the corresponding sub-pixel in the lower layer, where the X direction is perpendicular to the Z direction.

12. The multicolor microdisplay chip according to claim 11, wherein: The light emitted from the sub-pixels in the lower pixel layer exits after passing through the second notch and the first notch in the upper pixel layer in sequence. The second notch is formed on the common cathode layer. The length of the second notch in the X direction is greater than the top surface length of the corresponding sub-pixel in the lower layer.

13. The multi-color microdisplay chip according to claim 6, wherein: The anode connector located in the bottom pixel layer penetrates through an auxiliary pixel and is electrically connected to the corresponding anode contact on the driving wafer; the auxiliary pixel is located in the bottom pixel layer and between two adjacent sub-pixels in the X direction, where the X direction is perpendicular to the Z direction.

14. The multicolor microdisplay chip according to claim 1, characterized in that: At least one lens is connected to the upper part of the pixel layer at the top layer. The lens corresponds to each mother pixel, or each lens corresponds to each sub-pixel.

Images