Universal multifunctional reset circuit

Abstract

The utility model discloses a universal multifunctional reset circuit, which is connected with a processor and is consistent with the processor in power supply, and comprises a monitoring circuit used for monitoring the power supply voltage of the processor and a CD4011 NAND gate circuit connected with the monitoring circuit, the monitoring circuit comprises an MAX791 monitoring chip, and the MAX791 monitoring chip is connected with the CD4011 NAND gate circuit. The sixteenth pin end and the fifteenth pin end of the MAX791 monitoring chip are connected with the CD4011 NAND gate circuit, the CD4011 NAND gate circuit comprises a CD4011 chip, and the CD4011 NAND gate circuit is used for outputting a reset signal; the utility model has the characteristics of simple structure, complete function and wide application range, can complete the functions of power-on reset, manual reset and crash reset of the processor, and can also realize watchdog shielding through manual control so as to complete the function of software on-line loading. The method can be used for equipment requiring manual reset, power-down reset, software online upgrade and reset time, and is suitable for various processors.

Description

Technical Field

[0001] The utility model relates to the technical field of processor reset circuits, and specifically relates to a general-purpose multi-functional reset circuit. Background Technique

[0002] In application devices in fields such as commerce, industry, and aerospace, to ensure the normal and reliable operation of the core processor of the product, it is often necessary to add necessary power-on reset, manual reset, and watchdog timeout reset functions when the software freezes. At the same time, due to some requirement changes and software function additions during the application process, it is often necessary to change the software of the processor. However, it often takes time and cost to return to the factory for software upgrade after the device leaves the factory, and the time cost is high. For this reason, the in-situ software upgrade function of the device is essential. Therefore, in these occasions where software needs to be loaded online, it is also necessary to manually shield the watchdog signal in the reset circuit to achieve in-situ software online upgrade of the device. The existing reset circuits have relatively single functions. Therefore, a general-purpose multi-functional reset circuit is proposed. Content of the Utility Model

[0003] The purpose of the utility model is to provide a general-purpose multi-functional reset circuit to solve the problems of single function and high time cost mentioned in the above background technique.

[0004] To achieve the above purpose, the utility model provides the following technical solutions:

[0005] A general-purpose multi-functional reset circuit, which is connected to the processor and has the same power supply as the processor, includes a monitoring circuit for monitoring the power supply voltage of the processor and a CD4011 NAND gate circuit connected to the monitoring circuit. The monitoring circuit includes a MAX791 monitoring chip. The sixteenth pin and the fifteenth pin of the MAX791 monitoring chip are connected to the CD4011 NAND gate circuit. The MAX791 monitoring chip is used for input signals, and the input signals include a watchdog feeding signal, a watchdog shielding signal, and a manual reset control signal. The watchdog shielding signal and the manual reset control signal are both ground / open signals. The watchdog feeding signal is connected to the signal port of the processor;

[0006] The CD4011 NAND gate circuit includes a CD4011 chip, a pull-up resistor R1, a pull-up resistor R5, a pull-up resistor R7, a pull-up resistor R8, a pull-up resistor R9, and a current-limiting resistor R6. The CD4011 NAND gate circuit is used for outputting a reset signal, and the reset signal is connected to the reset pin of the processor. The CD4011 chip is used for the logical conversion between the input signal and the output reset signal.

[0007] Further, the monitoring circuit further includes a decoupling capacitor C1, a decoupling capacitor C2, and a filtering capacitor C3. The filtering capacitor C3 is used as a watchdog timeout adjustment capacitor. The monitoring circuit is used to power on and power off and reset the processor when the supply voltage of the processor is lower than its normal operating voltage.

[0008] Further, the monitoring circuit further includes a resistor R2, a resistor R3, and a resistor R4 connected to the MAX791 monitoring chip. The resistance values of the voltage-dividing resistors of the resistor R2 and the resistor R4 can be adjusted to adapt to the normal supply voltage range of the processor.

[0009] Further, the CD4011 NAND gate circuit further includes a decoupling capacitor C4. The input end of the decoupling capacitor C4 is connected to a 3.3V power supply, and the output end of the decoupling capacitor C4 is connected to the power ground DGND.

[0010] The beneficial effects of the present utility model are as follows: The present utility model has the characteristics of simple structure, complete functions, and wide application range. It can complete the power-on reset, manual reset, and crash reset functions of the processor, and can also achieve watchdog masking through manual control to complete the software online loading function; while realizing the power-on reset of the device processor and the software crash timeout reset function, it can also perform online loading through manual control reset and manual control to mask the watchdog, and can set the watchdog reset time by adjusting device parameters as needed to meet the application requirements of devices with requirements for the reset time, and is applicable to a variety of processors. Description of the Drawings

[0011] Figure 1 is the multi-functional reset circuit diagram of the present utility model.

[0012] In the figure: 1 MAX791 monitoring chip, 2 dog feeding signal, 3 CD4011 NAND gate circuit, 4 reset signal, 5 watchdog masking signal, 6 manual reset control signal. Detailed Embodiments

[0013] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0014] Please refer to Figure 1, which provides a technical solution for the present utility model. A general-purpose multifunctional reset circuit is connected to a processor and has the same power supply as the processor. It includes a monitoring circuit for monitoring the power supply voltage of the processor and a CD4011 NAND gate circuit 3 connected to the monitoring circuit. The monitoring circuit includes a MAX791 monitoring chip 1. The sixteenth and fifteenth pins of the MAX791 monitoring chip 1 are connected to the CD4011 NAND gate circuit 3. The MAX791 monitoring chip 1 is used to input signals, and the input signals include a watchdog feed signal 2, a watchdog mask signal 5, and a manual reset control signal 6. The watchdog mask signal 5 and the manual reset control signal 6 are both ground / open signals. The watchdog feed signal 2 is connected to the signal port of the processor; The CD4011 NAND gate circuit 3 includes a CD4011 chip, a pull-up resistor R1, a pull-up resistor R5, a pull-up resistor R7, a pull-up resistor R8, a pull-up resistor R9, and a current-limiting resistor R6. The CD4011 NAND gate circuit 3 is used to output a reset signal, and the reset signal is connected to the reset pin of the processor. The pull-up resistors R1, R5, R7, R8, and R9 play a role in fixing the level; The CD4011 chip is used for logical conversion between the input signal and the output reset signal; The CD4011 NAND gate circuit also includes a decoupling capacitor C4. The input end of the decoupling capacitor C4 is connected to a 3.3V power supply, and the output end of the decoupling capacitor C4 is connected to the power ground DGND; Among them, the watchdog feed signal 2 is marked as the WDI signal. The WDI signal is sent by the processor and continuously flipping indicates a normal watchdog feeding state, and continuous high or low level indicates an abnormal state; The watchdog mask signal 5 is marked as the CON1 signal. The CON1 signal is used to mask the watchdog timeout reset function during online upgrade. This signal is valid when grounded, and the normal state input is open; The manual reset control signal 6 is marked as the CON2 signal. When the processor needs to be manually reset, the CON2 signal is grounded, and the normal state input is open; The function of the current-limiting resistor R6 is to ensure that the circuit will not be damaged when there is a conflict between the input of the CON2 signal and the output level of the CD4011 chip.

[0015] In this embodiment, the mentioned monitoring circuit further includes a decoupling capacitor C1, a decoupling capacitor C2, and a filter capacitor C3. The filter capacitor C3 is used as a watchdog timeout adjustment capacitor. The monitoring circuit is used to perform power-on and power-off reset on the processor when the power supply voltage of the processor is lower than its normal operating voltage; The monitoring circuit also includes a resistor R2, a resistor R3, and a resistor R4 connected to the MAX791 monitoring chip 1. The voltage-dividing resistor values of the resistor R2 and the resistor R4 can be adjusted to adapt to the normal power supply voltage range of the processor.

[0016] This general-purpose multifunctional reset circuit realizes the watchdog circuit function through devices such as the MAX791 monitoring chip 1, CD4011 NAND gates, resistors, and capacitors. The MAX791 monitoring chip 1 and CD4011 chip are used to achieve logic combination and switching, and the resistors and capacitors are used for filtering and delaying the signals transmitted between the NAND gates. By controlling the setting of the resistor and capacitor parameters, the configuration functions of the power-down reset threshold and timeout reset time are realized.

[0017] When the general-purpose multi-functional reset circuit is in use, the 3.3V power supply starts to supply power. Before reaching the minimum voltage of 3.029V for the processor's power supply, the PFO signal output of the six-pin of the MAX791 monitoring chip 1 is at a low level. At this time, the RESET reset signal of the eleven-pin of the CD4011 chip remains at a low level, and the processor remains in the reset state; after power-on, the RET signal of the fifteen-pin of the MAX791 monitoring chip 1 remains at a low level for 140ms to 280ms, preferably the signal remains at a low level for 200ms. At this time, the RESET reset signal of the 11-pin of the CD4011 chip remains at a low level, and the processor remains in the reset state; after the power-on reset is completed, the PFO signal and the RET signal output of the six-pin and fifteen-pin of the MAX791 monitoring chip 1 are at a high level. At this time, the RESET reset signal of the eleven-pin of the CD4011 chip is at a high level, and the processor is no longer reset. The watchdog is fed normally to the reset circuit through the WDI signal. At this time, the WDO output of the fourteen-pin of the MAX791 monitoring chip 1 is at a high level, MR is the nine-pin of the MAX791 monitoring chip 1 maintaining a high level, the CON1 signal and the CON2 signal are open input signals, and the processor works normally; when the processor power supply voltage is lower than 3.029V, the PFO signal output of the six-pin of the MAX791 monitoring chip 1 is at a low level through power-down reset, and the RESET reset signal of the eleven-pin of the CD4011 chip is set to a low level, and the processor is reset; when the processor stops feeding the watchdog abnormally during operation, the WDO output of the fourteen-pin of the MAX791 monitoring chip 1 is at a low level, and MR is set to a low level. At this time, the RET output of the fifteen-pin of the MAX791 monitoring chip 1 will be at a low level, and the RESET reset signal of the eleven-pin of the CD4011 chip is also at a low level, and the processor is reset; when the processor needs to be manually reset during normal operation, a low level is input to the ground through the CON2 signal, which is equivalent to MR being set to a low level. At this time, the RET output of the fifteen-pin of the MAX791 monitoring chip 1 will be at a low level, and the RESET reset signal of the eleven-pin of the CD4011 chip is also at a low level, and the processor is reset; when the processor needs to be software-updated online during normal operation, a low level is input to the ground through the CON1 signal. At this time, regardless of the states of the WDI signal and the WDO signal, the MR signal is at a high level and will not reset the processor; it should be noted that: when the CON2 input remains at a low level effectively, the manual reset is always effective and software online upgrade cannot be performed through CON1; the logic truth table of the general-purpose multi-functional reset circuit is as follows:

[0018] In summary: Combining with the logic truth table 1, this general-purpose multi-functional reset circuit can realize the power-on reset and software crash timeout reset functions of the device processor, with adjustable reset time. At the same time, it can also achieve online loading by manually controlling the reset and manually controlling the shielding of the watchdog. It is not only applicable to a variety of processors, but also has the advantages of simple circuit structure, complete functions, and wide application range.

[0019] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0020] The above embodiments only represent the preferred implementation modes of the present invention. The description is relatively specific and detailed, but it should not be understood as a limitation to the scope of the utility model patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. In the present invention, unless otherwise clearly defined and limited, terms such as "installation", "connection", "connection", "fixation", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the internal connection of two components or the interaction relationship between two components. Among them, there are various detachable installation methods. For example, it can be through the cooperation of plugging and buckling, or through the method of bolt connection, etc.

[0021] Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principle and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A general-purpose multi-functional reset circuit, which is connected to a processor and has the same power supply as the processor, is characterized in that: It includes a monitoring circuit for monitoring the power supply voltage of the processor and a CD4011 NAND gate circuit connected to the monitoring circuit. The monitoring circuit includes a MAX791 monitoring chip. The sixteenth pin and the fifteenth pin of the MAX791 monitoring chip are connected to the CD4011 NAND gate circuit. The MAX791 monitoring chip is used for inputting signals, and the input signals include a watchdog signal, a watchdog mask signal, and a manual reset control signal. The watchdog mask signal and the manual reset control signal are both ground / open signals. The watchdog signal is connected to the signal port of the processor. The CD4011 NAND gate circuit includes a CD4011 chip, a pull-up resistor R1, a pull-up resistor R5, a pull-up resistor R7, a pull-up resistor R8, a pull-up resistor R9, and a current-limiting resistor R6. The CD4011 NAND gate circuit is used for outputting a reset signal. The reset signal is connected to the reset pin of the processor. The CD4011 chip is used for the logic conversion between the input signal and the output reset signal.

2. The general-purpose multi-functional reset circuit according to claim 1, wherein: The monitoring circuit further includes a decoupling capacitor C1, a decoupling capacitor C2, and a filtering capacitor C3. The filtering capacitor C3 is used as a watchdog timeout adjustment capacitor. The monitoring circuit is used for powering on and powering off and resetting the processor when the power supply voltage of the processor is lower than its normal operating voltage.

3. The general-purpose multifunctional reset circuit according to claim 1, wherein: The monitoring circuit further includes a resistor R2, a resistor R3, and a resistor R4 connected to the MAX791 monitoring chip. The voltage-dividing resistor values of the resistor R2 and the resistor R4 can be adjusted to adapt to the normal power supply voltage range of the processor.

4. The general-purpose multi-functional reset circuit according to claim 1, characterized in that: The CD4011 NAND gate circuit further includes a decoupling capacitor C4. The input end of the decoupling capacitor C4 is connected to a 3.3V power supply, and the output end of the decoupling capacitor C4 is connected to the power supply ground DGND.

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