Semiconductor device

Abstract

The present disclosure provides a semiconductor device including a plurality of semiconductor layers vertically separated from each other, a gate structure including a lower portion and an upper portion, where the lower portion surrounds each of the plurality of semiconductor layers, and a gate spacer extending along a sidewall of the upper portion of the gate structure. In some examples, a gap dimension measured between the gate spacer and an adjacent one of the plurality of semiconductor layers is sufficiently small such that the gate structure does not contact the source / drain structure. In some examples, the gate spacer is separated from an adjacent one of the one or more semiconductor layers of the fin structure by a cap layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device manufactured using a capping layer. Background Art

[0002] In recent years, the semiconductor integrated circuit (IC) industry has continued to grow rapidly. The progress of IC materials and design technologies has enabled continuous improvement of IC iterations. The circuits of each new generation of products are smaller and more complex than those of the previous generation, resulting in higher functional density (i.e., the number of devices interconnected per wafer area) and smaller geometric dimensions (i.e., the smallest components or production lines that can be created using the manufacturing process). This downscaling process is beneficial for improving production efficiency and reducing related costs. However, as the feature size continues to shrink, the manufacturing process becomes more challenging, and ensuring the reliability of semiconductor devices becomes increasingly difficult. Therefore, the semiconductor industry faces continuous challenges to develop processes that can fabricate smaller and more reliable ICs. Summary of the Utility Model

[0003] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a plurality of semiconductor layers vertically separated from each other, a gate structure having a lower portion and an upper portion, wherein the lower portion surrounds each of the semiconductor layers of the plurality of semiconductor layers, and a gate spacer extending along the sidewalls of the semiconductor layers. The upper portion of the gate structure is electrically coupled to the source / drain structure through the plurality of semiconductor layers. The gap size measured between the gate spacer and an adjacent one of the plurality of semiconductor layers is small enough such that the gate structure does not contact the source / drain structure.

[0004] In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a fin structure disposed above a substrate, wherein the fin structure has one or more semiconductor layers vertically separated from each other, a gate structure having a lower portion and an upper portion, wherein the lower portion surrounds the upper portion of each fin structure of the one or more semiconductor layers, and a gate spacer extending along the sidewalls of the upper portion of the gate structure. Each gate spacer is separated from an adjacent one of the one or more semiconductor layers of the fin structure by a capping layer.

[0005] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a plurality of semiconductor layers vertically separated from each other, a gate structure having a lower portion and an upper portion, wherein the lower portion surrounds each of the semiconductor layers of the plurality of semiconductor layers, and a gate spacer extending along the sidewalls of the semiconductor layers. The upper portion of the gate structure is electrically coupled to the source / drain structure through the plurality of semiconductor layers. The gap size measured between the gate spacer and an adjacent one of the plurality of semiconductor layers is less than 3 nanometers, and each gate spacer is separated from an adjacent one or more semiconductor layers by a capping layer. Brief Description of the Drawings

[0006] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, various features may not be drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be increased or decreased arbitrarily.

[0007] Figure 1 A perspective view of a Gate All Around (GAA) field effect transistor (FET) device is shown according to some embodiments;

[0008] Figure 2 Shown according to some embodiments Figure 1 A cross-sectional view of a portion of the GAAFET device;

[0009] Figure 3 A flowchart of an exemplary method for manufacturing a semiconductor device is shown according to some embodiments;

[0010] Figures 4 to 15 Shown according to some embodiments during various manufacturing stages Figure 3 An exemplary semiconductor device (or a portion of an exemplary GAAFET) manufactured by the method;

[0011] Figures 16 to 18 Shown according to some embodiments during various manufacturing stages Figure 3 An exemplary semiconductor device (or a portion of an exemplary GAAFET) manufactured by the method; Figures 4 to 15 A perspective view of the exemplary semiconductor device (or a portion of an exemplary GAAFET) during various manufacturing stages;

[0012] Figure 19 Shown according to some embodiments during various manufacturing stages Figure 3 An exemplary semiconductor device manufactured by the method; Figures 4 to 15 A cross-sectional view of a portion of the exemplary semiconductor device during various manufacturing stages.

[0013]

Symbol Description

[0014] 100: GAAFET device

[0015] 102: Substrate

[0016] 104: Semiconductor layer

[0017] 106: Isolation region

[0018] 108: Gate structure

[0019] 110: Source / drain structure

[0020] 112: Interlayer dielectric

[0021] 114: Gate spacer

[0022] 116: Conformal layer

[0023] 118: Conformal layer

[0024] 120: Inner spacer

[0025] 200: Method

[0026] 210,212,214,216,218,220,222,224,226,228,230,232,234: Steps 300: Semiconductor device

[0027] 302: Substrate

[0028] 401: Fin structure

[0029] 410: Semiconductor layer / First semiconductor layer

[0030] 420: Semiconductor layer / Second semiconductor layer

[0031] 502: Capping layer

[0032] 503: Etch stop layer / ESL

[0033] 510A, 510B: dummy gate structure

[0034] 610A, 610B: Semiconductor layer / First semiconductor layer

[0035] 620A, 620B: Semiconductor layer / Second semiconductor layer

[0036] 630A, 631B: Capping layer

[0037] 631A, 631B: ESL

[0038] 710A, 710B: Inner spacer

[0039] 910A, 910B, 910C: Source / drain structure

[0040] 920: Interlayer dielectric / ILD

[0041] 950A, 950B: GAA transistor

[0042] 1000A, 1000B: Gate trench

[0043] 1120: Gate spacer

[0044] 1122: Conformal layer

[0045] 1124: Conformal layer

[0046] 1500A, 1500B: Active gate structure

[0047] CD1: Critical dimension

[0048] S2: Spacing dimension

[0049] X, Y, Z: Directions Detailed implementation manners

[0050] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. The following describes specific examples of components and arrangements to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature above or on a second feature hereinafter may include embodiments where the first feature and the second feature are formed in direct contact, and may also include embodiments where additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and in itself does not prescribe a relationship between the various embodiments and / or configurations discussed.

[0051] As used herein, terms such as "first", "second", and "third" describe various elements, components, regions, layers, and / or portions, but these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer, or portion from another. Unless the context clearly indicates otherwise, terms such as "first", "second", and "third" do not imply a sequence or order when used herein.

[0052] For the sake of brevity, conventional techniques related to the manufacture of conventional semiconductor devices are not described in detail herein. Additionally, the various steps and processes described herein may be incorporated into a more comprehensive process or process having additional functions not described in detail herein. Specifically, the various processes in semiconductor device manufacture are well known, and thus, for the sake of brevity, many conventional processes will only be briefly mentioned herein or will be completely omitted without providing well-known process details. Those skilled in the art will readily understand, after a complete reading of the present disclosure, that the structures disclosed herein can be used with a variety of techniques and can be incorporated into a variety of semiconductor devices and articles. Additionally, it should be noted that semiconductor device structures include a varying number of components, and a single component shown in the drawings may represent multiple components.

[0053] In addition, relative terms of available space in this disclosure, such as "above", "over", "upper", "above", "top", "below", "under", "lower", "beneath", "bottom", etc., are used to describe the relationship between one element or feature and one or more other elements or features. As shown in the accompanying drawings. The relative terms of space are intended to cover different orientations of the device during use or operation in addition to the orientations depicted in the drawings. This device can be oriented in other ways (rotated 90 degrees or in other orientations), and the relative descriptive words of space used herein can be interpreted accordingly. When relative terms of space such as those listed above are used to describe a first element relative to a second element, the first element can be directly on another element, or there can be intermediate elements or layers. When an element or layer is referred to as "on" another element or layer, then this element is directly on another element or layer and in contact with another element or layer.

[0054] It should be noted that references in the specification to "one embodiment", "an embodiment", "exemplary embodiment", "exemplary", "example", etc. indicate that the described embodiments may include specific features, structures or characteristics, but each embodiment does not necessarily include the specific features, structures or characteristics. In addition, such terms do not necessarily refer to the same embodiment. Furthermore, when a specific feature, structure or characteristic is described in connection with an embodiment, whether or not explicitly described, influencing such a feature, structure or characteristic in connection with other embodiments will be within the knowledge of those skilled in the art.

[0055] Some embodiments of the present disclosure will now be described with reference to the accompanying drawings, where the same reference numerals are generally used throughout to refer to the same elements. In the following, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the claimed subject matter. However, it is apparent that the claimed subject matter can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to facilitate the description of the claimed subject matter.

[0056] Additional operations can be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the described stages can be replaced or eliminated. Additional features can be added to the semiconductor device structure. For different embodiments, some of the features described below can be replaced or removed. Although some embodiments are discussed with operations performed in a specific order, these operations can be performed in another logical order.

[0057] As used herein, a "layer" is a region, such as a region including any boundary, and does not necessarily include a uniform thickness. For example, a layer can be a region including at least some thickness variations.

[0058] Embodiments of the present disclosure are discussed in the context of forming a Gate All Around (GAA) field effect transistor (FET) device. In some embodiments, an etch stop layer and a cap layer are formed over fins including a plurality of first semiconductor layers and a plurality of second semiconductor layers, serving as a sacrificial layer and a channel layer, respectively. A dummy gate structure is formed over the fins, and an etch stop layer and a capping layer are between the fins and the dummy gate structure. Then, a gate spacer is formed on the sidewalls of the dummy gate structure. Next, source / drain structures are formed on opposite sides of the dummy gate structure, and an interlayer dielectric (ILD) is deposited over the source / drain structures. When forming the ILD, the dummy gate structure, a portion of the cap layer and the etch stop layer, and a portion of the sacrificial layer are removed to form and extend a gate trench. Next, an active gate structure is formed in the gate trench to surround each channel layer.

[0059] The semiconductor devices and methods disclosed herein provide a cap layer to facilitate an increased process window and allow the etch stop layer to be etched with a weaker etchant (i.e., reactant). It can reduce the likelihood of source / drain structure damage, active gate structure extrusion, and active gate structure-source / drain structure short circuit.

[0060] Figure 1 With Figure 2 Perspective and cross-sectional views of an exemplary GAAFET device 100 shown in accordance with various embodiments. The GAAFET device 100 includes a substrate 102 and a plurality of semiconductor layers 104 (also referred to as nanostructures (e.g., nanosheets, nanowires, etc.)) above the substrate 102. The semiconductor layers 104 are vertically separated from each other (with respect to Figure 1 the direction). Isolation regions 106 are formed on opposite sides of the protruding portions of the substrate 102, where the semiconductor layers 104 are disposed above the protruding portions. A gate structure 108 surrounds each semiconductor layer 104 (e.g., the entire perimeter of each semiconductor layer 104). Source / drain structures 110 are disposed on opposite sides of the gate structure 108. The source / drain structures may refer to the source or the drain individually or collectively, depending on the context. An interlayer dielectric (ILD) 112 is disposed above the source / drain structures 110. Inner spacers 120 are located between the semiconductor layers 104 along the sidewalls of the gate structure 108. Gate spacers 114 are disposed between the gate structure 108 and the ILD 112. In this example, the gate spacers 114 include a first conformal layer 116 along the sidewalls of the semiconductor layers 104. A second conformal layer 118 along the sidewalls of the ILD 112.

[0061] Figure 1 and Figure 2 depicts a simplified GAAFET device, and it should be understood that one or more features of a complete GAAFET device may not be shown in Figure 1 and Figure 2 . Additionally, Figure 1 is provided as a reference to show multiple cross-sections in the subsequent figures. As shown, cross-section A-A extends along the longitudinal axis of semiconductor layer 104 and along the direction of current flow between the source / drain structures (e.g., along the Y direction). For clarity, the subsequent figures will refer to this reference cross-section. For example, Figure 2 depicts Figure 1 a portion of the GAAFET device along cross-section A-A.

[0062] Figure 3 shows a flowchart of a method 200 for forming a semiconductor device, such as a non-planar transistor device, according to one or more embodiments of the present disclosure. For example, at least some operations (or steps) of method 200 can be used to form a FinFET device, a GAAFET device (e.g., GAAFET device 100), a nanosheet transistor device, a nanowire transistor device, a vertical transistor device, etc. It should be noted that method 200 is only an example and is not used to limit the present disclosure. Therefore, it should be understood that additional operations can be provided before, during, and after Figure 3 the method 200, and some other operations may only be briefly described herein. For convenience, some operations of method 200 will be described with reference to cross-sectional views of an exemplary semiconductor device 300 at various manufacturing stages as shown in Figures 4 to 15 and Figure 19 respectively, and a perspective view of the exemplary semiconductor device 300 is shown in Figures 16 to 18 . However, method 200 is not limited to the exemplary semiconductor device 300 or Figures 4 to 19 the example shown.

[0063] Figures 14 to 19 The operations of Figure 1 , Figure 2 are intended to produce a GAAFET device similar to the GAAFET device 100 shown in Figures 4 to 19 . It should be understood that the semiconductor device 300 may include many other devices, such as but not limited to inductors, fuses, capacitors, coils, etc., and these components are not shown in Figures 4 to 19 for clarity. Figures 4 to 15 and Figure 19 The cross-sectional views are in a direction perpendicular to the length direction of the active / dummy gate structure of the semiconductor device 300 (e.g., cross-section A-A shown in Figure 1 ).

[0064] Method 200 may begin at step 210. At step 212, the method provides a substrate 302, as Figure 4 shown. The substrate 302 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 302 may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates may also be used, such as multi-layered or gradient substrates. In some embodiments, the semiconductor material of the substrate 302 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0065] At step 214, method 200 includes forming a fin structure 401, the fin structure 401 including a plurality of first semiconductor layers 410 and a plurality of second semiconductor layers 420 alternately arranged on top of each other (e.g., along the Z direction) to form a stack on the substrate 302. For example, one second semiconductor layer 420 is disposed above one first semiconductor layer 410, and then another first semiconductor layer 410 is disposed above the second semiconductor layer 420, and so on. The fin structure 401 extends along the lateral direction (e.g., the Y direction) of the substrate 302.

[0066] This stack may include any number of first semiconductor layers 410 and second semiconductor layers 420 alternately arranged respectively. For example, in Figure 5 , the stack includes three first semiconductor layers 410, two second semiconductor layers 420 alternately disposed between the first semiconductor layers 410, and another second semiconductor layer 420 located at the top of the first semiconductor layers 410 and the second semiconductor 420. It should be understood that the semiconductor device 300 may include any number of first semiconductor layers 410 and any number of second semiconductor layers 420, where either the first semiconductor layer 410 or the second semiconductor layer 420 is the topmost semiconductor layer, while still being within the scope of this disclosure.

[0067] The first semiconductor layer 410 and the second semiconductor layer 420 may each have different thicknesses. In addition, the first semiconductor layer 410 may have different thicknesses from one layer to another. The second semiconductor layer 420 may have different thicknesses from one layer to another. The thickness of each of the first semiconductor layer 410 and the second semiconductor layer 420 may be, for example, in the range of from a few nanometers to tens of nanometers. The first layer of the stack (e.g., closest to the substrate 302) may be thicker than the other first semiconductor layers 410 and second semiconductor layers 420. In some embodiments, each first semiconductor layer 410 has a thickness in the range of from about 5 nanometers (nm) to about 20 nm, and each second semiconductor layer 420 has a thickness in the range of from about 5 nm to about 20 nm.

[0068] The semiconductor layers 410 and 420 have different compositions. In various embodiments, the compositions of the semiconductor layers 410 and 420 provide different oxidation rates and / or different etching selectivities between the semiconductor layers 410 and 420. In an embodiment, the first semiconductor layer 410 includes silicon germanium (Si 1-x Ge x ), and the second semiconductor layer includes silicon (Si). In one embodiment, each semiconductor layer 420 is silicon that may be undoped or substantially free of dopants (ie, having a thickness from about 0 cm -3 to approximately 1x1017cm -3 extrinsic dopant concentration), where doping is not intentionally performed, for example, when forming the second semiconductor layer 420 (eg, silicon).

[0069] In various embodiments, the semiconductor layer 420 may be intentionally doped. For example, when the semiconductor device 300 is configured as n-type (and operates in enhancement mode), each semiconductor layer 420 may be silicon doped with a p-type dopant, such as boron (B), aluminum (Al), indium (In), and gallium (Ga); and when the semiconductor device 300 is configured as p-type (and operates in enhancement mode), each semiconductor layer 420 may be silicon doped with an n-type dopant, such as phosphorus (P), arsenic (As), and antimony (Sb). In another example, when the semiconductor device 300 is configured as n-type (and operates in depletion mode), each semiconductor layer 420 may be silicon doped with an n-type dopant; when the semiconductor device 300 is configured as p-type (and operates in depletion mode), each semiconductor layer 420 may be silicon doped with a p-type dopant. In some embodiments, each semiconductor layer 410 is Si-Ge and includes Ge with a molar ratio (x<0.5) less than 50%. For example, Si 1-x Ge xThe semiconductor layer 410 may include Ge in a molar ratio of about 15% to 35%. In addition, the first semiconductor layer 410 may include compositions different from each other, and the second semiconductor layer 420 may include compositions different from each other.

[0070] Either of the semiconductor layers 410 and 420 may include other materials, for example, compound semiconductor materials such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, or alloy semiconductor materials such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. The materials of the semiconductor layers 410 and 420 may be selected based on providing different oxidation rates and / or etching selectivities.

[0071] In various examples, the fin structure 401 may be formed by first forming the first semiconductor layer 410 and the second semiconductor layer 420 in an alternating manner to define a stack, and then patterning the stack and the semiconductor substrate 302.

[0072] In various examples, the semiconductor layers 410 and 420 may be epitaxially grown from the semiconductor substrate 302. For example, each of the semiconductor layers 410 and 420 may be grown by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process such as a metal organic CVD (MOCVD) process, and / or other suitable epitaxial growth processes. During the epitaxial growth process, the crystal structure of the semiconductor substrate 302 extends upward such that the semiconductor layers 410 and 420 have the same crystal orientation as the semiconductor substrate 302.

[0073] In various examples, techniques such as photolithography and etching may be used to pattern the stack and the substrate 302. For example, a mask layer (which may include multiple layers such as a bottom oxide layer and a covering nitride layer) is formed on the topmost semiconductor layer (such as Figure 5Above the 420). The liner oxide layer may be a thin film including, for example, silicon oxide formed using a thermal oxidation process. The liner oxide layer may be used as an adhesion layer between the topmost semiconductor layer 420 (or the topmost semiconductor layer 410 in some other embodiments) and the overlying liner nitride layer. In some embodiments, the liner nitride layer is formed of silicon nitride, silicon oxynitride, silicon carbonitride, etc., or a combination thereof. For example, low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) may be used to form the liner nitride layer.

[0074] Lithography techniques can be used to pattern the mask layer. Generally, lithography techniques utilize a photoresist material (not shown), deposit, irradiate (expose), and develop the photoresist material to remove a portion of the photoresist material. The remaining photoresist material can protect the underlying material (such as the mask layer in this example) from subsequent processing steps (such as etching). For example, a photoresist material is used to pattern the liner oxide layer and the liner nitride layer to form a patterned mask.

[0075] Subsequently, the patterned mask can be used to pattern the exposed portions of the first semiconductor layer 410, the second semiconductor layer 420, and the substrate 302 to form trenches (or openings), thereby defining fin structures 401 between adjacent trenches. When multiple fin structures 401 are formed, the trenches can be disposed between any adjacent fin structures 401. In some embodiments, the fin structures 401 are formed by etching trenches in the first semiconductor layer 410, the second semiconductor layer 420, and the substrate 302 using, for example, reactive ion etch (RIE), neutral beam etch (NBE), etc., or a combination thereof. The etching can be, for example, anisotropic. In some embodiments, (when viewed from the top), the trenches can be parallel to each other and closely spaced strips. In some embodiments, the trenches can be continuous and surround the fin structures 401.

[0076] At step 216, method 200 includes forming a capping layer 502 and an etch stop layer (ESL) 503 on top of the first semiconductor layer 410 or the second semiconductor layer 420, as Figure 6As shown. The capping layer 502 may be formed over the fin structure 401. The capping layer 502 may be formed by a deposition process, such as chemical vapor deposition (CVD) (e.g., plasma enhanced chemical vapor deposition (PECVD), high aspect ratio process (HARP), or a combination thereof), atomic layer deposition (ALD) process, another suitable process, or a combination thereof. The capping layer 502 may be formed of various materials that provide a controllable etch rate, i.e., an etch rate slower than various other materials of the semiconductor device 100, such as the first semiconductor layer 410, the second semiconductor layer 420, and / or dummy gate structures 510A, dummy gate structures 510B (discussed in detail below). By providing a controllable etch rate, the capping layer 502 may subsequently be etched to have substantially vertical edges, which may then facilitate a more vertical deposition of other layers on the capping layer 502 (e.g., the gate spacer 1120 discussed below). Non-limiting examples of materials that may be used for the capping layer 502 include silicon germanium (Si 1-x Ge x ), silicon boride (SiB x ), silicon phosphide (SiP), and silicon arsenide (SiAs x ). The capping layer 502 promotes an increase in the process window and allows the use of a weaker etchant to etch the ESL 503. This in turn reduces the likelihood of source / drain structure damage, metal gate extrusion, and metal gate-source / drain short circuits.

[0077] Next, the ESL 503 may be formed over the capping layer 502. In some other embodiments, the ESL 503 may be formed only over the top surface of the capping layer 502. The ESL 503 may be formed by a deposition process, such as chemical vapor deposition (CVD) (e.g., plasma enhanced chemical vapor deposition (PECVD), high aspect ratio process (HARP), or a combination thereof), atomic layer deposition (ALD) process, another suitable process, or a combination thereof. The ESL 503 may be formed of a material that is resistant to the etchant used to remove portions of the dummy gate structures 510A and dummy gate structures 510B formed in subsequent steps of method 200 discussed in more detail below. In some examples, the ESL 503 may include silicon monoxide (SiO) or be formed of silicon monoxide (SiO).

[0078] At step 218, method 200 includes forming one or more dummy gate structures 510A and dummy gate structures 510B over the capping layer 502 and the ESL 503, as Figure 7As shown. The dummy gate structures 510A and 510B may each extend along a lateral direction (e.g., the X direction), and the vertical direction in which the dummy gate structures 510A and 510B extend is perpendicular to the lateral direction in which the fin structure 401 extends. In various embodiments, the dummy gate structures 510A and 510B may be disposed at positions where corresponding active (e.g., metal) gate structures will be formed later. For example, in Figure 7 , each of the dummy gate structures 510A and 510B is disposed over a corresponding portion of the fin structure 401, where the capping layer 502 and the ESL 503 are sandwiched between the dummy gate structures 510A and 510B and the fin structure 401. The covered portion of the fin structure 401 is then formed into a conduction channel, which includes a portion of the second semiconductor layer 420, and the active gate structures 1500A and 1500B each replace the dummy gate structures 510A and 510B to surround respective portions of the second semiconductor layer 420.

[0079] In some embodiments, each of the dummy gate structures 510A and 510B includes a material that is unfavorable for epitaxial growth. Thus, during a later stage of performing an epitaxial growth process (e.g., when forming the source / drain structures 970A to 970C), the epitaxial growth can be significantly confined around the dummy gate structures 510A and 510B (e.g., along the sidewalls of the dummy gate structures 510A and 510B). In some embodiments, each of the dummy gate structures 510A and 510B may include and be deposited with one or more silicon-based dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxycarbide, a multi-layer structure of the above materials, or a combination of the above materials. In some embodiments, each of the dummy gate structures 510A and 510B may include and be deposited with one or more metal-based materials, such as cobalt, tungsten, hafnium oxide, aluminum oxide, or a combination of the above materials. Figure 16 A perspective view of the semiconductor device 300 after forming the dummy gate structures 510A and 510B is shown according to various embodiments. Figure 17 An isolation enlarged view of the fin structure 401 is shown.

[0080] Figure 8A cross-sectional view of the semiconductor device 300 during various stages of fabrication, in which portions of the capping layer 502 and the ESL 503 that are not located below the dummy gate structures 510A and 510B are removed. The portions of the ESL 503 and the capping layer 502 that are not located below the dummy gate structures 510A and 510B can be removed by, for example, an etching process having one or more steps. For example, a portion of the ESL 503 can be removed by a first step of the etching process, which exposes a portion of the capping layer 502. Next, the exposed portion of the capping layer 502 can be removed by a second step of the etching process. In another example, these portions of the ESL 503 and the capping layer 502 can be removed together by one step of the etching process. By removing these portions of the ESL 503 and the capping layer 502, the top surface of the topmost semiconductor layer 420 is exposed.

[0081] The etching process can include a plasma etching process, which can have a certain degree of anisotropic characteristics. In the plasma etching process (including radical plasma etching, remote plasma etching, and other suitable plasma etching processes), a gas source and a passivation gas can be included, where the gas source can include, for example, chlorine gas (Cl2), hydrogen bromide (HBr), carbon tetrafluoride (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), hexafluoro-1,3-butadiene (C4F6), boron trichloride (BCl3), sulfur hexafluoride (SF6), hydrogen gas (H2), nitrogen trifluoride (NF3), hydrogen fluoride (HF), ammonia gas (NH3), and other suitable gas sources and their combinations, and the passivation gas can include, for example, nitrogen gas (N2), oxygen gas (O2), carbon dioxide (CO2), sulfur dioxide (SO2), carbon monoxide (CO), methane (CH4), silicon tetrachloride (SiCl4), and other suitable passivation gases and their combinations. In addition, for the plasma etching process, the gas source and / or the passivation gas can be diluted with gases such as argon (Ar), helium (He), neon (Ne), and other suitable dilution gases and their combinations to control the etching rate described above. As a non-limiting example, in the etching process, the source power is from 10 watts to 4000 watts, the bias power is from 0 watts to 4000 watts, the pressure is from 1 millitorr to 8 torr, and the etching gas flow rate is from 0 standard cubic centimeters per minute (sccm) to 5000 sccm, for example, about 20 sccm to 3000 sccm. However, it should be noted that source power, bias power, pressure, and flow rates outside of these ranges are also conceivable.

[0082] In another example, the etching process may include a wet etching process combined with a plasma etching process, and the wet etching process may have a certain amount of isotropic characteristics. In such a wet etching process, a main etching chemical, an auxiliary etching chemical, and a solvent may be used. The main etching chemical may be, for example, hydrofluoric acid (HF), fluorine (F2), and other suitable main etching chemicals and their combinations. The auxiliary etching chemical may be, for example, sulfuric acid (H2SO4), hydrogen chloride (HCl), hydrogen bromide (HBr), ammonia (NH3), phosphoric acid (H3PO4), and other suitable auxiliary etching chemicals and their combinations. The solvent may be, for example, deionized water, alcohol, acetone, and other suitable solvents and their combinations to control the above etching rate.

[0083] The dummy gate structure 510A and the dummy gate structure 510B may be used as masks to etch the non-overlapping portions of the capping layer 502 and the ESL 503. As a result, along the Z direction, the newly formed sidewalls of the remaining portions of the capping layer 502 and the ESL 503 are aligned with the sidewalls of the dummy gate structure 510A or the dummy gate structure 510B. For example, in Figure 8 the capping layer 630A and the ESL 631A are the remaining portions of the capping layer 502 and the ESL 503 covered by the dummy gate structure 510A, respectively; the capping layer 630B and the ESL 631B are the remaining portions of the ESL 503 and the capping layer 502 covered by the dummy gate structure 510B, respectively.

[0084] Figure 18 A perspective view of the semiconductor device 300 after removing a portion of the capping layer 502 and the ESL 503 as described above is presented according to various embodiments.

[0085] Reference Figure 19 , after the etching process, the ESL 631A and the ESL 631B may have exposed portions defining their vertical sidewalls (e.g., forming an angle of approximately 90 degrees with the top surface of the topmost semiconductor layer 420), so that, i.e., substantially flush or aligned with the sidewalls of the dummy gate structure 510A and the dummy gate structure 510B. The capping layer 630A and the capping layer 630B may have exposed portions defining sidewalls. In some examples, the sidewalls of the capping layer 630A and the capping layer 630B are perpendicular and aligned with the sidewalls of the ESL 631A and the ESL 631B, while in other examples, as Figure 19As shown, capping layers 630A and 630B extend from the vertical sidewalls and have a curvature. In some embodiments, the exposed portions of capping layers 630A and 630B may extend a protrusion dimension Da, where the protrusion dimension Da is measured from the vertical sidewalls along the top surfaces of the topmost semiconductor layers 620A and 620B, and the protrusion dimension Da is, for example, about 0.3 nm to 3 nm, or about 0.3 nm to 2 nm. In some embodiments, the sidewall curvature of capping layers 630A and 630B may have an angle θa of about 90 degrees to about 100 degrees.

[0086] At step 220, method 200 includes forming a gate spacer 1120 as Figure 9 shown. The gate spacer 1120 is formed along the sidewalls of dummy gate structures 510A and 510B. The gate spacer 1120 may be formed as a single conformal layer or a combination of two or more conformal layers, and each conformal layer lines a corresponding sidewall of dummy gate structures 510 and 510B. It should be understood that any number of combinations of conformal layers may be formed as the gate spacer while still being within the scope of this disclosure. In Figure 9 the example of, the gate spacer 1120 includes a first conformal layer 1124 and a second conformal layer 1122.

[0087] In some embodiments, each conformal layer 1122 and conformal layer 1124 may include a dielectric material selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide, silicon oxycarbide, etc. or a combination thereof. For example, atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD) may be used to form conformal layers 1122 and 1124. The thickness of each conformal layer may be between about 2 angstroms to about in range.

[0088] In some embodiments, the first conformal layer 1124 may be deposited on the sidewalls of dummy gate structures 510A, dummy gate structure B, and the topmost semiconductor layer 420. Next, the second conformal layer 1122 may be deposited on the first conformal layer 1124. Thereafter, a portion of conformal layers 1122 and 1124 located above the topmost semiconductor layer 420 may be removed, for example, by an etching process.

[0089] After the etching process, the gate spacer 1120 can include a second conformal layer 1122 having one exposed sidewall and a first conformal layer 1124 having an L-shaped profile. Specifically, the L-shaped first conformal layer 1124 includes a vertical portion and a horizontal portion, where the vertical portion is located between the dummy gate structure 510A and the dummy gate structure 510B and the second conformal layer 1122, and the horizontal portion exposes one of its sidewalls.

[0090] At step 222, method 200 includes removing a portion of the fin structure 401, as Figure 10 shown. The dummy gate structures 510A and 510B can be used as masks to etch the non-overlapping portions of the fin structure 401, which results in the fin structure 401 having a remaining portion that includes one or more alternating stacked semiconductor layers 410 and 420. As a result, along the Z direction, the newly formed sidewalls of each fin structure 401 are aligned with the sidewalls of the dummy gate structure 510A or the dummy gate structure 510B. For example, in Figure 10 the semiconductor layers 610A and 620A are the remaining portions of the semiconductor layers 410 and 420 covered by the dummy gate structure 510A, respectively; the semiconductor layers 610B and 620B are the remaining portions of the semiconductor layers 410 and 420 covered by the dummy gate structure 510B, respectively.

[0091] At step 224, method 200 includes forming a first inner spacer 710A along the respective etched ends of the semiconductor layer 610A and forming a second inner spacer 710B along the respective etched ends of the semiconductor layer 610B, as Figure 11 shown. To form the inner spacer 710A and the inner spacer 710B, the respective ends of each semiconductor layer 610A and semiconductor layer 610B can be removed first. The semiconductor layers 610A and 610B can be pulled back by an initial pull-back distance using a "pull-back" process to remove (e.g., etch) the ends of the semiconductor layer 610A-B. Although in the embodiment shown in Figure 10 the etched ends of each semiconductor layer 610A and semiconductor layer 610B are approximately perpendicular (e.g., parallel to the sidewalls of the dummy gate structure 510A and the dummy gate structure B), it should be understood that the etched ends can be curved inward or outward. Where the semiconductor layers 620A and 620B include silicon and the semiconductor layers 610A and 610B include SiGe (i.e., Si 1-x Ge x) In the example of , the pull-back process may include a hydrogen chloride (HCl) gas isotropic etching process that etches SiGe without etching silicon. Thus, semiconductor layers 620A and 620B may remain intact during this process.

[0092] Next, inner spacers 710A and 710B may be formed along the etched ends of semiconductor layers 610A and 620B, respectively. Thus, inner spacers 710A and 710B (e.g., their respective inner sidewalls) may follow the contours of the etched ends of semiconductor layers 610A and 620B. In some embodiments, inner spacers 710A and 710B may be conformally formed by chemical vapor deposition (CVD) or by monolayer doping (MLD) of nitride followed by spacer RIE. Inner spacers 710A and 710B may be deposited using a conformal deposition process, followed by an isotropic or anisotropic etch process to remove excess spacer material on the sidewalls of the stacked fin structures 401 and on the surface of semiconductor substrate 302. The materials of inner spacers 710A and 710B may be formed of the same or different materials as dummy gate structures 510A and 510B. For example, inner spacers 710A and 710B may be formed of silicon nitride, silicon boron carbonitride, silicon carbonitride, silicon carbon nitride, or any other type of dielectric material suitable for acting as an insulating gate sidewall spacer for a transistor (e.g., a dielectric material having a dielectric constant k less than about 5).

[0093] At step 226, the method includes forming source / drain structures 910A, 910B, and 910C and an interlayer dielectric (ILD) 920. Source / drain structures 910A, 910B, and 910C may be formed on the exposed ends of semiconductor layers 620A and 620B, respectively, using, for example, an epitaxial layer growth process. In some embodiments, the bottom surfaces of source / drain structures 910A, 910B, and 910C may be flush with the top surface of an isolation structure (not shown) embedded in the lower portion of fin structure 401. In some other embodiments, the bottom surfaces of source / drain structures 910A, 910B, and 910C may be lower than the top surface of this isolation structure. On the other hand, in some embodiments, the top surfaces of source / drain structures 910A, 910B, and 910C may be higher than the top surfaces of the topmost semiconductor layers 610A and 620B, as Figure 12 shown. In some other embodiments, the top surfaces of source / drain structures 910, 910B, and 910C may be flush with or lower than the top surfaces of the topmost semiconductor layers 610A and 610B.

[0094] The source / drain structures 910A, 910B, and 910C are electrically coupled to the corresponding semiconductor layers 620A and semiconductor layer 620B. For example, the source / drain structures 910A and 910B may be electrically coupled to the semiconductor layer 620A; the source / drain structures 910B and 910B may be electrically coupled to the semiconductor layer 620B. In various embodiments, the semiconductor layer 620A may be commonly used as the conductive channel of a first GAA transistor (hereinafter "GAA transistor 950A"); and the semiconductor layer 620B may be commonly used as the conductive channel of a second GAA transistor (hereinafter "GAA transistor 950B"). It should be noted that at this manufacturing stage, the GAA transistor 950A and the GAA transistor 950B are not yet complete.

[0095] In-situ doping (ISD) can be applied to form the doped source / drain structures 910A, 910B, and 910C, thereby creating the junctions of the GAA transistor 950A and the GAA transistor 950B. N-type and P-type FETs are formed by injecting different types of dopants into selected regions of the device (e.g., source / drain structures 910A, 910B, and 910C) to form junctions. An N-type device can be formed by implanting arsenic (As) or phosphorus (P), and a P-type device can be formed by implanting boron (B).

[0096] When forming the source / drain structures 910A, 910B, and 910C, the ILD 920 can be formed by depositing a bulk dielectric material over the partially formed GAA transistor 950A and GAA transistor 950B, and polishing the bulk oxide (e.g., using CMP) back to the height of the dummy gate structures 510A and dummy gate structures 510B. The dielectric material of the ILD 920 may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or a combination thereof.

[0097] At step 228, the method 200 includes removing the dummy gate structures 510A, dummy gate structures 510B, ESL 631A, ESL 631B, and a portion of the capping layers 630A, 630B, as Figure 13 shown. When forming the ILD 920 ( Figure 12)After that, the dummy gate structures 510A and 510B are removed to form gate trenches 1000A and 1000B respectively. The dummy gate structures 510A and 510B can be removed by known etching processes, such as RIE or chemical oxide removal (COR). After removing the dummy gate structures 510A and 510B (forming the gate trenches 1000A and 1000B), the top surfaces of the ESLs 631A and 631B are exposed. Although not shown in the cross-sectional view of Figure 12 , it should be understood that in some embodiments, in addition to exposing the top surfaces of the ESLs 613A and 631B, the sidewalls (facing the X direction) of the semiconductor layers 610A, 620B and semiconductor layers 620A, 620B can also be exposed.

[0098] The portions of the ESLs 631A and 631B and the capping layers 630A and 630B that do not extend along the sidewalls of the gate trenches 1000A and 1000B can be removed by an etching process, which can include one or more steps. For example, a portion of the exposed portions of the ESLs 631A and 631B above the bottom surfaces of the gate trenches 1000A and 1000B (the top surfaces of the capping layers 630A and 630B) can be removed by the first step of the etching process, and a portion of the capping layers 630A and 630B is exposed. Next, the exposed portions of the capping layers 630A and 630B can be removed by the second step of the etching process. In another example, the above portions of the ESLs 631A and 631B and the capping layers 630A and 630B can be removed together by one step of the etching process. By removing these portions of the ESLs 631A and 631B and the capping layers 630A and 630B, the top surfaces of the topmost semiconductor layers 620A and 620B are exposed. The etching process can include, for example, a plasma etching process, a wet etching process, or a combination thereof, as described above in Figure 10 described.

[0099] The remaining portions (if any) of the ESLs 631A and 631B and the capping layers 630A and 630B respectively have sidewalls that are vertically aligned with the sidewalls formed by the conformal layers 1122 and 1124 of the gate spacers 1120. The sidewalls of these vertically aligned gate spacers 1120 are exposed in the gate trenches 1000A and 1000B. In this way, as Figure 15As shown, the ESL631A, ESL631B, capping layer 630A, capping layer 630B, and gate spacer 1120 may share a critical dimension CD1, which is measured between their respective sidewalls along the Y direction. In various embodiments, the critical dimension CD1 may be from about 0.3 nanometers (nm) to 10 nm, such as from about 3 nm to 10 nm.

[0100] At step 230, method 200 includes removing the first semiconductor layers 610A, first semiconductor layers 610B (referring again to Figure 13 ). The semiconductor layers 610A, semiconductor layers 610B may be removed by applying a selective etch (e.g., hydrochloric acid (HCl)), while leaving the semiconductor layers 620A, semiconductor layers 620B substantially intact. According to various embodiments, after removing the semiconductor layers 610A, semiconductor layers 610B, the bottom surface and / or top surface of each of the semiconductor layers 620A, semiconductor layers 620B may be exposed through the "extended" gate trenches 1000A, gate trenches 1000B, respectively. For example, when removing the semiconductor layers 610A, semiconductor layers 610B, the gate trenches 1000A, gate trenches 1000B may extend from a region above the topmost semiconductor layers 610A, semiconductor layers 610B to a region below the topmost semiconductor layers 610A, semiconductor layers 610B. Thus, the bottom surface of each of the topmost semiconductor layers 620A, semiconductor layers 620B may be exposed, and the corresponding top and bottom surfaces of the remaining semiconductor layers 620A, semiconductor layers 620B may also be exposed.

[0101] At step 232, method 200 includes forming one or more active gate structures 1500A and active gate structures 1500B. The active gate structures 1500A, active gate structures 1500B may be formed in the extended gate trenches 1000A, gate trenches 1000B ( Figure 13 ), while leaving other components (e.g., gate spacer 1120) substantially intact. Thus, the active gate structures 1500A, active gate structures 1500B may inherit the dimensions and profiles of the gate trenches 1000A, gate trenches 1000B, respectively. The upper portion may be surrounded by the gate spacer 1120, and the lower portion may surround each of the semiconductor layers 620A, semiconductor layers 620B.

[0102] In some embodiments, each of the active gate structures 1500A and active gate structures 1500B includes a gate dielectric and a gate metal. In such embodiments, both the gate dielectric and the gate metal may be formed with one or more layers.

[0103] In some embodiments where the gate dielectric and the gate metal each comprise a single layer, the gate dielectric may surround each semiconductor layer 620A, semiconductor layer 620B, such as the top surface, bottom surface, and sidewalls facing the X direction. The gate dielectric may be formed of different high-k dielectric materials or similar high-k dielectric materials. Exemplary high-k dielectric materials include metal oxides, nitrides, or silicates of Hf, Al, Zr, Ta, La, Mg, Ba, Ti, Pb, and combinations thereof. The gate dielectric may comprise a stack of multiple high-k dielectric materials. Any suitable method may be used to deposit the gate dielectric, where the methods include, for example, molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc. In some embodiments, the gate dielectric may optionally comprise a substantially thin oxide (e.g., SiO2) layer, and the gate dielectric may be a native oxide layer formed on the surfaces of each semiconductor layer 620A, semiconductor layer 620B.

[0104] The gate metal may surround each semiconductor layer 620A and semiconductor layer 620B, and the gate dielectric is disposed between the gate metal and the semiconductor layers 620A, 620B. Specifically, the gate metal may comprise a plurality of gate metal segments adjacent to each other in the Z direction. Each gate metal portion may extend not only along a horizontal surface (e.g., a plane extended by the X direction and the Y direction), but also along a vertical direction (e.g., the Z direction). In this way, two adjacent gate metal portions in the gate metal portion can be adjacent to each other and form a corresponding layer around the semiconductor layers 620A and 620B, and the gate dielectric is disposed between the gate metal and the semiconductor layers 620A, 620B.

[0105] The gate metal may comprise a stack of multiple metal materials. For example, the gate metal may comprise a P-type work function layer, an N-type work function layer, multiple layers thereof, or a combination thereof. The work function layer may also be referred to as a work function metal. Exemplary P-type work functions may include TiN, TAN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary N-type work function metals may include Ti, Ag, TaAl, TaAIC, TiAlN, TAC, TACN, TaSiN, Mn, Zr, other suitable N-type work function materials, or combinations thereof. The work function value is associated with the material composition of the work function layer. Therefore, the material of the work function layer is selected to adjust its work function value so as to achieve the target threshold voltage V in the device to be formed. The work function layer may be deposited by CVD, physical vapor deposition (PVD), ALD, and / or other suitable processes.

[0106] In various embodiments, the gate spacer 1120 and the topmost semiconductor layer 620B can be in substantial contact such that little or no material of the active gate structure 1500A, the active gate structure 1500B is located therebetween (e.g., as shown on the left side). In other embodiments, the capping layers 630A, 630B can isolate the gate spacer 1120 and the topmost semiconductor layer 620B. In some embodiments, the capping layers 630A, 630B provide a spacer dimension S2, as shown in Figure 15 , measured in the Z direction between the gate spacer 1120 and the topmost semiconductor layer 620B, where the spacer dimension S2 can be about 0.3 nm or less. Figure 15 In other embodiments, the capping layers 630A, 630B can isolate the gate spacer 1120 and the topmost semiconductor layer 620B. In some embodiments, the capping layers 630A, 630B provide a spacer dimension S2, as shown in Figure 15 , measured in the Z direction between the gate spacer 1120 and the topmost semiconductor layer 620B, where the spacer dimension S2 can be about 0.3 nm or less. Figure 15 shown, measured in the Z direction between the gate spacer 1120 and the topmost semiconductor layer 620B, where the spacer dimension S2 can be about 0.3 nm or less.

[0107] Method 200 can terminate at step 234.

[0108] Accordingly, the present disclosure provides a semiconductor device and a method of forming a semiconductor device using a capping layer.

[0109] The semiconductor device and method disclosed herein provide capping layers (e.g., capping layers 630A, 630B) that facilitate increasing the process window and allow the use of a weaker etchant to etch the etch stop layer (e.g., ESLs 631A, 631B). This can reduce the likelihood of damage to the source / drain structures (source / drain structures 910A, 910B, and 910C), extrusion of the metal gate (e.g., active gate structures 1500A, 1500B), and metal gate-source / drain short circuits.

[0110] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a plurality of semiconductor layers vertically separated from each other, a gate structure having a lower portion and an upper portion, where the lower portion surrounds each semiconductor layer of the plurality of semiconductor layers, and a gate spacer extending along the sidewalls of the semiconductor layers. The upper portion of the gate structure is electrically coupled to the source / drain structure through the plurality of semiconductor layers. A gap dimension measured between the gate spacer and an adjacent one of the plurality of semiconductor layers is small enough such that the gate structure does not contact the source / drain structure.

[0111] In some embodiments, the gap size is less than 3 nanometers (nm). In some embodiments, each gate spacer has a thickness dimension measured along a direction perpendicular to the vertical sidewall of the gate structure, and the thickness dimension is 3 nm or greater. In some embodiments, each gate spacer and an adjacent layer of the semiconductor layer are separated by a capping layer. In some embodiments, the capping layer is formed of silicon germanium. In some embodiments, the capping layer has sidewalls, and the angle formed by the sidewalls and an adjacent layer of the semiconductor layer is between 90 degrees and 100 degrees. In some embodiments, the edge of the capping layer extends from the sidewall of the gate spacer, and the capping layer has a dimension measured along a direction perpendicular to the sidewall of the gate spacer, and the dimension is 2 nm or less.

[0112] In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a fin structure disposed above a substrate. The fin structure has one or more semiconductor layers vertically separated from each other, a gate structure having a lower portion and an upper portion, where the lower portion surrounds the upper portion of each fin structure of the one or more semiconductor layers, and gate spacers extending along the sidewalls of the upper portion of the gate structure. Each gate spacer and an adjacent layer of the one or more semiconductor layers of the fin structure are separated by a capping layer.

[0113] In some embodiments, the measured gap size between the gate spacer and an adjacent layer of the one or more semiconductor layers is 0.3 nm or less. In some embodiments, the gate spacer and an adjacent layer of the one or more semiconductor layers of the fin structure are separated by an etch stop layer. In some embodiments, the etch stop layer is aligned with the sidewall of the gate spacer. In some embodiments, the capping layer is formed of silicon germanium. In some embodiments, the capping layer has sidewalls, and the angle formed by the sidewalls and an adjacent layer of the one or more semiconductor layers is between 90 degrees and 100 degrees. In some embodiments, the edge of the capping layer extends from the sidewall of the gate spacer, and the capping layer has a dimension measured along a direction perpendicular to the sidewall of the gate spacer, and the dimension is 2 nm or less.

[0114] In another aspect of the present disclosure, a method of manufacturing a semiconductor device is disclosed. The method includes the following steps. Form a fin structure on a substrate, the fin structure extending along a first lateral direction of the substrate, wherein the fin structure includes a plurality of alternating first semiconductor layers and a plurality of second semiconductor layers. Form a capping layer on the fin structure. Form a dummy gate structure over a portion of the fin structure, wherein the dummy gate structure extends along the substrate in a second direction perpendicular to the first lateral direction, wherein a portion of the capping layer is located between the fin structure and the dummy gate structure. Line a plurality of gate spacers on sidewalls of the dummy gate, wherein the gate spacers are separated from an adjacent one of the first semiconductor layer and the second semiconductor layer by the capping layer. Remove a portion of the fin structure and the capping layer that is not under the dummy gate structure. Form a plurality of source / drain structures respectively coupled to a plurality of ends of the fin structure, wherein the source / drain structures are formed at positions originally occupied by the fin structure and a portion of the capping layer. Remove the dummy gate structure and the underlying capping layer to form a gate trench. Remove the first semiconductor layer such that the second semiconductor layers are vertically separated from each other by a plurality of voids. And form an active gate structure in the gate trench, the active gate structure filling the voids between the second semiconductor layers such that the active gate structure surrounds the second semiconductor layers of the fin structure.

[0115] In some embodiments, the measured gap size between each gate spacer and an adjacent one of the first semiconductor layer and the second semiconductor layer is 0.3 nm or less. In some embodiments, each gate spacer has a thickness dimension measured along a direction perpendicular to the sidewall of the active gate structure, wherein the thickness dimension is 3 nm or greater. In some embodiments, a portion of the capping layer is disposed between each gate spacer and an adjacent one of the second semiconductor layers. In some embodiments, the capping layer has sidewalls, wherein the angle formed by the sidewalls and an adjacent one of the first semiconductor layer and the second semiconductor layer is between 90 degrees and 100 degrees. In some embodiments, an edge of the capping layer extends from the sidewall of the gate spacer, and the capping layer has a dimension measured along a direction perpendicular to the sidewall of the gate spacer, wherein the dimension is 2 nm or less.

[0116] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a plurality of semiconductor layers vertically separated from each other, a gate structure having a lower portion and an upper portion, wherein the lower portion surrounds each semiconductor layer of the plurality of semiconductor layers, and gate spacers extending along sidewalls of the semiconductor layers. The upper portion of the gate structure is electrically coupled to a source / drain structure through the plurality of semiconductor layers. The measured gap size between the gate spacers and an adjacent one of the plurality of semiconductor layers is less than 3 nanometers, wherein each gate spacer is separated from an adjacent one of one or more semiconductor layers by a capping layer.

[0117] In some embodiments, the capping layer has sidewalls, and the angle formed by the sidewalls with the semiconductor layer or an adjacent layer of the semiconductor layer is between 90 degrees and 100 degrees.

[0118] The features of several embodiments are outlined above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that the present disclosure can be readily used as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made by those skilled in the art within the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that, Comprising: A plurality of semiconductor layers, vertically separated from each other; A gate structure including a lower portion and an upper portion, wherein the lower portion surrounds each of the semiconductor layers; A plurality of gate spacers extending along the sidewalls of the upper portion of the gate structure; And A plurality of source / drain structures electrically coupled through the plurality of semiconductor layers, wherein a gap size measured between the plurality of gate spacers and an adjacent one of the plurality of semiconductor layers is small enough such that the gate structure does not contact the plurality of source / drain structures.

2. The semiconductor device according to claim 1, wherein, Wherein each of the gate spacers and an adjacent one of the plurality of semiconductor layers are separated by a capping layer.

3. The semiconductor device according to claim 2, wherein, Wherein the capping layer is formed of silicon germanium.

4. The semiconductor device according to claim 2, wherein, Wherein the capping layer has a sidewall, and an angle formed by the sidewall and an adjacent one of the plurality of semiconductor layers is between 90 degrees and 100 degrees.

5. The semiconductor device according to claim 2, characterized in that, Wherein an edge of the capping layer extends from the sidewall of each of the gate spacers, and the capping layer has a dimension measured in a direction perpendicular to the sidewall of each of the gate spacers, and the dimension is 2 nanometers or less.

6. A semiconductor device, characterized in that, Comprising: A fin structure disposed above a substrate, wherein the fin structure has one or more semiconductor layers vertically separated from each other; A gate structure including a lower portion and an upper portion, wherein the lower portion surrounds the semiconductor layer or the plurality of semiconductor layers of the fin structure; And A plurality of gate spacers extending along the sidewalls of the upper portion of the gate structure, wherein each of the plurality of gate spacers and an adjacent one of the semiconductor layer or the plurality of semiconductor layers are separated by a capping layer.

7. The semiconductor device according to claim 6, wherein, Wherein a gap size measured between the plurality of gate spacers and an adjacent one of the semiconductor layer or the plurality of semiconductor layers is 0.3 nanometers or less.

8. The semiconductor device according to claim 6, wherein, Wherein the plurality of gate spacers and an adjacent one of the semiconductor layer or the plurality of semiconductor layers of the fin structure are separated by an etch stop layer.

9. A semiconductor device, characterized in that, Comprising: A plurality of semiconductor layers, vertically separated from each other; A gate structure including a lower portion and an upper portion, wherein the lower portion surrounds each of the semiconductor layers; A plurality of gate spacers extending along the sidewalls of the upper portion of the gate structure; And A plurality of source / drain structures electrically coupled through the plurality of semiconductor layers, wherein a gap size measured between the plurality of gate spacers and an adjacent one of the plurality of semiconductor layers is less than 3 nanometers, wherein each of the plurality of gate spacers and an adjacent one of the semiconductor layer or the plurality of semiconductor layers are separated by a capping layer.

10. The semiconductor device according to claim 9, wherein, Wherein the capping layer has a sidewall, and an angle formed by the sidewall and an adjacent one of the semiconductor layer or the plurality of semiconductor layers is between 90 degrees and 100 degrees.

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