Multilayer multicolor micro display chip

Abstract

The utility model relates to a multilayer multicolor micro-display chip, which comprises a driving wafer and at least two pixel layers, and an anode contact is arranged on the driving wafer. All the pixel layers are sequentially stacked on the driving wafer in the Z direction, at least one sub-pixel is arranged in each pixel layer, each sub-pixel is provided with a bonding metal piece, the bonding metal piece of the sub-pixel in the upper pixel layer is electrically connected to the corresponding anode contact through the anode connecting piece penetrating through the lower pixel layer, and the bonding metal piece of the sub-pixel in the lower pixel layer is electrically connected to the corresponding anode contact through the anode connecting piece penetrating through the lower pixel layer. The bonding metal piece of the sub-pixel in the upper pixel layer is provided with a first contact surface, the first contact surface is a non-flat surface, the first contact surface is embedded into the pixel layer where the anode connecting piece is located and is in contact with the anode connecting piece, or the anode connecting piece is embedded into the first contact surface; the sub-pixels in the same pixel layer have the same light emitting color, and the sub-pixels in two adjacent pixel layers have different light emitting colors. According to the utility model, the reliability of anode current transmission is effectively ensured.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a multi-layer and multi-color microdisplay chip. Background Art

[0002] In the field of LED display, microdisplay technology has been widely developed in recent years, especially Micro-LED display technology, which has the advantages of high efficiency, low power consumption, high integration and high stability, and is considered to be one of the most promising next-generation new display and lighting devices. Micro-LED display technology has now been widely applied to near-eye display terminal products, including virtual reality (VR), augmented reality (AR), mixed reality (MR), etc. In the existing microdisplay chip, a plurality of pixel units arranged in an array are usually arranged in the display area. In order to further reduce the horizontal size of the microdisplay chip and increase the pixel density, in the prior art, the chip can be set into a vertically stacked multi-layer structure, and each layer is provided with light-emitting pixel units. In such a multi-layer structure, generally, adjacent two layers need to be bonded through a bonding layer, and the pixel units of the upper layer are connected to the anode connectors of the lower layer through the bonding layer, so as to realize the connection between the pixel units and the anode of the driving wafer through the anode connectors. However, in the existing structure, gaps are easily generated between the bonding layer and the anode connectors in adjacent two layers, resulting in poor contact between the two and affecting electrical transmission, and thus unable to meet the use requirements. Summary of the Utility Model

[0003] Therefore, the technical problem to be solved by the utility model is to overcome the defect that poor contact easily occurs between the bonding layer and the anode connectors in the prior art, which affects electrical transmission.

[0004] To solve the above technical problem, the utility model provides a multi-layer and multi-color microdisplay chip, including

[0005] a driving wafer, on which an anode contact is arranged;

[0006] at least two pixel layers, all the pixel layers are sequentially stacked on the driving wafer along the Z direction, at least one sub-pixel is arranged in each pixel layer, a bonding metal part is arranged on one side of each sub-pixel close to the driving wafer, the bonding metal part of the sub-pixel in the upper pixel layer is electrically connected to the corresponding anode contact through an anode connector passing through the lower pixel layer, the bonding metal part of the sub-pixel in the upper pixel layer has a first contact surface for contacting the anode connector, the first contact surface is a non-flat surface, the first contact surface is embedded in the pixel layer where the anode connector is located and contacts the anode connector, or the anode connector is embedded in the first contact surface;

[0007] Among them, the light-emitting colors of each of the sub-pixels in the same pixel layer are the same, and the light-emitting colors of the sub-pixels in two adjacent pixel layers are different.

[0008] In an embodiment of the present utility model, the projections of all the sub-pixels on the driving wafer do not overlap.

[0009] In an embodiment of the present utility model, an anode hole corresponding to the anode connecting member is formed on the interface between two adjacent pixel layers. The anode hole is filled with an anode connecting member, and the top surface of the anode connecting member filled in the anode hole is lower than the interface to form a recessed portion. An embedding protrusion is formed on the first contact surface, and the embedding protrusion of the sub-pixel in the pixel layer is embedded into the recessed portion of the corresponding anode hole in the adjacent pixel layer below to be in electrical contact with the anode connecting member; or,

[0010] The top surface of the anode connecting member filled in the anode hole is higher than the interface to form a protruding portion, and an embedding recess is formed on the first contact surface. The embedding recess of the sub-pixel in the pixel layer is fitted with the protruding portion of the corresponding anode connecting member in the adjacent pixel layer below.

[0011] In an embodiment of the present utility model, the height of the recessed portion is 10 nm to 300 nm, and the height of the protruding portion is 10 nm to 300 nm.

[0012] In an embodiment of the present utility model, it includes at least three layers of the pixel layers. The bonding metal parts of the sub-pixels in the third and higher pixel layers are electrically connected to the corresponding anode contacts by a plurality of anode connecting members sequentially connected along the Z direction below. Each of the anode connecting members sequentially connected along the Z direction is located in a different pixel layer, and two adjacent anode connecting members among the anode connecting members sequentially connected along the Z direction are in direct contact; or, a conductive metal part is provided between two adjacent anode connecting members.

[0013] In an embodiment of the present utility model, the inclination angle of the inner wall of the anode hole relative to the top surface of the driving wafer is 90° to 120°.

[0014] In an embodiment of the present utility model, a cathode contact is further provided on the driving wafer. Each pixel layer includes an insulating body. The sub-pixels in the pixel layer are all located inside the insulating body. An insulating passivation layer is coated outside each sub-pixel. The bonding metal part of the sub-pixel is located inside the insulating passivation layer. An opening is provided in the upper part of the insulating passivation layer. A common cathode layer is coated outside the insulating passivation layer. The sub-pixel is electrically connected through the opening and the common cathode layer, and the common cathode layer is used for electrical connection with the cathode contact.

[0015] In an embodiment of the present utility model, each sub-pixel includes a P-type semiconductor layer, an active layer, and an N-type semiconductor layer arranged in sequence along the Z direction. A bonding metal part is provided on one side of the P-type semiconductor layer close to the driving wafer, and the N-type semiconductor layer is electrically connected to the common cathode layer through the opening.

[0016] In an embodiment of the present utility model, a cathode hole is formed on the interface between two adjacent pixel layers. The cathode hole is filled with a cathode connecting part, and each cathode connecting part is electrically connected to a cathode contact. The common cathode layer in the upper pixel layer is electrically connected to the cathode contact through the cathode connecting part in the lower pixel layer.

[0017] In an embodiment of the present utility model, the distance between the top surface of the insulating body of each pixel layer and the common cathode layer at the top of the sub-pixels in this layer is not less than 100 nm.

[0018] In an embodiment of the present utility model, the thickness of the common cathode layer is 50 nm to 500 nm.

[0019] In an embodiment of the present utility model, the sub-pixels are trapezoidal or cylindrical.

[0020] In an embodiment of the present utility model, the length of the top end of the anode connecting part in the X direction is greater than the length of the bottom end, and the X direction is perpendicular to the Z direction.

[0021] In an embodiment of the present utility model, at least one lens is connected to the upper part of the pixel layer located at the top layer. Each sub-pixel corresponds to one lens, or a plurality of sub-pixels correspond to one lens.

[0022] The above technical solution of the present utility model has the following advantages compared with the prior art:

[0023] For the multi-layer multi-color micro-display chip of the present utility model, through the way of mutual fitting, the bonding metal part and the anode connecting part are in full contact, thus effectively ensuring the reliability of anode current transmission; and also effectively ensuring the connection strength between the bonding metal part and the anode connecting part. Description of the Drawings

[0024] In order to make the content of the present utility model easier to be clearly understood, the following further details the present utility model according to the specific embodiments of the present utility model in conjunction with the drawings.

[0025] Figure 1 It is a comparison schematic diagram of trapezoidal sub-pixels and hemispherical sub-pixels;

[0026] Figure 2 It is the internal structure diagram of the first multi-layer micro-display chip of the present utility model;

[0027] Figure 3 is Figure 2 Internal enlarged view at U in

[0028] Figure 4 is Figure 2 Arrangement schematic diagram of the bottom pixel layer in

[0029] Figure 5 Internal structure diagram of the second multi - layer micro - display chip of the present utility model;

[0030] Figure 6 Internal structure diagram of the third multi - layer micro - display chip of the present utility model;

[0031] Figure 7 is Figure 6 Internal enlarged view at V in

[0032] Figure 8 is Figure 6 Arrangement schematic diagram of the bottom pixel layer in

[0033] Figure 9 Internal structure diagram of the fourth multi - layer micro - display chip of the present utility model;

[0034] Figure 10 Partial preparation flow chart of the chip of the present utility model;

[0035] Figure 11 is Figure 2 Preparation flow chart of the structure shown;

[0036] Explanation of reference numerals in the specification drawings:

[0037] 10. Driving wafer; 101. Anode contact; 102. Cathode contact;

[0038] 20. Sub - pixel; 201. P - type ohmic contact layer; 202. P - type semiconductor layer; 203. Active layer; 204. N - type semiconductor layer; 205. N - type ohmic contact layer;

[0039] 30. Pixel layer; 301. Insulating body; 302. Bonding layer; 3021. Bonding metal part; 30211. First contact surface; 30212. Embedded protrusion; 30213. Embedded depression; 3022. Conductive metal part; 303. Insulating passivation layer; 3031. Opening; 304. Common cathode layer; 305. Anode hole; 3051. Depression part; 306. Anode connecting part; 3061. Protrusion part; 307. Cathode hole; 308. Cathode connecting part;

[0040] 40. Interface;

[0041] 50. Compound semiconductor; 501. Substrate;

[0042] 60. Lens. Detailed implementation mode

[0043] The present utility model will be further described below in conjunction with the accompanying drawings and specific embodiments, so that those skilled in the art can better understand the present utility model and be able to implement it, but the embodiments cited are not used as a limitation to the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and in no way limits the present disclosure, its application or use.

[0044] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "vertical", "upper", "lower", "top", "side", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present utility model. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present utility model, unless otherwise specified, the meaning of "a plurality" is two or more.

[0045] The following will be combined with Figures 1 - 11 to further describe the structure of the multi-layer multi-color microdisplay chip of this embodiment.

[0046] It should be noted that for the convenience of description, the microdisplay chip in the present utility model has mutually perpendicular Z direction and X direction, where the Z direction is generally the direction away from the driving wafer. In the present utility model, "upper" and "lower" are relative in the Z direction. Similarly, "top", "bottom" or "high", "low" are also relative in the Z direction. The top pixel layer refers to the uppermost pixel layer, and the bottom pixel layer refers to the lowermost pixel layer. Among them, the bottom pixel layer is also called the first-layer pixel layer, and the pixel layers stacked in sequence above are the second layer, the third layer, etc. in sequence.

[0047] Embodiment

[0048] Refer to Figures 2 - 11 , this embodiment discloses a multi-layer multi-color microdisplay chip, including a driving wafer 10 and at least two layers of pixel layers 30; wherein, the driving wafer 10 has a driving circuit inside for controlling the sub-pixels 20 in the pixel layer 30 to emit light, and the driving wafer 10 can adopt a CMOS driving wafer;

[0049] Among them, the driving wafer 10 is provided with an anode contact 101;

[0050] All pixel layers are stacked sequentially along the Z direction on the driver wafer 10. Each pixel layer 30 is provided with at least one sub-pixel 20. A bonding metal part 3021 is provided on the side of each sub-pixel 20 close to the driver wafer 10. The bonding metal part 3021 of the sub-pixel 20 in the upper pixel layer is electrically connected to the corresponding anode contact 101 by an anode connector 306 that passes through the underlying pixel layer 30. The bonding metal part 3021 of the sub-pixel in the upper pixel layer has a first contact surface 30211, which is used to contact the anode connector 306. The first contact surface 30211 is a non-flat surface. The first contact surface 30211 is embedded in the pixel layer 30 where the anode connector 306 is located and contacts the anode connector 306, or the anode connector 306 is embedded in the first contact surface 30211.

[0051] The light emitting colors of each sub-pixel 20 in the same pixel layer are the same, and the light emitting colors of the sub-pixels in two adjacent pixel layers are different, so as to achieve a multi-color configuration.

[0052] In the above structure, when the bonding metal part 3021 of the sub-pixel 20 in the upper pixel layer is connected to the anode connector 306 of the lower pixel layer, the contact surface between the bonding metal part 3021 and the anode connector 306 is a non-flat surface, so that the first contact surface 30211 is embedded in the pixel layer 30 where the anode connector 306 is located and contacts the anode connector 306, or the anode connector 306 is embedded in the first contact surface 30211. This interlocking structure can effectively avoid the bonding gap or void between the bonding metal part 3021 and the anode connector 306, so that the bonding metal part 3021 and the anode connector 306 are in full contact, thereby effectively ensuring the reliability of the anode current transmission; in addition, the above-mentioned mutually interlocking structure can also effectively ensure the connection strength between the bonding metal part 3021 and the anode connector 306, and is also more conducive to alignment and positioning.

[0053] The bonding metal parts 3021 may correspond to the anode contacts 101 one by one, or multiple anode contacts 101 may correspond to one bonding metal part 3021 .

[0054] In one embodiment, the projections of all sub-pixels 20 on the driver wafer 10 do not overlap, so as to minimize the optical crosstalk between sub-pixels or the color variation caused by photoexcitation, thereby more accurately controlling the light combining effect.

[0055] In some embodiments, as Figures 2 - 4As shown, an anode hole 305 corresponding to the anode connection member 306 is formed on the interface 40 between two adjacent pixel layers. The anode hole 305 is filled with the anode connection member 306. The top surface of the anode connection member 306 filled in the anode hole 305 is lower than the interface 40 to form a recessed portion 3051. An embedding protrusion 30212 is formed on the first contact surface 30211. The embedding protrusion 30212 of the sub-pixel 20 in the pixel layer is embedded in the recessed portion 3051 of the corresponding anode hole 305 in the adjacent pixel layer below to be in electrical contact with the anode connection member 306;

[0056] Alternatively, as Figures 6 - 8 shown, the top surface of the anode connection member 306 filled in the anode hole 305 is higher than the interface 40 to form a protruding portion 3061. An embedding recess 30213 is formed on the first contact surface 30211. The embedding recess 30213 of the sub-pixel 20 in the pixel layer is engaged with the protruding portion 3061 of the corresponding anode connection member 306 in the adjacent pixel layer below. This method is more convenient for processing. Through the above-mentioned convex-concave engagement method, excellent electrical transmission effects can be effectively ensured.

[0057] In addition, compared with making the interface between two adjacent pixel layers into a completely flat structure, the above-mentioned interface with convex-concave characteristics is easier to process, simplifies the processing technology, and is more conducive to mass production of products.

[0058] Furthermore, as Figure 4 shown, the height h1 of the recessed portion 3051 is 10 nm to 300 nm. As Figure 8 shown, the height h2 of the protruding portion 3061 is 10 nm to 300 nm to better avoid bonding voids and ensure electrical transmission effects. The above height should not be too large, as an overly large height will easily increase the process difficulty. If the height is too small, the electrical transmission effects cannot be better ensured.

[0059] In some embodiments, it includes at least three pixel layers 30. The bottom pixel layer is also called the first pixel layer, and the pixel layers stacked above are the second layer, the third layer, and so on in sequence. Then, the bonding metal member 3021 of the sub-pixel 20 in the third layer and above pixel layers is electrically connected to the corresponding anode contact 101 by a plurality of anode connection members 306 connected in sequence along the Z direction below. Each of the anode connection members 306 connected in sequence along the Z direction is located in different pixel layers 30;

[0060] Among them, two adjacent anode connection members 306 among the anode connection members 306 connected in sequence along the Z direction are in direct contact. As Figure 9 shown, this method does not retain the bonding metal member and other components between two adjacent anode connection members 306. This method is more conducive to avoiding poor electrical transmission caused by bonding voids;

[0061] Alternatively, as Figure 2 shown, a conductive metal piece 3022 can also be provided between two adjacent anode connection pieces 306. In this way, the bonding metal pieces of the two anode connection pieces 306 are retained as the conductive metal piece 3022, and the processing technology is simpler.

[0062] In some embodiments, the length of the top end (X direction) of the anode hole 305 is greater than the length of the bottom end.

[0063] In some embodiments, as Figure 4 shown, the inclination angle φ of the inner wall of the anode hole 305 relative to the top surface of the driving wafer 10 is 90° to 120°.

[0064] Furthermore, the anode hole 305 can be trapezoidal; or it can be Y-shaped.

[0065] In some embodiments, a cathode contact 102 is further provided on the driving wafer 10. Each pixel layer 30 includes an insulating body 301. The sub-pixels 20 in the pixel layer 30 are all coated inside the insulating body 301. An insulating passivation layer 303 is coated outside each sub-pixel 20. The bonding metal piece 3021 of the sub-pixel 20 is located inside the insulating passivation layer 303. An opening 3031 is provided in the upper part of the insulating passivation layer 303. A common cathode layer 304 is coated outside the insulating passivation layer 303. The sub-pixel 20 is electrically connected to the common cathode layer 304 through the opening 3031, and the common cathode layer 304 is used to be electrically connected to the cathode contact 102.

[0066] Among them, each sub-pixel 20 includes a P-type semiconductor layer 202, an active layer 203, and an N-type semiconductor layer 204 arranged in sequence along the Z direction. The active layer 203 is used to emit light. The P-type semiconductor layer 202 is used to be connected to the anode of the driving wafer 10 to achieve anode connection, and the N-type semiconductor layer 204 is used to be connected to the cathode of the driving wafer 10 to achieve cathode connection.

[0067] Furthermore, the sub-pixel 20 includes a P-type ohmic contact layer 201, a P-type semiconductor layer 202, an active layer 203, and an N-type semiconductor layer 204 arranged in sequence along the Z direction upward. A bonding metal piece 3021 is provided on the side of the P-type semiconductor layer 202 close to the driving wafer 10. A P-type ohmic contact layer 201 is provided between the P-type semiconductor layer 202 and the bonding metal piece 3021 to achieve ohmic contact between the P-type semiconductor layer 202 and the bonding metal piece 3021. Thus, finally, the P-type semiconductor layer 202 is electrically connected to the corresponding anode contact 101 through the bonding metal piece 3021. The N-type semiconductor layer is exposed at the above-mentioned opening 3031, and the exposed part is electrically connected to the common cathode layer 304. The insulating passivation layer 303 is used to insulate and isolate the N-type semiconductor layer 204 and the P-type semiconductor layer 202 in the sub-pixel 20 to avoid short circuit.

[0068] In some embodiments, as Figure 4 shown, the height D of the sub-pixel 20 in the Z direction is 0.3 um to 5 um; preferably, D is 0.3 um to 1.5 um; wherein, the height of the sub-pixel 20 is the distance between its P-type semiconductor layer 202 and N-type semiconductor layer 204 (including the thicknesses of the P-type semiconductor layer 202 and N-type semiconductor layer 204 themselves).

[0069] In some embodiments, the thickness of the P-type ohmic contact layer 201 is 10 nm to 300 nm, and its material can be a transparent conductive thin film such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., or a metal alloy thin film such as AuBe, AnZn, etc.

[0070] In some embodiments, as Figure 11 shown in stage d of [reference], the thickness d1 of the insulating and passivating layer 303 is 30 nm to 500 nm to better ensure the insulation and passivation capabilities.

[0071] In some embodiments, the thickness d2 of the common cathode layer 304 is 50 nm to 500 nm to increase its transmittance as much as possible while ensuring the current spreading ability. The thicker the common cathode layer 304, the better the current spreading, but the lower the transmittance, which will cause greater light loss and increase the processing difficulty. If the thickness is too thin, it will affect the metal current spreading ability.

[0072] In some embodiments, cathode holes 307 are formed on the interface 40 between two adjacent pixel layers, and the cathode holes 307 are filled with cathode connectors 308. The cathode connectors 308 are all electrically connected to the cathode contacts 102, and the common cathode layer 304 in the upper pixel layer is electrically connected to the cathode contacts 102 through the cathode connectors 308 in the lower pixel layer.

[0073] Understandably, when only three pixel layers 30 are arranged, in the specific arrangement, the common cathode layer 304 of the pixel layer of the third layer can be electrically connected to the cathode contact 102 through the cathode connection members 308 in the second layer and the first layer in sequence, the common cathode layer 304 of the second pixel layer can be electrically connected to the cathode contact 102 through the cathode connection members 308 in the first layer in sequence, and the common cathode layer 304 of the first pixel layer can be directly electrically connected to the cathode contact 102; alternatively, the cathode connection member 308 of the second layer can also be directly connected to the cathode contact 102. At this time, the common cathode layer 304 of the third pixel layer can also be directly electrically connected to the cathode contact 102 through the cathode connection member 308 in the second layer. That is to say, the common cathode layer 304 in the pixel layer can be electrically connected to the cathode contact 102 through a plurality of cathode connection members 308 in the lower pixel layer in sequence, or can be directly electrically connected to the cathode contact 102 through the pixel layer of the adjacent lower layer.

[0074] Furthermore, cathode holes 307 are also formed on the interface 40 between two adjacent pixel layers. The top surface of the cathode connection member 308 filled in the cathode hole 307 is lower than the interface 40 to form a recessed portion 3051, or the top surface of the cathode connection member 308 filled in the cathode hole 307 is higher than the interface 40 to form a protruding portion 3061. The recessed portion 3051 / protruding portion 3061 is fitted with the corresponding bonding metal member 3021, which is similar to the setting method of the anode connection member 306 and will not be elaborated here.

[0075] In some embodiments, as Figure 4 shown, in the Z direction, the distance H between the top surface of the insulating body 301 of each pixel layer 30 and the common cathode layer 304 at the top of the sub-pixels 20 in this layer is not less than 100 nm to prevent interlayer leakage caused by insulation abnormalities.

[0076] In some embodiments, the sub-pixels 20 are trapezoidal or cylindrical. Compared with pixels having a hemispherical structure or a semi-ellipsoidal structure, the trapezoidal or cylindrical sub-pixels can effectively increase the pixel light-emitting area, thereby increasing the light-emitting intensity; generally, an active layer 203 is provided in the sub-pixels to emit light. As Figure 1 can be seen, when the bottom dimensions of the sub-pixels are the same, the area of the active layer 203 (the entire shaded part) in the trapezoidal sub-pixel is larger than the area of the active layer in the hemispherical sub-pixel (the shaded part inside the hemisphere), thereby effectively increasing the light-emitting intensity. Similarly, compared with the hemispherical sub-pixel, the cylindrical sub-pixel can also increase the area of the active layer, thereby effectively increasing the light-emitting intensity.

[0077] Furthermore, as Figure 11As shown in the d stage, the inclination angle θ of the side wall of the sub-pixel 20 relative to the driving wafer 10 is 45° to 135°; it can be understood that the side wall of the sub-pixel 20 here refers to the wall surface between the top surface and the bottom surface of the sub-pixel 20;

[0078] The above inclination angle can reduce total reflection and is more conducive to light extraction. Beyond this range, the light extraction efficiency will be reduced; in addition, due to limited horizontal space, a certain space needs to be reserved for subsequent processes. When the inclination angle is too small, the bottom surface of the pixel occupies too much horizontal space, which will increase the difficulty of arranging the pixel pitch.

[0079] Preferably, the inclination angle θ of the side wall of the sub-pixel 20 relative to the driving wafer 10 is 75° to 105°, which has the best light extraction efficiency and the best pixel pitch design.

[0080] In some embodiments, the length of the top end of the anode connector 306 in the X direction is greater than the length of the bottom end, and the X direction and the Z direction are perpendicular. That is, the anode connector 306 has a structure with a wider top and a narrower bottom. When the length of the bottom end is the same, this structure can obtain a thicker anode connector compared with the structure with a narrower top and a wider bottom, thereby enhancing the anode electrical transmission ability.

[0081] In some embodiments, at least one lens 60 is connected to the upper part of the pixel layer 30 located at the top layer, as Figure 2 shown, each sub-pixel 20 corresponds to one lens 60, and this method is used to better collimate the outgoing light of each sub-pixel, further reducing the light interference within the mother pixel. Or, as Figure 5 shown, multiple sub-pixels 20 correspond to one lens 60.

[0082] This embodiment also discloses a method for manufacturing a multi-layer microdisplay chip, including,

[0083] Step M1, preparing a driving wafer 10, and an anode contact 101 is provided on the driving wafer 10;

[0084] Step M2, stacking at least two pixel layers 30 on the driving wafer 10 in the Z direction in sequence. At least one sub-pixel 20 is provided in each pixel layer 30. A bonding metal part 3021 is provided on the side of each sub-pixel 20 close to the driving wafer 10. The bonding metal part 3021 of the sub-pixel 20 in the upper pixel layer is electrically connected to the corresponding anode contact 101 through an anode connector 306 passing through the lower pixel layer. The bonding metal part 3021 has a first contact surface 30211 for contacting the anode connector 306. The first contact surface 30211 is a non-flat surface. The first contact surface 30211 is embedded in the pixel layer where the anode connector 306 is located and contacts the anode connector 306, or the anode connector 306 is embedded in the first contact surface 30211.

[0085] Furthermore, when preparing the pixel layer 30, an anode hole 305 corresponding to the anode connecting member 306 needs to be formed on the interface 40 between two adjacent pixel layers, and the anode connecting member 306 is filled in the anode hole 305. The top surface of the anode connecting member 306 filled in the anode hole 305 is lower than the interface 40 to form a recessed portion 3051. An embedding protrusion 30212 is formed on the first contact surface 30211, so that the embedding protrusion 30212 corresponding to the bonding metal member 3021 of the sub-pixel 20 in the pixel layer is embedded into the recessed portion 3051 of the corresponding anode hole 305 in the adjacent pixel layer below to be in electrical contact with the anode connecting member 306;

[0086] Alternatively, the top surface of the anode connecting member 306 filled in the anode hole 305 is higher than the interface 40 to form a protruding portion 3061. An embedding recess 30213 is formed on the first contact surface 30211, and the embedding recess 30213 corresponding to the bonding metal member 3021 of the sub-pixel in the pixel layer is engaged with the protruding portion 3061 of the corresponding anode connecting member 306 in the adjacent pixel layer below.

[0087] During specific preparation, step M2 includes:

[0088] Step M21: Bond a compound semiconductor 50 on the driving wafer 10;

[0089] As Figure 10 shown, the above-mentioned compound semiconductor 50 includes a P-type ohmic contact layer 201, a P-type semiconductor layer 202, an active layer 203, an N-type semiconductor layer 204, and a substrate 501 which are sequentially arranged in a direction away from the driving wafer. After bonding the compound semiconductor 50 on the driving wafer 10, the substrate 501 needs to be removed to expose the N-type semiconductor layer 204; after removing the substrate 501, an N-type ohmic contact layer 205 can also be provided on the N-type semiconductor layer 204;

[0090] Furthermore, the thickness of the N-type ohmic contact layer 205 is 10 nm to 300 nm, and its material can be a transparent conductive thin film such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., or a metal alloy thin film such as gold germanium alloy (AuGe), gold nickel alloy (AuNi), etc.

[0091] Preferably, the thickness of the N-type ohmic contact layer 205 is 10 nm to 100 nm to ensure ohmic contact while also having a high transmittance, thereby reducing light loss.

[0092] Among them, the compound semiconductor 50 can be bonded to the driving wafer 10 through the bonding layer 302, and the bonding alignment accuracy can be 10 to 500 μm.

[0093] Step M22: Patterning and etching the compound semiconductor 50 to obtain at least one sub-pixel 20, such that the sub-pixel 20 is electrically connected to the corresponding anode contact 101 via the bonding layer 302; the bonding layer 302 includes a plurality of bonding metal members 3021, such that each sub-pixel 20 corresponds to a bonding metal member 3021, and the sub-pixel 20 is electrically connected to the corresponding anode contact 101 via the corresponding bonding metal member 3021;

[0094] Each bonding metal member 3021 is obtained by etching the bonding layer 302; the anode contacts 101 and the sub-pixels 20 correspond one to one, or multiple anode contacts 101 correspond to one sub-pixel 20;

[0095] Step M23: depositing an insulating passivation layer 303 outside the sub-pixel 20 and providing an opening 3031 on the upper portion of the insulating passivation layer 303 to expose the N-type semiconductor layer 204 or the N-type ohmic contact layer 205 of the sub-pixel 20;

[0096] Step M24: deposit a common cathode layer 304 outside the insulating passivation layer 303, so that the sub-pixel 20 is electrically connected to the common cathode layer 304 through the opening 3031, and the common cathode layer 304 is used to be electrically connected to the cathode contact 102, thereby obtaining Figure 11 The structure shown in stage d;

[0097] That is, the N-type semiconductor layer 204 of the sub-pixel 20 is electrically connected to the cathode contact 102 via the common cathode layer 304, thereby achieving cathode connection.

[0098] Among them, only one cathode contact 102 may be provided on the driver wafer 10 , or the number of cathode contacts 102 may be determined according to needs.

[0099] Step M25: Figure 11 As shown in stage e, an insulating body 301 is filled outside the common cathode layer 304 so that all sub-pixels 20 are located inside the insulating body 301 , and an anode connector 306 is prepared in the insulating body 301 , thereby obtaining a pixel layer;

[0100] It can be understood that the insulating passivation layer 303 and the common cathode layer 304 outside the sub-pixel 20 are also located inside the insulating body 301 .

[0101] Step M26: Figure 11As shown in the f stage of the Chinese text, another compound semiconductor 50 is bonded on top of the previous pixel layer 30 through a bonding layer 302, and step M22 is executed. The bonding metal parts 3021 of the sub-pixels in this pixel layer are electrically connected to the corresponding anode contacts through the anode connectors 306 passing through the previous pixel layer. When the bonding metal parts 3021 of the sub-pixels in this layer are connected to the anode connectors 306 of the previous pixel layer, the first contact surface 30211 of the bonding metal part is embedded in the previous pixel layer and contacts the anode connector 306, or the anode connector 306 is embedded in the first contact surface 30211, and then steps M23 - M25 are executed to obtain the next pixel layer;

[0102] Step M27: Repeat step M26 until the preparation of all pixel layers is completed;

[0103] Among them, the light-emitting colors of each sub-pixel 20 in the same pixel layer 30 are the same, and the light-emitting colors of the sub-pixels 20 in two adjacent pixel layers are different.

[0104] It can be understood that the bonding metal parts 3021 between the anode connectors 306 adjacent in the Z direction can be directly used as the conductive metal parts 3022.

[0105] Specifically, three pixel layers can be set so that the light-emitting colors of the sub-pixels in each pixel layer are all different to achieve a three-color configuration. Two pixel layers can also be set, and the light-emitting colors of the sub-pixels in these two pixel layers are different to achieve a two-color configuration. More layers can also be set by continuing to stack on the basis of the three pixel layers.

[0106] For ease of description, the sub-pixel with a light-emitting color of red is called a red sub-pixel, the sub-pixel with a light-emitting color of green is called a green sub-pixel, and the sub-pixel with a light-emitting color of blue is called a blue sub-pixel;

[0107] Then in actual configuration, if only three pixel layers are set, red sub-pixels can be arranged in the first pixel layer (the bottom pixel layer), green sub-pixels in the second pixel layer, and blue sub-pixels in the third pixel layer (the top pixel layer). In actual working conditions, which pixel layer the sub-pixels of different colors are specifically located in can be selected according to needs and is not limited here;

[0108] It can be understood that since the light-emitting colors of the sub-pixels in two adjacent pixel layers are different, the materials of the compound semiconductors 50 used in the preparation of two adjacent pixel layers are also different so that the light-emitting colors of the compound semiconductors 50 used are different; when preparing each pixel layer, the light-emitting color of the selected compound semiconductor is determined according to the actual situation. If a sub-pixel with a light-emitting color of red needs to be prepared, a compound semiconductor with a light-emitting color of red is selected.

[0109] Among them, the compound semiconductor 50 uses inorganic compound materials. For example, the compound semiconductor corresponding to the blue light pixel layer uses InGaN material, the compound semiconductor corresponding to the green light pixel layer uses InGaN material, and the compound semiconductor corresponding to the red light pixel layer uses InGaN or AlGaInP material.

[0110] In practical applications, the film layers of the compound semiconductor will be more complex, or there may be cross - use of materials. A typical compound semiconductor structure mainly includes a P - type semiconductor layer 202, an N - type semiconductor layer 204, and an active layer 203 (MQW active quantum well) and other functional layers sandwiched between them. For the film layer materials of the red compound semiconductor, please refer to Table 1, and for the film layer materials of the green and blue compound semiconductors, please refer to Table 2.

[0111] Table 1 Film Layer Materials of Compound Semiconductor (R)

[0112]

[0113]

[0114] Table 2 Film Layer Materials of Compound Semiconductor (G / B)

[0115] Layer Name Material Material Material P - type Semiconductor Layer GaN GaN GaN MQW Active Quantum Well InGaN InGaN InGaN N - type Semiconductor Layer GaN GaN GaN Substrate GaN Si Sapphire

[0116] In one of the embodiments, the insulating and passivating layer 303 can be made of one or more of alumina, silica, and silicon nitride.

[0117] In one of the embodiments, the insulating body 301 can be made of one or more of silicon oxide, silicon nitride, silicon carbide (SiC), silicon carbonitride (SiCN), phosphate glass (PSG), and borophosphosilicate glass (BPSG).

[0118] In one of the embodiments, the common cathode layer 304 includes one or more of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum - doped zinc oxide (AZO), aluminum - doped indium tin oxide, silver - doped indium tin oxide, and gold - doped indium tin oxide.

[0119] In one of the embodiments, the material of the anode connector 306 can be one or more of aluminum, copper, and tungsten.

[0120] Furthermore, the material of the cathode connector 308 can be the same as that of the anode connector 306, as long as it is a conductive material.

[0121] In one embodiment, the bonding metal member 3021 may be made of one of Al, Au, and Cu, or a laminated structure of Ni, Au, Cu, etc. and Sn, or a bonding laminate of Au and In, Ge, or a bonding laminate of Au and Si.

[0122] Furthermore, the bonding metal member 3021 may adopt the following structural form: Cr 2nm / Pt 50nm / Ti 10nm / Pt 50nm / Au 100nm / Sn 150nm / Au 50nm, where Cr is the adhesion layer and Pt / Ti / Pt is the barrier layer.

[0123] In some embodiments, after step M2, as Figure 11 shown in the h stage, a dielectric layer is further deposited on the upper part of the pixel layer located at the top layer, and the dielectric layer is patterned and etched to form a lens 60, so that each sub-pixel 20 corresponds to the lens 60 one by one, or multiple sub-pixels 20 correspond to one lens 60.

[0124] For the multi-layer and multi-color microdisplay chip and its manufacturing method in the above embodiments, through the interlocking method, the bonding metal member and the anode connecting member are in full contact, thus effectively ensuring the reliability of the anode current transmission; it also effectively ensures the connection strength between the bonding metal member and the anode connecting member, and at the same time is more conducive to the alignment and positioning of the two.

[0125] All the above optional technical solutions can be combined arbitrarily to form optional embodiments of the present invention, that is, any number of embodiments can be combined to meet the requirements of different application scenarios, and all are within the protection scope of this application, and will not be elaborated one by one here.

[0126] It should be noted that the above embodiments are only examples for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims

1. A multi-layer multi-color microdisplay chip, characterized in that: Comprising, a driving wafer, on which an anode contact is provided; at least two layers of pixel layers, all the pixel layers are sequentially stacked along the Z direction on the driving wafer, at least one sub-pixel is provided in each pixel layer, and a bonding metal part is provided on one side of each sub-pixel close to the driving wafer. The bonding metal part of the sub-pixel in the upper pixel layer is electrically connected to the corresponding anode contact by an anode connecting part passing through the lower pixel layer. The bonding metal part of the sub-pixel in the upper pixel layer has a first contact surface for contacting the anode connecting part. The first contact surface is a non-flat surface. The first contact surface is embedded in the pixel layer where the anode connecting part is located and contacts the anode connecting part, or the anode connecting part is embedded in the first contact surface; wherein, the light-emitting colors of each sub-pixel in the same pixel layer are the same, and the light-emitting colors of the sub-pixels in two adjacent pixel layers are different.

2. The multi-layer and multi-color microdisplay chip according to claim 1, characterized in that: The projections of all the sub-pixels on the driving wafer do not overlap.

3. The multi-layer and multi-color microdisplay chip according to claim 1, wherein: An anode hole corresponding to the anode connecting part is formed on the interface between two adjacent pixel layers. The anode hole is filled with an anode connecting part. The top surface of the anode connecting part filled in the anode hole is lower than the interface to form a recessed part. An embedding protrusion is formed on the first contact surface. The embedding protrusion of the sub-pixel in the pixel layer is embedded in the recessed part of the corresponding anode hole in the adjacent pixel layer below to be electrically contacted with the anode connecting part; or, the top surface of the anode connecting part filled in the anode hole is higher than the interface to form a protruding part. An embedding recess is formed on the first contact surface. The embedding recess of the sub-pixel in the pixel layer is fitted with the protruding part of the corresponding anode connecting part in the adjacent pixel layer below.

4. The multi-layer multi-color microdisplay chip according to claim 3, wherein: The height of the recessed part is 10 nm to 300 nm, and the height of the protruding part is 10 nm to 300 nm.

5. The multi-layer and multi-color microdisplay chip according to claim 3, characterized in that: Comprising at least three layers of the pixel layers. The bonding metal parts of the sub-pixels in the pixel layers of the third layer and above are electrically connected to the corresponding anode contacts by a plurality of anode connecting parts sequentially connected along the Z direction below. Each of the anode connecting parts sequentially connected along the Z direction is located in a different pixel layer. Two adjacent anode connecting parts among the anode connecting parts sequentially connected along the Z direction are in direct contact; or, a conductive metal part is provided between two adjacent anode connecting parts.

6. The multi-layer and multi-color microdisplay chip according to claim 3, wherein: The inclination angle of the inner wall of the anode hole with respect to the top surface of the driving wafer is 90° to 120°.

7. The multi-layer multi-color microdisplay chip according to claim 1, characterized in that: A cathode contact is further provided on the driving wafer. Each pixel layer includes an insulating body. The sub-pixels in the pixel layer are all located inside the insulating body. An insulating passivation layer is coated outside each sub-pixel. The bonding metal part of the sub-pixel is located inside the insulating passivation layer. An opening is provided in the upper part of the insulating passivation layer. A common cathode layer is coated outside the insulating passivation layer. The sub-pixel is electrically connected to the common cathode layer through the opening. The common cathode layer is used for being electrically connected to the cathode contact.

8. The multi-layer multi-color micro-display chip according to claim 7, characterized in that: Each sub-pixel includes a P-type semiconductor layer, an active layer, and an N-type semiconductor layer sequentially arranged along the Z direction. The bonding metal parts are provided on one side of the P-type semiconductor layer close to the driving wafer, and the N-type semiconductor layer is electrically connected to the common cathode layer through the opening.

9. The multi-layer multi-color microdisplay chip according to claim 7, characterized in that: Cathode holes are formed on the interface between two adjacent pixel layers, and cathode connectors are filled in the cathode holes. The cathode connectors are all electrically connected to cathode contacts, and the common cathode layer in the upper pixel layer is electrically connected to the cathode contacts through the cathode connectors in the lower pixel layer.

10. The multi-layer multi-color microdisplay chip according to claim 7, characterized in that: The distance between the top surface of the insulating body of each pixel layer and the common cathode layer at the top of the sub-pixels in this layer is not less than 100 nm.

11. The multi-layer multi-color micro-display chip according to claim 7, wherein: The thickness of the common cathode layer is 50 nm to 500 nm.

12. The multi-layer multi-color microdisplay chip according to claim 1, wherein: The sub-pixels are trapezoidal or cylindrical.

13. The multi-layer and multi-color micro-display chip according to claim 1, wherein: The length of the top end of the anode connector in the X direction is greater than the length of the bottom end, and the X direction is perpendicular to the Z direction.

14. The multi-layer multi-color microdisplay chip according to claim 1, wherein: At least one lens is connected to the upper part of the pixel layer located at the top layer, and each sub-pixel corresponds to one lens, or multiple sub-pixels correspond to one lens.

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