Multilayer micro-display chip

Abstract

The utility model relates to a multilayer micro-display chip, which comprises a driving wafer and at least two pixel layers, and an anode contact is arranged on the driving wafer. All the pixel layers are sequentially stacked on the driving wafer in the Z direction, at least one sub-pixel is arranged in each pixel layer, a bonding metal piece is arranged on the side, close to the driving wafer, of each sub-pixel, the bonding metal piece of the sub-pixel in the upper pixel layer is electrically connected to the corresponding anode contact through an anode connecting piece penetrating through the lower pixel layer, and the bonding metal piece of the sub-pixel in the lower pixel layer is electrically connected to the corresponding anode contact through an anode connecting piece penetrating through the lower pixel layer. The bonding metal piece of the sub-pixel in the upper pixel layer is provided with a first contact surface, the first contact surface is a non-flat surface, the first contact surface is embedded into the pixel layer where the anode connecting piece is located and is in contact with the anode connecting piece, or the anode connecting piece is embedded into the first contact surface. According to the utility model, the bonding metal piece and the anode connecting piece are fully contacted, so that the reliability of anode current transmission is effectively ensured.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor technology, in particular to a multi-layer microdisplay chip. Background Art

[0002] In the field of LED display, microdisplay technology has been widely developed in recent years, especially Micro-LED display technology, which has the advantages of high efficiency, low power consumption, high integration and high stability, and is considered to be one of the most promising next-generation new display and lighting devices. Micro-LED display technology has now been widely used in near-eye display terminal products, including virtual reality (VR), augmented reality (AR), mixed reality (MR), etc. In the existing microdisplay chip, a plurality of pixel units arranged in an array are usually arranged in the display area. In order to further reduce the horizontal size of the microdisplay chip and increase the pixel density, in the prior art, the chip can be set into a vertically stacked multi-layer structure, and each layer is provided with light-emitting pixel units. In such a multi-layer structure, adjacent layers generally need to be bonded through a bonding layer, and the pixel units of the upper layer are connected to the anode connectors of the lower layer through the bonding layer, so as to realize the connection between the pixel units and the anode of the driving wafer through the anode connectors. However, in the existing structure, gaps are easily generated between the bonding layer and the anode connectors in adjacent layers, resulting in poor contact between the two and affecting electrical transmission, which cannot meet the use requirements. Summary of the Utility Model

[0003] Therefore, the technical problem to be solved by the present utility model is to overcome the defect that the contact between the bonding layer and the anode connectors in the prior art is easily poor, which affects electrical transmission.

[0004] To solve the above technical problem, the present utility model provides a multi-layer microdisplay chip, including,

[0005] A driving wafer, on which an anode contact is provided;

[0006] At least two pixel layers, all the pixel layers are sequentially stacked on the driving wafer along the Z direction, at least one sub-pixel is provided in each pixel layer, and a bonding metal part is provided on one side of each sub-pixel close to the driving wafer. The bonding metal part of the sub-pixel in the upper pixel layer is electrically connected to the corresponding anode contact through the anode connector passing through the lower pixel layer. The bonding metal part of the sub-pixel in the upper pixel layer has a first contact surface for contacting the anode connector. The first contact surface is a non-flat surface. The first contact surface is embedded in the pixel layer where the anode connector is located and contacts the anode connector, or the anode connector is embedded in the first contact surface.

[0007] In one embodiment of the present utility model, an anode hole corresponding to the anode connecting member is formed on the interface between two adjacent pixel layers. The anode hole is filled with an anode connecting member, and the top surface of the anode connecting member filled in the anode hole is lower than the interface to form a recess. An embedding protrusion is formed on the first contact surface, and the embedding protrusion of the sub-pixel in the pixel layer is embedded in the recess of the corresponding anode hole in the adjacent pixel layer below to be in electrical contact with the anode connecting member; or,

[0008] the top surface of the anode connecting member filled in the anode hole is higher than the interface to form a protrusion, and an embedding recess is formed on the first contact surface. The embedding recess of the sub-pixel in the pixel layer is fitted with the protrusion of the corresponding anode connecting member in the adjacent pixel layer below.

[0009] In one embodiment of the present utility model, the height of the recess is 10 nm to 300 nm, and the height of the protrusion is 10 nm to 300 nm.

[0010] In one embodiment of the present utility model, at least three layers of the pixel layers are included. The bonding metal parts of the sub-pixels in the third and higher pixel layers are electrically connected to the corresponding anode contacts by a plurality of anode connecting members sequentially connected along the Z direction below. Each of the anode connecting members sequentially connected along the Z direction is located in a different pixel layer, and two adjacent anode connecting members among the anode connecting members sequentially connected along the Z direction are in direct contact; or, a conductive metal part is arranged between two adjacent anode connecting members.

[0011] In one embodiment of the present utility model, the inclination angle of the inner wall of the anode hole relative to the top surface of the driving wafer is 90° to 120°.

[0012] In one embodiment of the present utility model, a cathode contact is further arranged on the driving wafer. Each pixel layer includes an insulating body. The sub-pixels in the pixel layer are all coated inside the insulating body. An insulating passivation layer is coated outside each sub-pixel. The bonding metal part of the sub-pixel is located inside the insulating passivation layer. An opening is formed in the upper part of the insulating passivation layer. A common cathode layer is coated outside the insulating passivation layer. The sub-pixel is electrically connected through the opening and the common cathode layer, and the common cathode layer is used for electrical connection with the cathode contact.

[0013] In one embodiment of the present utility model, each sub-pixel includes a P-type semiconductor layer, an active layer, and an N-type semiconductor layer sequentially arranged along the Z direction. The bonding metal part is arranged on one side of the P-type semiconductor layer close to the driving wafer, and the N-type semiconductor layer is electrically connected through the opening and the common cathode layer.

[0014] In an embodiment of the present utility model, a cathode hole is formed on the interface between two adjacent pixel layers. The cathode hole is filled with a cathode connecting member, and all the cathode connecting members are electrically connected to a cathode contact. The common cathode layer in the upper pixel layer is electrically connected to the cathode contact through the cathode connecting member in the lower pixel layer.

[0015] In an embodiment of the present utility model, the distance between the top surface of the insulating body of each pixel layer and the common cathode layer at the top of the sub-pixels in this layer is not less than 100 nm.

[0016] In an embodiment of the present utility model, the sub-pixels are trapezoidal or cylindrical.

[0017] In an embodiment of the present utility model, the light-emitting colors of each sub-pixel in the same pixel layer are the same, and the light-emitting colors of the sub-pixels in two adjacent pixel layers are different.

[0018] In an embodiment of the present utility model, the light-emitting colors of the sub-pixels in each pixel layer are all the same.

[0019] In an embodiment of the present utility model, the multi-layer microdisplay chip further includes a color conversion member. The color conversion member is located in a pixel layer, and excitation pixels are arranged in the adjacent pixel layer below the pixel layer where the color conversion member is located. The color conversion member is located on the light-emitting path of the excitation pixels.

[0020] In an embodiment of the present utility model, at least one lens is connected to the upper part of the pixel layer located at the top layer. Each sub-pixel corresponds to one lens, or multiple sub-pixels correspond to one lens.

[0021] The above technical solution of the present utility model has the following advantages compared with the prior art:

[0022] For the multi-layer microdisplay chip of the present utility model, through the way of mutual embedding, the bonding metal member and the anode connecting member are in full contact, thus effectively ensuring the reliability of the anode current transmission; and also effectively ensuring the connection strength between the bonding metal member and the anode connecting member. Description of the Drawings

[0023] In order to make the content of the present utility model easier to be clearly understood, the following further details the present utility model according to the specific embodiments of the present utility model in combination with the drawings.

[0024] Figure 1 It is a comparison schematic diagram of trapezoidal sub-pixels and hemispherical sub-pixels;

[0025] Figure 2 It is the internal structure diagram of the first multi-layer microdisplay chip of the present utility model;

[0026] Figure 3 is Figure 2 Internal enlarged schematic diagram at U in

[0027] Figure 4 is Figure 2 Arrangement schematic diagram of the bottom pixel layer in

[0028] Figure 5 Internal structure diagram of the second multi - layer micro - display chip of the present utility model;

[0029] Figure 6 Internal structure diagram of the third multi - layer micro - display chip of the present utility model;

[0030] Figure 7 is Figure 6 Internal enlarged schematic diagram at V in

[0031] Figure 8 is Figure 6 Arrangement schematic diagram of the bottom pixel layer in

[0032] Figure 9 Internal structure diagram of the fourth multi - layer micro - display chip of the present utility model;

[0033] Figure 10 Partial preparation flow chart of the chip of the present utility model;

[0034] Figure 11 is Figure 2 Preparation flow chart of the structure shown;

[0035] Figure 12 Internal structure diagram of the fifth multi - layer micro - display chip of the present utility model;

[0036] Figure 13 Internal structure diagram of the sixth multi - layer micro - display chip of the present utility model;

[0037] Explanation of reference numerals in the specification drawings:

[0038] 10. Driving wafer; 101. Anode contact; 102. Cathode contact;

[0039] 20. Sub - pixel; 201. P - type ohmic contact layer; 202. P - type semiconductor layer; 203. Active layer; 204. N - type semiconductor layer; 205. N - type ohmic contact layer;

[0040] 30. Pixel layer; 301. Insulating body; 302. Bonding layer; 3021. Bonding metal part; 30211. First contact surface; 30212. Embedded protrusion; 30213. Embedded depression; 3022. Conductive metal part; 303. Insulating passivation layer; 3031. Opening; 304. Common cathode layer; 305. Anode hole; 3051. Depressed part; 306. Anode connecting part; 3061. Protruding part; 307. Cathode hole; 308. Cathode connecting part; 309. Filling hole; 310. Isolation layer;

[0041] 40. Interface;

[0042] 50. Excited pixel;

[0043] 60. Color conversion part;

[0044] 70. Compound semiconductor; 701. Substrate;

[0045] 80. Lens; Detailed implementation mode

[0046] The present utility model will be further described below in conjunction with the accompanying drawings and specific embodiments, so that those skilled in the art can better understand the present utility model and be able to implement it, but the embodiments cited are not used as a limitation to the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and in no way a limitation to the present disclosure and its application or use.

[0047] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "vertical", "upper", "lower", "top", "side", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present utility model. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present utility model, unless otherwise specified, the meaning of "a plurality" is two or more.

[0048] The following will be combined with Figures 1 - 13 , and the structure of the multi-layer microdisplay chip of this embodiment will be further described.

[0049] It should be noted that for the convenience of description, in the microdisplay chip of the present utility model, there are Z direction and X direction perpendicular to each other. Generally, the Z direction is the direction away from the driving wafer. In the present utility model, "up" and "down" are relative in the Z direction. Similarly, "top", "bottom" or "high", "low" are also relative in the Z direction. The top pixel layer refers to the uppermost pixel layer, and the bottom pixel layer refers to the lowermost pixel layer. Among them, the bottom pixel layer is also called the first pixel layer, and the pixel layers stacked in sequence above are the second layer, the third layer, and so on in sequence.

[0050] Embodiment 1

[0051] Refer to Figures 2 - 4 , this embodiment discloses a multi-layer microdisplay chip, including a driving wafer 10 and at least two layers of pixel layers 30; the driving wafer 10 can adopt a CMOS driving wafer, which is used to control the sub-pixels 20 in the pixel layer 30 to emit light;

[0052] Among them, an anode contact 101 is arranged on the driving wafer 10;

[0053] All the pixel layers 30 are stacked in sequence along the Z direction on the driving wafer 10. At least one sub-pixel 20 is arranged in each pixel layer 30. A bonding metal part 3021 is arranged on the side of each sub-pixel 20 close to the driving wafer 10. The bonding metal part 3021 of the sub-pixel 20 in the upper pixel layer is electrically connected to the corresponding anode contact 101 through an anode connecting part 306 passing through the lower pixel layer to realize anode connection;

[0054] The bonding metal part 3021 has a first contact surface 30211, and the first contact surface 30211 is used to contact the anode connecting part 306. The first contact surface 30211 is a non-flat surface. The first contact surface 30211 is embedded in the pixel layer 30 where the anode connecting part 306 is located and contacts the anode connecting part 306, or the anode connecting part 306 is embedded in the first contact surface 30211.

[0055] Among them, the light emitting colors of each sub-pixel 20 in the same pixel layer are the same, and the light emitting colors of the sub-pixels 20 in two adjacent pixel layers are different.

[0056] In the above structure, when the bonding metal part 3021 of the sub-pixel 20 in the upper pixel layer is connected to the anode connecting part 306 of the lower pixel layer, the contact surface between the bonding metal part 3021 and the anode connecting part 306 is a non-flat surface, so that the first contact surface 30211 is embedded into the pixel layer 30 where the anode connecting part 306 is located and contacts the anode connecting part 306, or the anode connecting part 306 is embedded into the first contact surface 30211. This form of fitting structure can effectively avoid the bonding gap or void between the bonding metal part 3021 and the anode connecting part 306, enabling the bonding metal part 3021 and the anode connecting part 306 to be in full contact, thus effectively ensuring the reliability of anode current transmission. Additionally, adopting the above mutually fitting structure also effectively guarantees the connection strength between the bonding metal part 3021 and the anode connecting part 306 and is more conducive to alignment and positioning.

[0057] Among them, the bonding metal part 3021 can correspond to the anode contact 101 one by one, or multiple anode contacts 101 can correspond to one bonding metal part 3021.

[0058] In some embodiments, as Figures 2 - 4 shown, an anode hole 305 corresponding to the anode connecting part 306 is formed on the interface 40 between two adjacent pixel layers. The anode hole 305 is filled with the anode connecting part 306. The top surface of the anode connecting part 306 filled in the anode hole 305 is lower than the interface 40 to form a recessed part 3051. An embedding protrusion 30212 is formed on the first contact surface 30211. The embedding protrusion 30212 on the bonding metal part 3021 of the sub-pixel in the pixel layer is embedded into the recessed part 3051 of the corresponding anode hole 305 in the adjacent lower pixel layer to be in electrical contact with the anode connecting part 306;

[0059] Or, as Figures 6 - 8 shown, the top surface of the anode connecting part 306 filled in the anode hole 305 is higher than the interface 40 to form a protruding part 3061. An embedding recess 30213 is formed on the first contact surface 30211. The embedding recess 30213 of the bonding metal part 3021 of the sub-pixel in the pixel layer is fitted with the protruding part 3061 of the corresponding anode connecting part 306 in the adjacent lower pixel layer. This method is more convenient for processing. Through the above convex-concave fitting method, excellent electrical transmission effects can be effectively guaranteed.

[0060] In addition, compared with making the interface between two adjacent pixel layers into a completely flat structure, the above interface with convex-concave characteristics is easier to process, simplifies the processing technology, and is more conducive to mass production of products.

[0061] Furthermore, as Figure 4 shown, the height h1 of the recessed part 3051 is 10 nm to 300 nm, as Figure 8As shown, the height h2 of the convex portion 3061 is 10 nm to 300 nm, so as to better avoid bonding voids and ensure the electrical transmission effect. The above height should not be too large, as an overly large height will easily increase the process difficulty. If the height is too small, the electrical transmission effect cannot be better ensured.

[0062] Furthermore, the projections of all sub-pixels 20 on the driving wafer 10 do not overlap, so as to avoid crosstalk between sub-pixels 20 or color noise phenomena caused by photoexcitation to the greatest extent, thereby more precisely controlling the light combining effect.

[0063] In some embodiments, it includes at least three pixel layers 30. The bottom pixel layer is also called the first pixel layer, and the pixel layers stacked above it are the second layer, the third layer, and so on in sequence. Then, the bonding metal parts 3021 of the sub-pixels in the pixel layers of the third layer and above are electrically connected to the corresponding anode contacts 101 by a plurality of anode connectors 306 connected in sequence along the Z direction. Each of the anode connectors 306 connected in sequence along the Z direction is located in different pixel layers;

[0064] Among them, adjacent two of the anode connectors 306 connected in sequence along the Z direction are in direct contact. As Figure 9 shown, this method does not retain the bonding metal parts and other components between adjacent two anode connectors 306. This method is more conducive to avoiding poor electrical transmission caused by bonding voids;

[0065] Or, as Figure 2 shown, it is also possible to provide a conductive metal part 3022 between adjacent two anode connectors 306. This method retains the bonding metal part between the two anode connectors 306 as the conductive metal part 3022, and the processing technology is simpler.

[0066] In some embodiments, the length of the top end of the anode connector 306 in the X direction is greater than the length of the bottom end, that is, it has a structure with a wider top and a narrower bottom. When the length of the bottom end is the same, this shaped structure can obtain a thicker anode connector 306 compared to the structure with a narrower top and a wider bottom, thereby enhancing the anode electrical transmission ability.

[0067] In some embodiments, the length of the top end (in the X direction) of the anode hole 305 is greater than the length of the bottom end.

[0068] In some embodiments, as Figure 4 shown, the inclination angle φ of the inner wall of the anode hole 305 relative to the top surface of the driving wafer 10 is 90° to 120°.

[0069] Furthermore, the anode hole 305 can be trapezoidal; it can also be Y-shaped.

[0070] In some embodiments, a cathode contact 102 is further provided on the driving wafer 10. Each pixel layer 30 includes an insulating body 301. The sub-pixels 20 in the pixel layer 30 are all covered inside the insulating body 301. An insulating passivation layer 303 is covered outside each sub-pixel 20. The bonding metal part 3021 of the sub-pixel 20 is located inside the insulating passivation layer 303. An opening 3031 is provided in the upper part of the insulating passivation layer 303. A common cathode layer 304 is covered outside the insulating passivation layer 303. The sub-pixel 20 is electrically connected to the common cathode layer 304 through the opening 3031, and the common cathode layer 304 is used to be electrically connected to the cathode contact 102.

[0071] Among them, each sub-pixel 20 includes a P-type semiconductor layer 202, an active layer 203, and an N-type semiconductor layer 204 arranged in sequence along the Z direction. The active layer 203 is used to emit light. The P-type semiconductor layer 202 is used to be connected to the anode of the driving wafer 10 to achieve anode connection, and the N-type semiconductor layer 204 is used to be connected to the cathode of the driving wafer 10 to achieve cathode connection.

[0072] Further, the sub-pixel 20 includes a P-type ohmic contact layer 201, a P-type semiconductor layer 202, an active layer 203, and an N-type semiconductor layer 204 arranged in sequence upward along the Z direction. A bonding metal part 3021 is provided on one side of the P-type semiconductor layer 202 close to the driving wafer 10. A P-type ohmic contact layer 201 is provided between the P-type semiconductor layer 202 and the bonding metal part 3021 to achieve ohmic contact between the P-type semiconductor layer 202 and the bonding metal part 3021. Thus, finally, the P-type semiconductor layer 202 is electrically connected to the corresponding anode contact 101 through the bonding metal part 3021. The N-type semiconductor layer is exposed at the above-mentioned opening 3031, and the exposed part is electrically connected to the common cathode layer 304. The insulating passivation layer 303 is used to insulate and isolate the N-type semiconductor layer 204 and the P-type semiconductor layer 202 in the sub-pixel 20 to avoid short circuit.

[0073] In some embodiments, as Figure 4 shown, the height D of the sub-pixel 20 in the Z direction is 0.3 um to 5 um; preferably, D is 0.3 um to 1.5 um; among them, the height of the sub-pixel 20 is the distance between its P-type semiconductor layer 202 and N-type semiconductor layer 204 (including the thicknesses of the P-type semiconductor layer and the N-type semiconductor layer itself).

[0074] In some embodiments, the thickness of the P-type ohmic contact layer 201 is 10 nm to 300 nm, and its material can be a transparent conductive film such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or a metal alloy film such as AuBe or AnZn.

[0075] In some embodiments, asFigure 11 As shown in Stage d, the thickness d1 of the insulating passivation layer 303 is 30 nm to 500 nm to preferably ensure the insulating and passivation capabilities.

[0076] In some embodiments, the thickness d2 of the common cathode layer 304 is 50 nm to 500 nm to increase its transmittance as much as possible while ensuring the current spreading ability. The thicker the common cathode layer 304, the better the current spreading, but the lower the transmittance, which will cause greater optical loss and increase the processing difficulty at the same time. If the thickness is too thin, it will affect the metal current spreading ability.

[0077] In some embodiments, cathode holes 307 are formed on the interface 40 between two adjacent pixel layers. The cathode holes 307 are filled with cathode connectors 308, and the cathode connectors 308 are all electrically connected to the cathode contacts 102. The common cathode layer 304 in the upper pixel layer is electrically connected to the cathode contacts 102 through the cathode connectors 308 and the cathode contacts 102 in the lower pixel layer.

[0078] It can be understood that when only three pixel layers are arranged, in the specific arrangement, the common cathode layer 304 of the third pixel layer can be electrically connected to the cathode contacts 102 through the cathode connectors 308 and the cathode contacts 102 in the second and first layers in sequence. The common cathode layer 304 of the second pixel layer can be electrically connected to the cathode contacts 102 through the cathode connectors 308 and the cathode contacts 102 in the first layer in sequence. The common cathode layer 304 of the first pixel layer can be directly electrically connected to the cathode contacts 102; or, the cathode connectors 308 of the second layer can be directly connected to the cathode contacts 102. At this time, the common cathode layer 304 of the third pixel layer 30 can also be directly electrically connected to the cathode contacts 102 through the cathode connectors 308 and the cathode contacts 102 in the second layer. That is, the common cathode layer 304 in the pixel layer can be electrically connected to the cathode contacts 102 through multiple cathode connectors 308 and the cathode contacts 102 in the lower pixel layer in sequence, or can be directly electrically connected to the cathode contacts 102 through the pixel layer of the adjacent lower layer.

[0079] Furthermore, cathode holes 307 are also formed on the interface 40 between two adjacent pixel layers. The top surface of the cathode connector 308 filled in the cathode hole 307 is lower than the interface 40 to form a recessed portion 3051, or the top surface of the cathode connector 308 filled in the cathode hole 307 is higher than the interface 40 to form a protruding portion 3061. The recessed portion 3051 / protruding portion 3061 is engaged with the corresponding bonding metal part 3021. This is similar to the setting method of the anode connector 306 and will not be elaborated here.

[0080] In some embodiments, such as Figure 4As shown, in the Z direction, the distance H between the top surface of the insulating body 301 of each pixel layer 30 and the common cathode layer 304 at the top of the sub-pixels 20 in this layer is not less than 100 nm to prevent interlayer leakage caused by insulation abnormalities.

[0081] In some embodiments, the sub-pixels 20 are trapezoidal or cylindrical. Compared with pixels having a hemispherical structure or a semi-ellipsoidal structure, the trapezoidal or cylindrical sub-pixels can effectively increase the light-emitting area of the pixels, thereby increasing the light-emitting intensity; generally, an active layer 203 is provided in the sub-pixels to emit light. As can be seen, Figure 1 when the bottom dimensions of the sub-pixels are the same, the area of the active layer 203 (the entire shaded part) in the trapezoidal sub-pixel is larger than the area of the active layer of the hemispherical sub-pixel (the shaded part inside the hemisphere), thereby effectively increasing the light-emitting intensity. Similarly, compared with the hemispherical sub-pixel, the cylindrical sub-pixel can also increase the area of the active layer 203, thereby effectively increasing the light-emitting intensity.

[0082] Furthermore, as Figure 11 shown in stage d in the figure, the inclination angle θ of the side wall of the sub-pixel 20 relative to the driving wafer 10 is 45° to 135°; it can be understood that the side wall of the sub-pixel 20 here refers to the wall surface between the top surface and the bottom surface of the sub-pixel 20;

[0083] The above inclination angle can reduce total reflection and is more conducive to light extraction. Beyond this range, the light extraction efficiency will be reduced; in addition, due to limited horizontal space, a certain space needs to be reserved for subsequent processes. When the inclination angle is too small, the bottom surface of the pixel occupies too much horizontal space, which will increase the difficulty of arranging the pixel pitch.

[0084] Preferably, the inclination angle θ of the side wall of the sub-pixel 20 relative to the driving wafer 10 is 75° to 105°, which has the best light extraction efficiency and the best pixel pitch design.

[0085] In some embodiments, at least one lens 80 is connected to the upper part of the pixel layer 30 at the top layer. As Figure 2 shown, each sub-pixel 20 corresponds to one lens 80, and this method is used to better collimate the emitted light of each sub-pixel 20 and further reduce the light interference within the mother pixel. Or, as Figure 5 shown, multiple sub-pixels 20 correspond to one lens 80.

[0086] This embodiment also discloses a method for manufacturing a multi-layer microdisplay chip, including,

[0087] Step M1: Prepare a driving wafer 10, and an anode contact 101 is provided on the driving wafer 10;

[0088] Step M2: At least two pixel layers 30 are stacked in sequence along the Z direction on the driving wafer 10, and at least one sub-pixel 20 is provided in each pixel layer 30. A bonding metal part 3021 is provided on the side of each sub-pixel 20 close to the driving wafer 10. The bonding metal part 3021 of the sub-pixel 20 in the upper pixel layer is electrically connected to the corresponding anode contact 101 by the anode connector 306 passing through the lower pixel layer. The bonding metal part 3021 has a first contact surface 30211 for contacting the anode connector 306. The first contact surface 30211 is a non-flat surface. The first contact surface 30211 is embedded in the pixel layer where the anode connector 306 is located and contacts the anode connector 306, or the anode connector 306 is embedded in the first contact surface 30211.

[0089] Furthermore, when preparing the pixel layer 30, an anode hole 305 corresponding to the anode connector 306 is formed on the interface 40 between two adjacent pixel layers, and the anode connector 306 is filled in the anode hole 305. The top surface of the anode connector 306 filled in the anode hole 305 is lower than the interface 40, forming a recessed portion 3051. An embedding protrusion 30212 is formed on the first contact surface 30211, so that the embedding protrusion 30212 corresponding to the bonding metal part 3021 of the sub-pixel in the pixel layer is embedded in the recessed portion 3051 of the corresponding anode hole 305 of the adjacent pixel layer below, thereby electrically contacting the anode connector 306.

[0090] Alternatively, the top surface of the anode connector 306 filled in the anode hole 305 is higher than the interface 40 to form a protrusion 3061, and an embedded recess 30213 is formed on the first contact surface 30211. The embedded recess 30213 corresponding to the bonding metal part 3021 of the sub-pixel in the pixel layer is embedded with the protrusion 3061 of the corresponding anode connector 306 of the adjacent pixel layer below.

[0091] During the specific preparation, step M2 includes:

[0092] Step M21: bonding a compound semiconductor 70 to the driver wafer 10;

[0093] like Figure 10 As shown, the compound semiconductor 70 includes a P-type ohmic contact layer 201, a P-type semiconductor layer 202, an active layer 203, an N-type semiconductor layer 204, and a substrate 701, which are sequentially arranged away from the driver wafer. After the compound semiconductor 70 is bonded to the driver wafer 10, the substrate 701 needs to be removed to expose the N-type semiconductor layer 204. After removing the substrate 701, an N-type ohmic contact layer 205 can also be arranged on the N-type semiconductor layer 204.

[0094] Further, the thickness of the N-type ohmic contact layer 205 is in the range of 10 nm to 300 nm, and its material can be a transparent conductive thin film such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or a metal alloy thin film such as gold germanium alloy (AuGe), gold nickel alloy (AuNi), etc.

[0095] Preferably, the thickness of the N-type ohmic contact layer 205 is 10 nm to 100 nm to ensure ohmic contact while also having a high transmittance, thereby reducing optical loss.

[0096] Among them, the compound semiconductor 70 can be bonded to the driving wafer 10 through the bonding layer 302, and the bonding alignment accuracy can be 10 to 500 μm.

[0097] Step M22: Pattern etch the compound semiconductor 70 to obtain at least one sub-pixel 20, so that the sub-pixel 20 is electrically connected to the corresponding anode contact 101 through the bonding layer 302; the bonding layer 302 includes a plurality of bonding metal parts 3021, so that each sub-pixel 20 corresponds to a bonding metal part 3021, and the sub-pixel 20 is electrically connected to the corresponding anode contact 101 through the corresponding bonding metal part 3021;

[0098] Among them, each bonding metal part 3021 is obtained by etching the bonding layer 302; here, the anode contacts 101 and the sub-pixels 20 are in one-to-one correspondence, or multiple anode contacts 101 can correspond to one sub-pixel 20;

[0099] Step M23: Deposit an insulating passivation layer 303 outside the sub-pixel 20, and set an opening 3031 on the upper part of the insulating passivation layer 303 to expose the N-type semiconductor layer 204 or the N-type ohmic contact layer 205 of the sub-pixel 20;

[0100] Step M24: Deposit a common cathode layer 304 outside the insulating passivation layer 303, so that the sub-pixel 20 is electrically connected to the common cathode layer 304 through the opening 3031, and the common cathode layer 304 is used to be electrically connected to the cathode contact 102, obtaining Figure 11 the structure shown in stage d;

[0101] That is, the N-type semiconductor layer 204 of the sub-pixel 20 is electrically connected to the cathode contact 102 through the common cathode layer 304 to achieve cathode connection;

[0102] Among them, only one cathode contact 102 can be provided on the driving wafer 10, or the number of cathode contacts can be determined according to needs.

[0103] Step M25: As Figure 11As shown in stage e, an insulating body 301 is filled outside the common cathode layer 304, so that all the sub-pixels 20 are located inside the insulating body 301, and an anode connecting member 306 is fabricated in the insulating body 301, thereby obtaining a pixel layer;

[0104] It can be understood that the insulating passivation layer 303 and the common cathode layer 304 outside the sub-pixel 20 are also located inside the insulating body 301.

[0105] Step M26: As Figure 11 shown in stage f, another compound semiconductor 70 is bonded to the top of the previous pixel layer through a bonding layer 302, and step M22 is performed, and the bonding metal member 3021 of the sub-pixel in this pixel layer is electrically connected to the corresponding anode contact through the anode connecting member 306 passing through the previous pixel layer. When the bonding metal member 3021 of the sub-pixel in this layer is connected to the anode connecting member 306 of the previous pixel layer, the first contact surface 30211 of the bonding metal member is embedded in the previous pixel layer and contacts the anode connecting member 306, or the anode connecting member �06 is embedded in the first contact surface 30211, and then steps M23 - M25 are performed to obtain the next pixel layer;

[0106] Step M27: Repeat step M26 until all pixel layers are fabricated;

[0107] Among them, the light-emitting colors of each sub-pixel 20 in the same pixel layer 30 are the same, and the light-emitting colors of the sub-pixels 20 in two adjacent pixel layers 30 are different.

[0108] It can be understood that the bonding metal member 3021 between the adjacent anode connecting members 306 in the Z direction can be directly used as the conductive metal member 3022.

[0109] Specifically, three pixel layers 30 can be set so that the light-emitting colors of the sub-pixels 20 in each pixel layer are all different to achieve a three-color configuration, or two pixel layers can be set, and the light-emitting colors of the sub-pixels 20 in these two pixel layers are different, thereby achieving a two-color configuration, or more layers can be set by continuing to stack on the basis of the three pixel layers.

[0110] For the convenience of description, the sub-pixel with a light-emitting color of red is called a red sub-pixel, the sub-pixel with a light-emitting color of green is called a green sub-pixel, and the sub-pixel with a light-emitting color of blue is called a blue sub-pixel;

[0111] Then, in actual configuration, if only the three-layer pixel layer 30 is set, red sub-pixels can be arranged in the first pixel layer (bottom pixel layer), green sub-pixels in the second pixel layer, and blue sub-pixels in the third pixel layer (top pixel layer). In actual working conditions, which pixel layer the sub-pixels of different colors are specifically located in can be selected according to needs and is not limited here.

[0112] It can be understood that since the light-emitting colors of the sub-pixels 20 in two adjacent pixel layers are different, the materials of the compound semiconductors 70 used in the preparation of two adjacent pixel layers are also different, so that the light-emitting colors of the compound semiconductors used are different; when preparing each pixel layer, the light-emitting color of the compound semiconductor selected is determined according to the actual situation. If it is necessary to prepare sub-pixels with a light-emitting color of red, a compound semiconductor with a light-emitting color of red is selected.

[0113] Among them, the compound semiconductor 70 uses inorganic compound materials. For example, the compound semiconductor corresponding to the blue light pixel layer uses InGaN material, the compound semiconductor corresponding to the green light pixel layer uses InGaN material, and the compound semiconductor corresponding to the red light pixel layer uses InGaN or AlGaInP material.

[0114] In actual applications, the film layers of the compound semiconductor will be more complex, or there will be cross-use of materials. A typical compound semiconductor structure mainly includes a P-type semiconductor layer 202, an N-type semiconductor layer 204, and an active layer 203 (MQW active quantum well) and other functional layers sandwiched between the two. For the film layer materials of the red compound semiconductor, refer to Table 1, and for the film layer materials of the green and blue compound semiconductors, refer to Table 2.

[0115] Table 1 Film Layer Materials of Compound Semiconductor (R)

[0116] Layer Name Material Material Material Material Material Material P - type Semiconductor Layer GaP GaAs GaAs GaN GaN GaN MQW Active Quantum Well AlGaInP AlGaInP AlGaAs InGaN InGaN InGaN N - type Semiconductor Layer GaAs AlGaAs GaAs GaN GaN GaN Substrate GaAs GaAs GaAs GaN Si Sapphire

[0117] Table 2 Film Layer Materials of Compound Semiconductor (G / B)

[0118] Layer Name Material Material Material P - type Semiconductor Layer GaN GaN GaN MQW Active Quantum Well InGaN InGaN InGaN N - type Semiconductor Layer GaN GaN GaN Substrate GaN Si Sapphire

[0119] In one of the embodiments, the insulating passivation layer 303 can be made of one or more of alumina, silica, and silicon nitride.

[0120] In one of the embodiments, the insulating body 301 can be made of one or more of silicon oxide, silicon nitride, silicon carbide (SiC), silicon carbonitride (SiCN), phosphate glass (PSG), and borophosphosilicate glass (BPSG).

[0121] In one embodiment, the common cathode layer 304 includes one or more of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), aluminum-doped indium tin oxide, silver-doped indium tin oxide, and gold-doped indium tin oxide;

[0122] In one embodiment, the material of the anode connector 306 can be one or more of aluminum, copper, and tungsten.

[0123] Furthermore, the material of the cathode connector 308 can be the same as that of the anode connector 306, as long as it is a conductive material.

[0124] In one embodiment, the material of the bonding metal part 3021 can be one of Al, Au, and Cu, or a laminated structure of Ni, Au, Cu, etc. and Sn, or a bonding laminate of Au and In, Ge, or a bonding laminate of Au and Si.

[0125] Furthermore, the above-mentioned bonding metal part 3021 can adopt the following structural form: Cr2nm / Pt50nm / Ti 10nm / Pt50nm / Au100nm / Sn150nm / Au50nm, where Cr is the adhesion layer and Pt / Ti / Pt is the barrier layer.

[0126] In some embodiments, after step M2, as Figure 11 shown in the h stage, a dielectric layer is further deposited on the upper part of the pixel layer 30 located at the top layer, and the dielectric layer is patterned and etched to form a lens 80, so that each sub-pixel 20 corresponds to the lens 80 one by one, or multiple sub-pixels 20 correspond to one lens 80.

[0127] Embodiment 2

[0128] As Figure 12 and Figure 13 shown, the main difference between this embodiment and Embodiment 1 is that the multi-layer microdisplay chip includes a color conversion part 60, the color conversion part 60 is located in a pixel layer 30, an excitation pixel 50 is arranged in the adjacent pixel layer below the pixel layer where the color conversion part 60 is located, and the color conversion part 60 is located on the light output path of the excitation pixel 50 to excite the color conversion part 60 to emit light of a corresponding color, and the excitation pixel 50 and the color conversion part 60 correspond to each other one by one.

[0129] The color conversion part 60 can adopt a quantum dot material or a phosphor material, so as to be excited by external light to undergo color conversion and emit light of a certain specific color. When the light emitted by the excitation pixel 50 is incident on the corresponding color conversion part 60, the color conversion part 60 will be excited to emit light of a certain color.

[0130] In some embodiments, filling holes 309 are provided in the pixel layer 30 where the color conversion member 60 is located, and each filling hole 309 is filled with the color conversion member 60.

[0131] Further, as Figure 12 shown, the inner wall of the filling hole 309 is inclined relative to the driving wafer 10, and the inclination angle C is 60° to 90°, which is more convenient for etching and can also ensure the filling effect.

[0132] In some embodiments, the length Ls of the filling hole 309 in the X direction is not less than the maximum length of the underlying excitation pixel 50 in the X direction, where the X direction and the Z direction are perpendicular. In this way, a good optical channel can be provided for the underlying excitation pixel 50 and optical crosstalk is not likely to occur, thereby ensuring the color conversion effect to the greatest extent.

[0133] In some embodiments, an isolation layer 310 is formed on the inner wall of the filling hole 309; the isolation layer 310 is used to shield the optical interference from the pixels below the non-filling space, so that the color conversion member 60 inside the filling hole 309 can have a better color conversion effect.

[0134] Among them, the isolation layer 310 can be a metal reflection layer or a light absorption layer.

[0135] The material of the metal reflection layer can be one or more of metals Al, Ti, Pt, Au, Cr, and Ni to shield optical interference through metal reflection; the material of the light absorption layer can be light-absorbing materials such as carbon film, black glue, and polysilicon to shield optical interference through light absorption.

[0136] Further, the thickness of the isolation layer 310 is 50 nm to 2 μm. If the thickness is too thin, it is easy to leak electricity, and if it is too thick, the cost will increase.

[0137] Specifically, it can be carried out according to the thickness required for optical interference shielding of different materials. For example, Al ≥ 50 nm and black glue ≥ 1 μm.

[0138] Specifically, only two pixel layers 30 can be provided. At least one excitation pixel 50 is provided in the first pixel layer, and a corresponding color conversion member 60 and sub-pixels with a light output color different from that of the color conversion member 60 are provided in the second pixel layer; the filling holes 309 can be opened in the insulating body 301 of the second pixel layer.

[0139] In some embodiments, the light output color of the color conversion member 60 is red, and the light output color of the excitation pixel 50 is blue.

[0140] Furthermore, sub-pixels are also provided in the first pixel layer. The light-emitting color of the sub-pixels in the first pixel layer is blue and is emitted through the second pixel layer. The light-emitting color of the sub-pixels in the second pixel layer is green and is emitted through the second pixel layer. As a result, the light finally emitted through the second pixel layer includes: green light, blue light, and red light emitted by the color conversion member 60.

[0141] It should be noted that the light-emitting wavelength of the excitation pixel 50 is shorter than the red light wavelength, so that light with a shorter wavelength is used to excite the color conversion member 60 to generate color conversion and emit red light. The color conversion member 60 is made of a quantum dot material or a red phosphor material.

[0142] In some embodiments, the red light color conversion member can be made of a quantum dot material, such as indium phosphide (InP); or a phosphor material, such as fluoride-based phosphor-KSF red phosphor (K2SiF6:Mn4+), or nitride Eu2+-doped CaAlSiN3-based red phosphor, etc.

[0143] The above-mentioned sub-pixels 20 and excitation pixels 50 are both electrically connected to the driving wafer 10. The driving wafer 10 has a driving circuit to control the light emission of the sub-pixels 20 and excitation pixels 50 by using the driving circuit.

[0144] The structure of the excitation pixel 50 is basically the same as that of the sub-pixel 20, and also includes a P-type semiconductor layer 202, an active layer 203, an N-type semiconductor layer 204, etc., which will not be elaborated here.

[0145] Similarly, the first contact surface 30211 of the bonding metal member 3021 in the sub-pixel 20 of the second pixel layer of this embodiment is also a non-flat surface and has an embedding protrusion 30212 as shown in Figure 12 . The anode connecting member 306 is lower than the interface 40 to form a corresponding recessed portion 3051, or the first contact surface 30211 has an embedding recess 30213 as shown in Figure 13 . The anode connecting member 306 is higher than the interface 40 to form a corresponding protruding portion 3061. This is the same as that in the first embodiment and will not be elaborated here.

[0146] In some embodiments, as shown in Figure 13 , at least one lens 80 is connected to the upper part of the pixel layer 30 located at the top layer. Each sub-pixel 20 corresponds to one lens 80, or multiple sub-pixels 20 correspond to one lens 80.

[0147] Furthermore, each color conversion member 60 also corresponds to one lens 80.

[0148] The preparation method of the multi-layer microdisplay chip in this embodiment is basically the same as that in Embodiment 1, except that filling holes 309 need to be provided in the corresponding pixel layers, and color conversion materials are filled in the filling holes 309 to form color conversion components 60, which will not be elaborated here.

[0149] Embodiment 3

[0150] The main difference between this embodiment and Embodiment 1 is that the light-emitting colors of the sub-pixels 20 in each pixel layer 30 are the same to prepare a multi-layer monochromatic product.

[0151] The preparation method of the multi-layer microdisplay chip in this embodiment is basically the same as that in Embodiment 1, except that the light-emitting colors of the sub-pixels in each pixel layer are the same, which will not be elaborated here.

[0152] For the multi-layer microdisplay chips and their preparation methods in the above embodiments, through the way of mutual embedding, the bonding metal parts and the anode connecting parts are in full contact, thus effectively ensuring the reliability of the anode current transmission; it also effectively ensures the connection strength between the bonding metal parts and the anode connecting parts, and is also more conducive to the alignment and positioning of the two.

[0153] All the above optional technical solutions can be combined arbitrarily to form optional embodiments of the present utility model, that is, any number of embodiments can be combined to meet the requirements of different application scenarios, and all are within the protection scope of this application, which will not be elaborated one by one here.

[0154] It should be noted that the above embodiments are merely examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims

1. A multi-layer microdisplay chip, characterized in that: Comprising, a driving wafer, on which an anode contact is provided; at least two pixel layers, all the pixel layers are sequentially stacked along the Z direction on the driving wafer, at least one sub-pixel is provided in each pixel layer, and a bonding metal part is provided on one side of each sub-pixel close to the driving wafer. The bonding metal part of the sub-pixel in the upper pixel layer is electrically connected to the corresponding anode contact by an anode connecting part passing through the lower pixel layer. The bonding metal part of the sub-pixel in the upper pixel layer has a first contact surface for contacting the anode connecting part. The first contact surface is a non-flat surface. The first contact surface is embedded in the pixel layer where the anode connecting part is located and contacts the anode connecting part, or the anode connecting part is embedded in the first contact surface.

2. The multi-layer microdisplay chip according to claim 1, wherein: An anode hole corresponding to the anode connecting part is formed on the interface between two adjacent pixel layers. The anode hole is filled with an anode connecting part. The top surface of the anode connecting part filled in the anode hole is lower than the interface to form a recessed part. An embedding protrusion is formed on the first contact surface. The embedding protrusion of the sub-pixel in the pixel layer is embedded in the recessed part of the corresponding anode hole in the adjacent pixel layer below to be electrically connected to the anode connecting part; or, The top surface of the anode connecting part filled in the anode hole is higher than the interface to form a protruding part. An embedding recess is formed on the first contact surface. The embedding recess of the sub-pixel in the pixel layer is fitted with the protruding part of the corresponding anode connecting part in the adjacent pixel layer below.

3. The multi-layer microdisplay chip according to claim 2, wherein: The height of the recessed part is 10nm - 300nm, and the height of the protruding part is 10nm - 300nm.

4. The multi-layer microdisplay chip according to claim 2, wherein: Comprising at least three pixel layers. The bonding metal parts of the sub-pixels in the pixel layers of the third layer and above are electrically connected to the corresponding anode contacts by a plurality of anode connecting parts sequentially connected along the Z direction below. Each of the anode connecting parts sequentially connected along the Z direction is located in a different pixel layer. Adjacent two of the anode connecting parts sequentially connected along the Z direction are in direct contact; or, a conductive metal part is provided between adjacent two of the anode connecting parts.

5. The multi-layer microdisplay chip according to claim 2, wherein: The inclination angle of the inner wall of the anode hole with respect to the top surface of the driving wafer is 90° - 120°.

6. The multi-layer microdisplay chip according to claim 1, characterized in that: A cathode contact is further provided on the driving wafer. Each pixel layer includes an insulating body. The sub-pixels in the pixel layer are all coated inside the insulating body. An insulating passivation layer is coated outside each sub-pixel. The bonding metal part of the sub-pixel is located inside the insulating passivation layer. The upper part of the insulating passivation layer has an opening. A common cathode layer is coated outside the insulating passivation layer. The sub-pixel is electrically connected to the common cathode layer through the opening. The common cathode layer is used for being electrically connected to the cathode contact.

7. The multi-layer microdisplay chip according to claim 6, wherein: Each sub-pixel includes a P-type semiconductor layer, an active layer, and an N-type semiconductor layer sequentially arranged along the Z direction. The bonding metal part is provided on one side of the P-type semiconductor layer close to the driving wafer. The N-type semiconductor layer is electrically connected to the common cathode layer through the opening.

8. The multi-layer microdisplay chip according to claim 6, wherein: Cathode holes are formed on the interface between two adjacent pixel layers. The cathode holes are filled with cathode connectors, and the cathode connectors are all electrically connected to cathode contacts. The common cathode layers in the upper pixel layer are all electrically connected through the cathode connectors and cathode contacts in the lower pixel layer.

9. The multi-layer microdisplay chip according to claim 6, wherein: The distance between the top surface of the insulating body of each pixel layer and the common cathode layer at the top of the sub-pixels in this layer is not less than 100 nm.

10. The multi-layer microdisplay chip according to claim 1, characterized in that: The sub-pixels are trapezoidal or cylindrical.

11. The multi-layer microdisplay chip according to claim 1, wherein: The light-emitting colors of each sub-pixel in the same pixel layer are the same, and the light-emitting colors of the sub-pixels in two adjacent pixel layers are different.

12. The multi-layer microdisplay chip according to claim 1, wherein: The light-emitting colors of the sub-pixels in each pixel layer are all the same.

13. The multi-layer microdisplay chip according to claim 1, wherein: It includes a color conversion component. The color conversion component is located in a pixel layer. Excitation pixels are arranged in the adjacent pixel layer below the pixel layer where the color conversion component is located. The color conversion component is located on the light-emitting path of the excitation pixels.

14. The multi-layer microdisplay chip according to claim 1, wherein: At least one lens is connected to the upper part of the pixel layer at the top layer. Each sub-pixel corresponds to one lens, or multiple sub-pixels correspond to one lens.

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