Radar target interference simulator

Abstract

The utility model discloses a radar target interference simulator, the simulator comprises a control terminal and an interference host, the interference host comprises a digital subsystem, a radio frequency subsystem and an antenna assembly, the digital subsystem is in signal connection with the control terminal and is configured to collect radar signals, and the radio frequency subsystem is configured to transmit the radar signals to the control terminal. The digital subsystem is used for receiving a radar signal and generating a targeted radio frequency interference signal including a suppressing interference signal and a false target deceptive interference signal based on the radar signal, and the radio frequency subsystem is connected with the digital subsystem and is configured to perform adjustment processing on the radio frequency interference signal. The antenna assembly is connected with the radio frequency subsystem and the digital subsystem, and is configured to adjust the targeted radio frequency interference signal after adjustment processing to radiate outwards and receive a radar signal.

Description

Technical Field

[0001] The utility model relates to the technical field of radar interference simulation, in particular to a radar target interference simulator. Background Art

[0002] A radar system is an electronic system that uses electromagnetic waves to detect and determine the position, speed, and other characteristics of a specific target. It is usually composed of a transmitter, receiver, antenna, antenna switch, timer, indicator, power supply, and other parts. It has the characteristics of long detection distance, fast target position determination, and all-weather operation. Therefore, it is widely used in early warning, guidance, fire control, guidance, reconnaissance, traffic control, etc.

[0003] In order to meet the actual use needs of radar, a simulator is needed that can implement interference signals such as dense false targets, random false targets, smart noise, narrowband noise, and broadband noise on the radar. Utility Model Content

[0004] In view of the above-mentioned prior art, the present invention provides a radar target interference simulator, which mainly solves the technical problems existing in the above-mentioned background technology.

[0005] To achieve the above-mentioned purpose, the technical solution of an embodiment of the present utility model is implemented as follows: a radar target interference simulator, the simulator includes a control terminal and an interference host, the interference host includes a digital subsystem, a radio frequency subsystem and an antenna assembly, the digital subsystem is connected to the control terminal signal, and is configured to collect radar signals and generate targeted radio frequency interference signals including suppressive interference signals and false target deceptive interference signals based on the radar signals, the radio frequency subsystem is connected to the digital subsystem, and is configured to adjust and process the radio frequency interference signals, the antenna assembly is respectively connected to the radio frequency subsystem and the digital subsystem, and is configured to adjust and radiate the adjusted targeted radio frequency interference signals outward, and receive radar signals.

[0006] Optionally, the digital subsystem includes an FPGA chip, an ADC / DAC circuit, a digital RF storage circuit, a suppression interference circuit, and a false target deception interference circuit, wherein the input end of the ADC / DAC circuit is connected to the antenna assembly, and the output end thereof is connected to the FPGA chip signal, and the FPGA chip signal is connected to the digital RF storage circuit signal. The suppression interference circuit and the false target deception interference circuit generate targeted RF interference signals including suppression interference signals and false target deception interference signals based on the radar echo signal stored in the digital RF storage circuit.

[0007] Optionally, the interference suppression circuit includes a narrowband aiming frequency interference signal generating circuit and a broadband blocking interference signal generating circuit.

[0008] Optionally, the RF subsystem includes a local oscillator circuit, a receiving circuit, a first transmitting circuit, and a second transmitting circuit. The local oscillator circuit provides a reference clock for the receiving circuit, the first transmitting circuit, and the second transmitting circuit. The receiving circuit down-converts and up-converts the RF interference signal. The first transmitting circuit is used to output the RF interference signal after down-conversion, and the second transmitting circuit is used to output the RF interference signal after up-conversion.

[0009] Optionally, the receiving circuit includes one down-conversion receiving circuit and two up-conversion receiving circuits.

[0010] Optionally, the antenna assembly includes a receiving antenna and a transmitting antenna.

[0011] The beneficial effects of the present invention are: receiving radar echo signals through the antenna assembly, collecting radar echo signals through the digital subsystem and correspondingly generating targeted radio frequency interference signals including suppressive interference signals and false target deceptive interference signals, and the radio frequency interference signals are limited, filtered, amplified and sensitivity-controlled by the radio frequency subsystem. In this process, control terminals including handheld terminals are used to display the processing results and generation results, and finally the radio frequency interference signals are radiated outward through the antenna assembly to exert suppressive interference and deceptive interference on the radar, thereby providing a signal environment for anti-interference performance detection for radar research, production, maintenance and use. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a schematic diagram of the overall module composition of the radar target interference simulator in an embodiment of the present application;

[0013] Figure 2 This is a schematic diagram of the overall module composition of the digital subsystem in the embodiment of the present application;

[0014] Figure 3 This is a schematic diagram of the overall module composition of the DRFM in an embodiment of the present application;

[0015] Figure 4 This is a schematic diagram of a circuit for generating a false target deception interference signal in an embodiment of the present application;

[0016] Figure 5 This is a connection diagram of the up-conversion component in the embodiment of the present application;

[0017] Figure 6 Schematic diagram of the connection of the down-conversion component in the embodiment of the present application.

[0018] Description of Figure Numbers:

[0019] 1 Control terminal, 2 Jamming host, 3 Digital sub-system, 301 FPGA chip, 302 ADC / DAC circuit, 303 Digital radio frequency storage circuit, 304 Suppression jamming circuit, 305 False target deception jamming circuit, 4 Radio frequency sub-system, 5 Antenna assembly. Detailed implementation manners

[0020] The technical solution of the present utility model will be further elaborated in detail below in conjunction with the accompanying drawings of the specification and specific embodiments. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present utility model belongs. The terms used in the specification of the present utility model herein are only for the purpose of describing specific embodiments and are not intended to limit the present utility model. In the following description, the expression "some embodiments" is involved, which describes a subset of all possible embodiments. However, it should be understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict.

[0021] In the following description, a large number of specific details are given to provide a more thorough understanding of the present utility model. However, it is obvious to those skilled in the art that the present utility model can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present utility model, some technical features known to the public are not described.

[0022] It should be understood that the present utility model can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and will fully convey the scope of the present utility model to those skilled in the art. And the purpose of the terms used herein is only to describe specific embodiments and not to limit the present utility model. When used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the related listed items.

[0023] It should be further noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or there can also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "inner", "outer", "left", "right" and similar expressions used herein are for illustrative purposes only and do not represent the only implementation.

[0024] To thoroughly understand the present utility model, detailed structures will be presented in the following description to illustrate the technical solutions proposed by the present utility model. The optional embodiments of the present utility model are described in detail as follows. However, in addition to these detailed descriptions, the present utility model can also have other implementations.

[0025] Please refer to the attached Figure 1 A radar target interference simulator provided by the present application, the simulator includes a control terminal 1 and an interference host 2. The interference host 2 includes a digital sub-system 3, a radio frequency sub-system 4 and an antenna assembly 5. The digital sub-system 3 is signal-connected to the control terminal 1 and is configured to collect radar signals and generate targeted radio frequency interference signals including suppression interference signals and false target deception interference signals based on the radar signals. The radio frequency sub-system 4 is connected to the digital sub-system 3 and is configured to adjust and process the radio frequency interference signals. The antenna assembly 5 is respectively connected to the radio frequency sub-system 4 and the digital sub-system 3 and is configured to adjust and radiate the processed targeted radio frequency interference signals outward and receive radar signals.

[0026] When the present application is implemented, the radar echo signal is received through the antenna assembly 5, the radar echo signal is collected through the digital sub-system 3 and corresponding targeted radio frequency interference signals including suppression interference signals and false target deception interference signals are generated. The radio frequency interference signals are subjected to amplitude limiting, filtering, amplification and sensitivity control through the radio frequency sub-system 4. During this process, the control terminal 1 including a handheld terminal is used to display the processing results and the generated results. Finally, the radio frequency interference signals are radiated outward through the antenna assembly 5, such as the radar releasing suppression interference and deception interference, providing a signal environment for anti-interference performance detection in the research, production, maintenance and use of the radar.

[0027] See Figure 2, in an embodiment provided by the present application, the digital sub-system 3 includes an FPGA chip 301, an ADC / DAC circuit 302, an ADC / digital radio frequency storage circuit 303, a jamming suppression circuit 304, and a false target deception jamming circuit 305. The input end of the ADC / DAC circuit 302 is connected to the antenna assembly 5, and its output end is connected to the FPGA chip 301 in a signal connection. The FPGA chip 301 is signal-connected to the ADC / digital radio frequency storage circuit 303. The jamming suppression circuit 304 and the false target deception jamming circuit 305 generate targeted radio frequency jamming signals including jamming suppression signals and false target deception jamming signals based on the radar echo signals stored in the ADC / digital radio frequency storage circuit 303.

[0028] Specifically, the FPGA chip 301 based on Xilinx company uses the XC7K325T-2FFG900 chip, which is pin-to-pin compatible with the FPGA XC7K410T-2FFG900, supports a 64-bit DDR3 capacity of 2 GByte, a gigabit Ethernet card, an FMC connector for HPC, provides 4 optical fiber interfaces, and the board supports various interface inputs.

[0029] Furthermore, the ADC / DAC circuit 302 adopts a standard FMC board type (single-width), with 1 intermediate frequency signal acquisition channel on the board, which can realize the sampling of the forward intermediate frequency signal. At the same time, there is 1 intermediate frequency output channel on the board, and the analog reverse intermediate frequency signal is output through the DAC.

[0030] Among them, the ADC circuit uses the A / D conversion chip AD9625 with mature applications in the company. The sampling accuracy is 12 bits, the maximum sampling rate supports 2.5 Gsps, and it has excellent SFDR performance in high-sampling-rate applications, providing direct RF sampling and an on-chip reference voltage source. The acquisition part of the circuit design uses mature technology to isolate the digital end and the analog end, effectively suppressing the digital end noise. The power supply uses an LDO with a high power supply rejection ratio for power supply to ensure performance such as SNR and SFDR. The ADC front end uses a large-bandwidth and low-loss transformer for AC coupling, which can provide a high common-mode rejection ratio, effectively suppress the common-mode noise of the analog signal, and at the same time ensure a stable in-band flatness. The ADC output data and the synchronous clock are connected to the FPGA of the signal processing motherboard through the FMC connector, and the output uses a flexible digital data output format based on the JESD204B specification. Compared with the traditional LVDS parallel data transmission, it reduces the wiring area and simplifies the connection with the FPGA. The digital end design fully considers the signal integrity design to ensure the stable transmission of synchronous data to the FPGA.

[0031] The DAC circuit uses the D / A conversion chip AD9129 with mature applications in the company. The sampling accuracy is 14 bits, and the highest sampling rate supports 2.8 GSPS. The power supply design is as described above. The input data and clock of the DAC are connected to the FPGA on the signal processing motherboard through the FMC connector, using signals in the high-speed parallel LVDS specification, so as to cooperate with the above-mentioned A / D and avoid consuming too many limited GTX interfaces of the FPGA, further expanding the application range of the DAC.

[0032] Furthermore, the ADC / digital radio frequency memory circuit 303 samples and stores two intermediate frequency signals from the microwave front end, and reads out the signals when needed, and outputs multi-dimensional coherent deception intermediate frequency interference signals of amplitude, frequency modulation to form range, angle, and speed, or continuously reads out and modulates to form an interference waveform.

[0033] The input intermediate frequency of the digital radio frequency memory is divided into two paths after intermediate frequency amplification. One path of the signal is sent to the DRFM control unit as a width-preserving pulse after detection, comparison, and shaping, and the other path of the signal is directly sent to the DRFM module for storage. The comprehensive control circuit receives the control parameter packet input by the power management circuit, decomposes the control parameters, and sends the working mode of the DRFM to the DRFM control unit. The DRFM control unit generates corresponding read and write signals according to the working mode of the DRFM, controls the DRFM to complete the storage of the intermediate frequency signal, and replicates and outputs the intermediate frequency signal at the required time.

[0034] Exemplarily, DRFM is a high-speed digital storage device that can store, copy, interference modulate, and forward intercepted and processed digital signals almost without distortion, generating one or more false targets with the same characteristics as the real target echo. Its structural block diagram is as Figure 3 shown

[0035] DRFM generally includes six parts, namely: down-conversion module, analog-to-digital conversion module, memory, control unit, digital-to-analog conversion module, and up-conversion module.

[0036] Its working process is mainly as follows: The jammer tunes the local oscillator frequency according to the reconnaissance information, processes the input radio frequency signal through mixing, filtering, etc. of the down-conversion module, and converts it into a baseband analog signal. Then, the ADC quantizes and samples the baseband analog signal to convert it into a baseband digital signal. Next, the interference control unit controls the storage to store, copy, and forward the baseband digital signal. The forwarded digital signal is converted back into a baseband analog signal through the transformation of the DAC. Finally, the up-conversion module performs up-conversion and power amplification on it, and converts the interference signal into a radio frequency output signal.

[0037] In an embodiment provided by the present application, the jamming suppression circuit 304 jams the radar in real time by generating various interference signals such as frequency-targeted interference, broadband interference, frequency-scanning interference, and high-repetition-frequency interference. Specifically, it includes a narrowband frequency-targeted interference signal generation circuit and a broadband blocking interference signal generation circuit.

[0038] For the narrowband frequency-targeted interference signal generation circuit, a phase-locked loop is used to ensure the frequency setting accuracy. The user generates a noise signal with specific frequency-domain and time-domain characteristics through the digital noise formation model built in the ETX, downloads the model data to the buffer memory of the modulation signal generation module through the serial port, reads out the data under the control of the high-speed control logic, and sends it to the D / A converter for conversion to form the required preset voltage, which is then added to the PLL phase discrimination voltage to control the VCO.

[0039] For the broadband blocking interference signal generation circuit, the ETX sends the parameters to the interference control module, and the programmable logic array (EPLD) translates the parameters into various hardware control logics, which can guide the modulation signal generation module to control the VCO to directly output signals with a bandwidth of several hundred megahertz or even several gigahertz, and then divides them into two frequency bands for amplification to avoid harmonic generation.

[0040] See Figure 4 In an embodiment provided by the present application, the false target deception jamming circuit 305 is used to generate dense false targets and random false target jamming. It consists of multiple independent channels. In each channel, digital frequency storage technology is used to record and save the radar signal waveform, and under the control of a computer, the time delay and Doppler modulation of signal types such as radar target echo, deceptive jamming signal, and chaff are completed, as well as the modulation of radar target characteristics. After upconversion, the radio frequency signal is output to meet the test of the anti-jamming capabilities of modern radars such as pulse compression, pulse Doppler, and coherent or non-coherent frequency agile radars. When used for target simulation, each unit can independently simulate the echo signals of coherent / incoherent pulse radar targets, pulse Doppler radar targets, continuous wave, and high-repetition-frequency radar targets. When testing the radar, one of the channels can simulate the rear reference signal

[0041] In an embodiment provided by the present application, the radio frequency sub-system 4 includes a local oscillator circuit, a receiving circuit, a first transmitting circuit, and a second transmitting circuit. The local oscillator circuit provides a reference clock for the receiving circuit, the first transmitting circuit, and the second transmitting circuit. The receiving circuit performs downconversion and upconversion processing on the radio frequency interference signal. The first transmitting circuit is used to output the downconverted radio frequency interference signal, and the second transmitting circuit is used to output the upconverted radio frequency interference signal. The receiving circuit includes one downconversion receiving circuit and two upconversion receiving circuits.

[0042] See Figure 5, specifically, for the up-conversion receiving circuit, since the intermediate frequency input frequency is 0.1 GHz - 1.3 GHz, and the required output frequency is 2 GHz - 4 GHz, and the obtained signal needs to be switched in four specified frequency bands at 2 GHz - 4 GHz, a single-pole four-throw switch is required to control the selection of the signal channel, and a two-stage frequency conversion method is determined. Considering from the aspect of gain, because a two-stage frequency conversion scheme is adopted, there will be two frequency conversion losses. Coupled with the connectors in the components and the losses of passive devices mainly the filters, in order to obtain an output of 0 dBm from an input of 0 dBm, several stages of amplifiers are necessarily used. Since the signal has more spurs at a higher frequency at the RF end and it is more difficult to amplify the signal than at the intermediate frequency end, an amplifier is added at each of the front and back of the first frequency conversion, and another amplifier is added after filtering out the spurs in the second frequency conversion. Whether an equalizer needs to be added is determined according to the actual test results. Considering the suppression of harmonics and spurs, since the mixer requires a large local oscillator to drive, resulting in an increase in local oscillator leakage, the performance of the mixer is crucial, and the isolation from the local oscillator port to the RF port and from the local oscillator port to the intermediate frequency port should also be high enough. The spurs after mixing are not needed by us, so a band-pass filter needs to be added after frequency conversion to filter out the excess spurs, and there is also an amplifier after filtering, so the performance requirements for the filter are relatively high.

[0043] See Figure 6 , the up-conversion component is implemented by adopting a two-stage frequency conversion method. Correspondingly, the down-conversion component also adopts a two-stage frequency conversion method. The down-conversion component is composed of two-stage amplification and equalization components, switch and filter components, ultra-wideband mixing components, filter and amplification components, broadband mixing components, and filter and amplification components. Since the down-conversion component requires a higher gain compared to the up-conversion component, the 2 GHz - 4 GHz amplification and equalization components are placed in two stages respectively before and after the switch, and two amplifiers are also considered to be added in the filter and amplification components to meet the module output index requirements of 0 dB output at the intermediate frequency.

[0044] Specifically, the antenna assembly 5 includes a receiving antenna and a transmitting antenna. The receiving antenna is used to receive radar echo signals. There are two transmitting antennas, which are respectively connected to the first transmitting circuit and the second transmitting circuit to realize the radiation of interference signals.

[0045] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. The protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. Radar target interference simulator, characterized in that, The simulator includes a control terminal and a jamming host. The jamming host includes a digital sub-system, a radio frequency (RF) sub-system, and an antenna assembly. The digital sub-system is signal-connected to the control terminal and is configured to collect radar signals and generate targeted RF jamming signals including suppressive jamming signals and false target deceptive jamming signals based on the radar signals. The RF sub-system is connected to the digital sub-system and is configured to adjust and process the RF jamming signals. The antenna assembly is respectively connected to the RF sub-system and the digital sub-system and is configured to radiate the adjusted targeted RF jamming signals outward and receive radar signals. The digital sub-system includes a Field Programmable Gate Array (FPGA) chip, an Analog-to-Digital Converter / Digital-to-Analog Converter (ADC / DAC) circuit, a digital RF storage circuit, a suppressive jamming circuit, and a false target deceptive jamming circuit. The input end of the ADC / DAC circuit is connected to the antenna assembly, and its output end is signal-connected to the FPGA chip. The FPGA chip is signal-connected to the digital RF storage circuit. The suppressive jamming circuit and the false target deceptive jamming circuit generate targeted RF jamming signals including suppressive jamming signals and false target deceptive jamming signals based on the radar echo signals stored in the digital RF storage circuit.

2. The radar target interference simulator according to claim 1, wherein The suppressive jamming circuit includes a narrowband frequency-tracking jamming signal generation circuit and a broadband blocking jamming signal generation circuit.

3. The radar target interference simulator according to claim 2, characterized in that, The RF sub-system includes a local oscillator circuit, a receiving circuit, a first transmitting circuit, and a second transmitting circuit. The local oscillator circuit provides a reference clock for the receiving circuit, the first transmitting circuit, and the second transmitting circuit. The receiving circuit performs down-conversion and up-conversion processing on the RF jamming signals. The first transmitting circuit is used to output the down-converted RF jamming signals, and the second transmitting circuit is used to output the up-converted RF jamming signals.

4. The radar target interference simulator according to claim 3, wherein The receiving circuit includes a single-channel down-conversion receiving circuit and two-channel up-conversion receiving circuits.

5. The radar target interference simulator according to claim 1, characterized in that, The antenna assembly includes a receiving antenna and a transmitting antenna.

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