Chip packaging structure and electronic equipment

Abstract

The embodiment of the utility model provides a chip packaging structure and electronic equipment, the chip packaging structure comprises a circuit board and an LPDDR chip, the circuit board comprises a packaging area, the width of the packaging area is 0-8.2 mm, and the length of the packaging area is 0-12.4 mm; the circuit board is provided with a packaging area, an LPDDR chip is packaged in the packaging area, the LPDDR chip is provided with a plurality of pins, the plurality of pins are electrically connected with the circuit board through a plurality of electric connection balls respectively, one pin is connected with one electric connection ball, and one electric connection ball corresponds to one signal point location; the packaging area comprises a first area and a second area, and a plurality of grounding point positions and suspension point positions are arranged in the second area. The size of the chip packaging structure is reduced, and the chip packaging structure can adapt to small electronic equipment such as smart phones and wearable equipment.

Description

Technical Field

[0001] This application relates to the technical field of chip packaging, and specifically relates to a chip packaging structure and an electronic device. Background Art

[0002] LPDDR (Low Power Double Data Rate SDRAM) chips are a communication standard developed by the US JEDEC (Joint Electron Device Engineering Council) association for low-power memory. They are known for low power consumption and small size and are specifically used for mobile electronic devices.

[0003] In the process of conceiving and implementing this application, the inventors found at least the following problems: In some solutions, generally 315 balls are used to separately package LPDDR chips, and the package size of this packaging method is 15 mm × 12.4 mm, occupying a relatively large area. Therefore, this package size is mostly used in large electronic devices such as laptop computers. However, this package size has a technical problem of poor adaptability for small electronic devices such as smart phones and wearable devices.

[0004] The foregoing description is for the purpose of providing general background information and does not necessarily constitute prior art. Summary of the Utility Model

[0005] In view of the above technical problems, this application provides a chip packaging structure and an electronic device, which reduce the size of the packaging structure to be suitable for small electronic devices such as smart phones and wearable devices.

[0006] This application provides a chip packaging structure, including a circuit board and an LPDDR chip. The circuit board includes a packaging area, the width of the packaging area is 0 - 8.2 mm, and the length of the packaging area is 0 - 12.4 mm; the LPDDR chip is packaged in the packaging area. The LPDDR chip has a plurality of pins, and the plurality of pins are respectively electrically connected to the circuit board through a plurality of electrical balls. Among them, one pin is connected to one electrical ball, and one electrical ball corresponds to one signal point position; the packaging area includes a first area and a second area, and a plurality of ground point positions and floating point positions are arranged in the second area.

[0007] In some optional embodiments, the width of the packaging area is 8.2 mm, and the length of the packaging area is 6.2 mm.

[0008] In some optional embodiments, the first area and the second area are both flush with the same edge of the circuit board, and the first area is arranged around a portion of the outside of the second area; data input / output points, power input / output points, write clock points, read clock points and differential synchronization signal points are arranged in the first area.

[0009] In some optional embodiments, the first region includes a first sub-region, a second sub-region and a third sub-region, the first sub-region and the second sub-region are arranged sequentially along the first direction, the third sub-region is adjacently arranged on the same side of the first sub-region and the second sub-region along the second direction, and along the first direction, the overall region composed of the first sub-region and the second sub-region occupies at least part of the area of the third sub-region.

[0010] In some optional embodiments, along the second direction, the second region is arranged between the first sub-region and the third sub-region.

[0011] In some optional embodiments, the first direction and the second direction are perpendicular to each other.

[0012] In some optional embodiments, in the first direction, one side edge of the first sub-region, the second region, and the third sub-region are all flush with the same side edge of the circuit board; the edge of the first sub-region facing the second sub-region is flush with the edge of the second region close to the second sub-region; the other side edge of the third sub-region is flush with the edge of the second sub-region facing away from the first sub-region.

[0013] In some optional embodiments, the first sub-area is arranged with five rows and eight columns of the signal points, the second sub-area is arranged with seven rows and five columns of the signal points; and the third sub-area is arranged with four rows and thirteen columns of the signal points.

[0014] In some optional embodiments, the first sub-area and the third sub-area are both provided with a plurality of data input and output points and a plurality of power input and output points, at least one of the first sub-area and the third sub-area is provided with a write clock point and a read clock point, and at least one of the first sub-area and the third sub-area is provided with a differential synchronization signal point.

[0015] In some optional implementations, positions of any two data input and output points in the first sub-area can be interchanged.

[0016] In some optional implementations, the positions of any two data input and output points in the third sub-area can be interchanged.

[0017] In some alternative embodiments, at least one of the first sub-region and the third sub-region has at least one floating point.

[0018] In some alternative embodiments, at least one of the power input / output points in at least one of the first sub-region and the third sub-region is formed as the floating point.

[0019] In some alternative embodiments, the at least one floating point is configured to be grounded.

[0020] An embodiment of the present application further provides an electronic device, including the chip packaging structure provided in the above embodiment.

[0021] In the chip packaging structure provided by the embodiment of the present application, by setting a packaging area on the circuit board, a single packaging form is formed. Among them, the width of the packaging area is 0 - 8.2 mm, and the length of the packaging area is 0 - 12.4 mm. The LPDDR chip is packaged in the packaging area. The LPDDR chip has multiple pins, and the multiple pins are respectively connected to the circuit board through solder balls. One pin is connected to one solder ball, and one solder ball corresponds to one signal point. In this way, by designing the chip packaging structure as a single-channel single-packaging structure with a small size, the area of the circuit board occupied by the LPDDR chip packaging is saved, so that the packaging structure can be adapted to a single-channel SOC and small electronic devices with a small packaging size, such as smart phones and wearable devices. By arranging multiple grounding points in the second region, the signal stability can be improved, and by arranging multiple floating points in the second region, the mechanical strength of the circuit board can be improved, and the overall flatness of the post-packaging structure can be improved.

[0022] In addition to the technical problems solved by the embodiments of the present application described above, the technical features constituting the technical solutions, and the beneficial effects brought by the technical features of these technical solutions, other technical problems that can be solved by the chip packaging structure and the electronic device provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought by these technical features will be further described in detail in the specific implementation manners. Description of the Drawings

[0023] The drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 Schematic diagram of the chip packaging structure provided by the embodiment of the present application;

[0025] Figure 2 Top view of the chip packaging structure provided by the embodiment of the present application;

[0026] Figure 3 Arrangement schematic diagram of the electrical connection balls of the chip packaging structure provided by the embodiment of the present application;

[0027] Figure 4 Arrangement schematic diagram of the signal point positions of the chip packaging structure provided by the embodiment of the present application;

[0028] Figure 5 Hardware structure schematic diagram of a mobile terminal for implementing various embodiments of the present application.

[0029] The realization of the purpose of the present application, functional characteristics and advantages will be further described in conjunction with the embodiments with reference to the accompanying drawings. Through the above-mentioned accompanying drawings, the specific embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and text descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed implementation manners

[0030] Here, the exemplary embodiments will be described in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are only examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0031] It should be noted that in this article, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including that element. Optionally, components, features, elements with the same name in different embodiments of the present application may have the same meaning or may have different meanings, and their specific meanings need to be determined by their explanations in the specific embodiments or further in combination with the context in the specific embodiments.

[0032] It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of the present disclosure, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining". Furthermore, as used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context indicates otherwise. It should be further understood that the terms "comprising", "including" indicate the presence of the stated features, steps, operations, elements, components, items, kinds, and / or groups, but do not preclude the presence, occurrence or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or", "and / or", "including at least one of the following" and the like used in this application may be interpreted inclusively, or mean any one or any combination. For example, "including at least one of the following: A, B, C" means "any one of the following: A; B; C; A and B; A and C; B and C; A and B and C", and again, "A, B or C" or "A, B and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A and B and C". An exception to this definition only occurs when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way.

[0033] It should be understood that although the steps in the flowchart in the embodiments of the present application are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this application, the execution of these steps has no strict order limit, and they can be executed in other orders. Moreover, at least a part of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same moment, but can be executed at different moments, and their execution order is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0034] Depending on the context, the words "if", "when" as used herein may be interpreted as "when"

[0035] or "while" or "in response to determining" or "in response to detecting". Similarly, depending on the context, the phrase "if determined" or "if detecting (stated condition or event)" may be interpreted as "when determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)".

[0036] It should be understood that the specific embodiments described herein are merely for explaining the present application and are not used to limit the present application.

[0037] In the following description, suffixes such as "module", "component", or "unit" used to represent elements are only for the convenience of explaining the present application and have no specific meaning in themselves. Therefore, "module", "component", or "unit" can be used interchangeably.

[0038] The LPDDR (Low Power Double Data Rate SDRAM) chip is a type of volatile memory product, characterized by low power consumption and small size, and is mainly used in mobile electronic devices.

[0039] Currently, mainstream suppliers generally use 315 balls to individually package the LPDDR chip. The package size of this packaging method is 15mm × 12.4mm, occupying a relatively large area. Therefore, this package size is mostly used in large electronic devices such as laptop computers. To reduce the package area of the LPDDR chip, in related technologies, a new packaging form is proposed, which adopts a dual-packaging structure with 245 balls, and the package area is 8.2 * 12.4mm. The circuit board includes two symmetric packaging areas, which is suitable for dual-channel LPDDR chips, and one LPDDR chip is packaged in one packaging area.

[0040] Optionally, 315 balls can be understood as having 315 solder balls or copper balls for electrical connection between the LPDDR chip and the circuit board; while 245 balls means having 245 solder balls or copper balls for electrical connection between the LPDDR chip and the circuit board.

[0041] Taking a smartphone as an example, the design of the circuit board of the smartphone is becoming increasingly complex, so the area available for the LPDDR chip to occupy is continuously compressed. Therefore, both the 315-ball LPDDR chip packaging structure and the 245-ball dual-LPDDR chip packaging structure have the problem of large package size; in addition, not all electronic devices are dual-channel LPDDR chips. The system-on-chip (SOC) of small electronic devices such as mobile phones and watches may be single-channel. For small electronic devices with a single-channel SOC, the existing packaging structure has the technical problem of poor adaptability due to large package size.

[0042] In view of the above problems, an embodiment of the present application proposes a chip packaging structure. By setting a packaging area on the circuit board, a single-packaging form is formed. Among them, the width of the packaging area is 0-8.2 mm, and the length of the packaging area is 0-12.4 mm. The LPDDR chip is packaged in the packaging area. The LPDDR chip has multiple pins, and the multiple pins are respectively connected to the circuit board through solder balls. One pin is connected to one solder ball, and one solder ball corresponds to one signal point. In this way, by designing the chip packaging structure as a single-channel single-packaging structure with a small size, the area of the circuit board occupied by the LPDDR chip packaging is saved, so that the packaging structure can be adapted to a single-channel SOC and small-sized electronic devices such as smart phones and wearable devices.

[0043] The chip packaging structure provided by the embodiment of the present application can be applied to large electronic devices and can also be applied to small electronic devices. Among them, the electronic device can be, for example, a terminal device, and the terminal device can also be referred to as a terminal, a user equipment (UE), a mobile station (MS), a mobile terminal (MT), etc. The electronic device can be a mobile phone, a smart TV, a wearable device, a tablet computer (Pad), a computer with wireless transceiver function, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, and so on. The embodiments of the present application do not limit the specific technologies and specific device forms adopted by the electronic device.

[0044] Next, the LPDDR chip packaging structure provided by the embodiment of the present application will be described with reference to the accompanying drawings.

[0045] Please refer to Figure 1As shown in the figure, the chip packaging structure 100 provided by the embodiments of the present application includes a circuit board 101 and an LPDDR chip 102. Optionally, the circuit board 101 can be the main board of an electronic device, which serves to carry electronic components such as a target storage chip, a processor chip, and a power management chip, and to realize the electrical connection between the target storage chip, the processor chip, and the power management chip. The circuit board 101 can include, but is not limited to, a printed circuit board 101 (PCB), a flexible printed circuit 101 (FPC), and a rigid-flex circuit board 101, etc. Hereinafter, the circuit board 101 being a PCB board will be taken as an example for illustration.

[0046] In the embodiments of the present application, the LPDDR chip 102 can be an LPDDR5 chip.

[0047] In some embodiments, one side of the circuit board 101 (for example, the front side of the circuit board 101) includes a packaging area, and the LPDDR chip 102 is packaged in the packaging area and connected to the circuit board 101 through electrical connection balls 103 to form a single-channel packaging structure.

[0048] Optionally, the width of the packaging area is 0 - 8.2 mm, and the length of the packaging area is 0 - 12.4 mm. In this way, the maximum width of the packaging area is 8.2 mm, and the maximum length of the packaging area is 12.4 mm, thereby forming a single-channel packaging structure with a maximum area of 8.2 * 12.4 mm for the packaging area.

[0049] Optionally, the width of the packaging area is, for example, 8.2 mm, and the length of the packaging area is, for example, 6.2 mm. In this way, a single-channel packaging structure of 8.2 * 6.2 mm is formed, that is, this packaging structure retains one channel, and the packaging size is 1 / 2 of 8.2 * 12.4 mm, which can reduce the area of the circuit board 101 occupied by the packaging to adapt to small electronic devices such as smart phones and wearable devices such as watches, etc.

[0050] Optionally, the packaging area has a plurality of electrical connection balls 103, and the plurality of electrical connection balls 103 are arranged in an array. Exemplarily, the plurality of electrical connection balls 103 are arranged in a rectangular array. Optionally, the packaging area has 143 electrical connection balls 103, and the 143 electrical connection balls 103 are arranged in a rectangular array.

[0051] Optionally, the LPDDR chip 102 has a plurality of pins. When the LPDDR chip 102 is packaged in the packaging area, one pin is connected to one electrical connection ball 103. Optionally, the pin can be connected to the electrical connection ball 103 through a metal wiring layer. One electrical connection ball 103 corresponds to one signal point position, and then is connected to an external circuit through the pin.

[0052] Optionally, each pin has its specific function definition. Optionally, for power supply, ground, data transmission, and control signal lights. Therefore, the signal points corresponding to each electric ball 103 have specific definitions.

[0053] In the embodiment of the present application, by setting a packaging area on the circuit board 101, a single-packaging form is formed. Optionally, the width of the packaging area is 0 - 8.2 mm, and the length of the packaging area is 0 - 12.4 mm. The LPDDR chip 102 is packaged in the packaging area. The LPDDR chip 102 has multiple pins, and the multiple pins are respectively connected to the circuit board 101 through electric balls 103. One pin is connected to one electric ball 103, and one electric ball 103 corresponds to one signal point. In this way, by designing the chip packaging structure 100 as a single-channel single-packaging structure with a smaller size, the area of the circuit board 101 occupied by the packaging of the LPDDR chip 102 is saved, so that the packaging structure can be adapted to single-channel SOC and small electronic devices with a smaller packaging size, such as smart phones and wearable devices.

[0054] In the embodiment of the present application, by reducing the size of the packaging structure and re-arranging the definitions of the pins of the LPDDR chip 102, optionally, the signal points of the packaging area are also re-arranged to adapt to the reduced packaging structure.

[0055] In some embodiments, please refer to Figure 3 and Figure 4 As shown, the signal points of the packaging area of the circuit board 101 are distributed to form a first area 110 and a second area 120. Both the first area 110 and the second area 120 are flush with the same edge of the circuit board 101, and the first area 110 surrounds a part of the outside of the second area 120.

[0056] In the embodiment of the present application, by making both the first area 110 and the second area 120 formed by the signal point distribution flush with the same side edge of the circuit board 101. In this way, each pin of the LPDDR chip 102 can extend out from the same side edge of the circuit board 101 through metal wiring to be connected to an external circuit. Optionally, in Figure 2 , each pin of the LPDDR chip 102 extends out from the left edge of the circuit board 101. In this way, the wiring between the LPDDR chip 102 and the external circuit can be simplified, and the wiring difficulty can be reduced.

[0057] Optionally, in order to improve the balance and stability of the LPDDR chip 102 packaged on the circuit board 101 and increase the strength of the circuit board 101, in the embodiment of the present application, data input / output points, power input / output points, write clock points, read clock points, and differential synchronization signal points are arranged in the first area 110; a plurality of floating points are arranged in the second area 120. Optionally, ball grid arrays 103 are arranged in both the first area 110 and the second area 120. The ball grid arrays 103 in the first area 110 are connected to the pins with specific functions on the LPDDR chip 102, while the ball grid arrays 103 in the second area 120 are only physically connected to the undefined pins on the LPDDR chip 102, that is, the points in the second area 120 form floating points without the characteristic of electrical conduction, thereby improving the flatness of the LPDDR chip 102 packaged on the circuit board 101 and increasing the strength of the circuit board 101.

[0058] In some embodiments, the floating points in the second area 120 can be grounded to form ground points, so that the signals between the LPDDR chip 102 and the circuit board 101 can be protected to ensure signal stability.

[0059] Optionally, in addition to the signal points with specific definitions in the first area 110, the signal points without specific definitions can also be set as floating points or ground points, so as to increase the strength of the circuit board 101 and protect the signals to ensure signal stability.

[0060] In the embodiment of the present application, the multiple ball grid arrays 103 in the first area 110 and the second area 120 are arranged in a matrix, and the distance between any two adjacent ball grid arrays 103 is equal. In this way, the arrangement uniformity of the multiple ball grid arrays 103 in the packaging area can be improved, thereby improving the strength of the circuit board 101 and the flatness of the LPDDR chip 102 on the circuit board 101.

[0061] In some embodiments, please refer to Figure 4 As shown, the first area 110 includes a first sub-area 111, a second sub-area 112, and a third sub-area 113. The first sub-area 111 and the second sub-area 112 are arranged in sequence along the first direction. The third sub-area 113 is adjacently arranged on the same side of the first sub-area 111 and the second sub-area 112 along the second direction. Along the first direction, the overall area formed by the first sub-area 111 and the second sub-area 112 occupies at least part of the area of the third sub-area 113; and along the second direction, the second area 120 is arranged between the first sub-area 111 and the third sub-area 113; optionally, the first direction and the second direction are perpendicular to each other.

[0062] In some embodiments, in the first direction, one side edge of the first sub-region 111, the second region 120, and the third sub-region 113 is flush with the same side edge of the circuit board 101; the edge of the first sub-region 111 facing the second sub-region 112 is flush with the side edge of the second region 120 close to the second sub-region 112; the other side edge of the third sub-region 113 is flush with the side edge of the second sub-region 112 facing away from the first sub-region 111. In this way, each pin of the LPDDR chip 102 can extend out from the same side edge of the circuit board 101 through metal wiring to be connected to an external circuit; thereby simplifying the wiring between the LPDDR chip 102 and the external circuit and reducing the wiring difficulty.

[0063] In some embodiments, please continue to refer to Figure 4 As shown, the first sub-region 111 is provided with five rows and eight columns of signal points, the second sub-region 112 is provided with seven rows and five columns of signal points; the third sub-region 113 is provided with four rows and thirteen columns of signal points; optionally, a plurality of data input / output points and a plurality of power input / output points are provided in both the first sub-region 111 and the third sub-region 113, at least one of the first sub-region 111 and the third sub-region 113 is provided with a write clock point and a read clock point, and at least one of the first sub-region 111 and the third sub-region 113 is provided with a differential synchronization signal point.

[0064] Optionally, as Figure 4 shown, the signal points in the packaging area are arranged in a rectangular array, and the signal points are respectively marked as the A row, the B row, the C row, the D row, the E row, the F row, the G row, the H row, the J row, the K row, and the L row along the first direction. Each column of pins is respectively marked as the 1st column, the 2nd column, the 3rd column, the 4th column, the 5th column, the 6th column, the 7th column, the 8th column, the 9th column, the 10th column, the 11th column, the 12th column, and the 13th column from left to right.

[0065] Optionally, in the packaging area on the front side of the PCB board, the LPDDR chip is arranged in the packaging area. Optionally, a first area 110 and a second area 120 are provided. The first area 110 includes a first sub-region 111, a second sub-region 112, and a third sub-region 113. The first sub-region 111 corresponds to the 1st column to the 8th column of the A row to the E row on the PCB board. The second sub-region 112 corresponds to the 9th column to the 13th column of the A row to the G row on the PCB board; the third sub-region 113 corresponds to the 1st column to the 1th column of the H row to the L row on the PCB board; the second area 120 corresponds to the 1st column to the 8th column of the F row to the G row on the PCB board.

[0066] As Figure 4 shown, the definitions of the pins of the LPDDR chip correspond to the definitions of the signal points. Below, Figure 4Taking the LPDDR chip as an example, the definition of the signal points corresponding to each pin of the LPDDR chip is explained.

[0067] Optionally, in Figure 4 In FIG, the pin in the first column and row C of the LPDDR chip is the eleventh data input / output point of the LPDDR chip, and the pin in the first column and row E of the LPDDR chip is the fourteenth data input / output point of the LPDDR chip.

[0068] Optionally, the second column, B row of the LPDDR chip is the ninth data input / output point of the LPDDR chip, the second column, D row of the LPDDR chip is the thirteenth data input / output point of the LPDDR chip, the second column, J row of the LPDDR chip is the first data input / output point of the LPDDR chip, and the pins in the second column, C row and K row of the LPDDR chip are the input / output power points of the LPDDR chip.

[0069] Optionally, the Cth row in the third column of the LPDDR chip is the tenth data input / output point of the LPDDR chip, the Eth row in the third column of the LPDDR chip is the fifteenth data input / output point of the LPDDR chip, the Hth row in the third column of the LPDDR chip is the seventh data input / output point of the LPDDR chip, and the Ath row in the third column of the LPDDR chip is the input / output power point of the LPDDR chip.

[0070] Optionally, the fourth column, B row of the LPDDR chip is the sixteenth data input / output point of the LPDDR chip, the fourth column, J row of the LPDDR chip is the first input data mask point of the LPDDR chip, the fourth column, L row of the LPDDR chip is the second data input / output point of the LPDDR chip, and the fourth column, A row, C row, D row and E row of the LPDDR chip are respectively the input / output power points of the LPDDR chip.

[0071] Optionally, the fifth column, C row of the LPDDR chip is the second input data mask point of the LPDDR chip, the fifth column, E row of the LPDDR chip is the second data input / output point of the LPDDR chip, the fifth column, H row of the LPDDR chip is the sixth data input / output point of the LPDDR chip, the fifth column, K row of the LPDDR chip is the fifth data input / output point of the LPDDR chip, and the fifth column, A row of the LPDDR chip is the input / output power point of the LPDDR chip.

[0072] Optionally, the B row of the sixth column of the LPDDR chip is the second differential read synchronization signal point of the LPDDR chip, the D row of the sixth column of the LPDDR chip is the second read clock point of the LPDDR chip, the L row of the sixth column of the LPDDR chip is the third data input / output point of the LPDDR chip, and the C row and the J row of the sixth column of the LPDDR chip are the input / output power supply points of the LPDDR chip respectively.

[0073] Optionally, the B row of the seventh column of the LPDDR chip is the second differential read synchronization signal point of the LPDDR chip, the D row of the seventh column of the LPDDR chip is the second write clock point of the LPDDR chip, the H row of the seventh column of the LPDDR chip is the eighth data input / output point of the LPDDR chip, the K row of the seventh column of the LPDDR chip is the fourth data input / output point of the LPDDR chip, and the E row and the J row of the seventh column of the LPDDR chip are the input / output power supply points of the LPDDR chip.

[0074] Optionally, the J row of the eighth column of the LPDDR chip is the first read clock point of the LPDDR chip, and the A row and the L row of the eighth column of the LPDDR chip are the input / output power supply points of the LPDDR chip.

[0075] Optionally, the B row of the ninth column of the LPDDR chip is the third address point of the LPDDR chip, the D row of the ninth column of the LPDDR chip is the first address point of the LPDDR chip, the G row of the ninth column of the LPDDR chip is the second chip select point of the LPDDR chip, the pin of the ninth column of the LPDDR chip is the first differential read synchronization signal point of the LPDDR chip, and the C row, the E row, and the H row of the ninth column of the LPDDR chip are the input / output power supply points of the LPDDR chip 102 respectively.

[0076] Optionally, the B row of the tenth column of the LPDDR chip is the second address point of the LPDDR chip, the D row of the tenth column of the LPDDR chip is the sixth address point of the LPDDR chip, the F row of the tenth column of the LPDDR chip is the reserved point of the LPDDR chip, the G row of the tenth column of the LPDDR chip is the first chip select point of the LPDDR chip, the K row of the tenth column of the LPDDR chip is the first differential read synchronization signal point of the LPDDR chip, and the A row and the H row of the tenth column of the LPDDR chip are the input / output power supply points of the LPDDR chip respectively.

[0077] Optionally, the C row of the eleventh column of the LPDDR chip is the seventh address point of the LPDDR chip, the E row of the eleventh column of the LPDDR chip is the fourth address point of the LPDDR chip, and the D row, the J row, the K row, and the L row are the input / output power supply points of the LPDDR chip respectively.

[0078] Optionally, the C row of the twelfth column of the LPDDR chip is the fifth address point of the LPDDR chip, the F row of the twelfth column of the LPDDR chip is the differential clock signal point of the LPDDR chip, the G row of the twelfth column of the LPDDR chip is the differential clock signal point of the LPDDR chip, and the J row and the L row of the twelfth column of the LPDDR chip are the input / output power points of the LPDDR chip.

[0079] Optionally, the J row of the thirteenth column of the LPDDR chip is the driving strength calibration signal point terminal, and the C row, the D row, the K row, and the L row of the thirteenth column of the LPDDR chip are the input / output power points of the LPDDR chip respectively.

[0080] Optionally, the first column, the second column, the twelfth column, and the thirteenth column of the A row of the LPDDR chip, the first column and the thirteenth column of the B row, the second column, the fourth column, and the sixth column of the F row, the first column, the third column, the fifth column, and the seventh column of the G row of the LPDDR chip are all floating points DNU (Do Not Use) of the LPDDR chip, indicating that they should not be connected to the power supply, GND, and any other signals. These pins are only physically connected to the electrical receiving ball 103 on the circuit board 101 and have no electrical signal connection.

[0081] Optionally, the D row, the F row, the H row, the J row, the K row, and the L row of the first column of the LPDDR chip; the E row, the G row, the H row, and the L row of the second column; the B row, the D row, the F row, the J row, and the L row of the third column; the H row, the G row, and the K row of the fourth column; the B row, the D row, the F row, the J row, and the L row of the fifth column; the A row, the G row, the H row, and the K row of the sixth column; the A row, the C row, the F row, and the L row of the seventh column; the B row, the C row, the D row, the E row, the F row, the G row, and the H row of the eighth column; the A row, the F row, and the L row of the ninth column; the C row, the E row, the J row, and the L row of the tenth column; the A row, the F row, the G row, and the H row of the eleventh column; the B row, the D row, the E row, the H row, and the K row of the twelfth column; the F row, the G row, the H row, and the E row of the thirteenth column of the LPDDR chip are all ground points of the LPDDR chip to ensure the stability, safety, and reliability of the LPDDR chip signals.

[0082] In some embodiments, the positions of any two data input / output points in the first sub-region 111 can be exchanged with each other; the positions of any two data input / output points in the third sub-region 113 can be exchanged with each other. In this way, the flexibility of the point layout can be improved to reduce the difficulty of metal wiring in the circuit board 101.

[0083] In some embodiments, each of the suspended points in the first sub-region 111 and the third sub-region 113 can be selectively connected to pins with specific definitions according to specific requirements. Optionally, the suspended points can be defined as power input / output points. Of course, at least one power input / output point in at least one of the first sub-region 111 and the third sub-region 113 is formed as a suspended point to increase or decrease the number of power input / output points, thereby improving the power supply stability of the circuit board 101.

[0084] Optionally, the number of ground points can also be increased by forming the suspended points as ground points, so as to ensure that the LPDDR chip 102 can be better protected, and further improve the safety and reliability of the signals of the LPDDR chip 102.

[0085] The embodiment of the present application also provides an electronic device, which includes the chip packaging structure provided in the above embodiment, and the chip packaging structure is, for example, an LPDDR chip packaging structure.

[0086] The processor in the electronic device can be the LPDDR chip packaging structure provided above in the present application. At least one control chip is further provided on one side of the LPDDR chip packaging structure. Optionally, the control chip is connected to the electrical ball of the LPDDR chip packaging structure by a trace across the target edge.

[0087] In some embodiments, the control chip can be an SOC control chip, the SOC control chip can be a 32-bit chip, and the SOC control chip is disposed on the PCB board and electrically connected to the LPDDR chip.

[0088] In some embodiments, the SOC control chip includes a single channel, and the single channel is electrically connected to the LPDDR chip.

[0089] Optionally, the electronic device can be implemented in various forms. For example, the electronic device described in the present application can include mobile terminals such as mobile phones, tablet computers, notebook computers, palmtop computers, personal digital assistants (PDAs), portable media players (PMPs), navigation devices, wearable devices, smart bracelets, pedometers, etc., and fixed terminals such as digital TVs and desktop computers.

[0090] In the following description, mobile terminals will be taken as examples for illustration. Those skilled in the art will understand that, except for elements specifically for mobile purposes, the structure according to the embodiments of the present application can also be applied to fixed-type terminals.

[0091] Please refer to Figure 5, which is a schematic diagram of the hardware structure of a mobile terminal for implementing various embodiments of the present application. The mobile terminal 500 may include: an RF (Radio Frequency) unit 501, a WiFi module 502, an audio output unit 503, an A / V (audio / video) input unit 504, a sensor 505, a display unit 506, a user input unit 507, an interface unit 508, a memory 509, a processor 510, and a power supply 511, etc. Those skilled in the art can understand that Figure 5 the mobile terminal structure shown in

[0092] does not limit the mobile terminal. The mobile terminal may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements. Figure 5 The following specifically introduces each component of the mobile terminal:

[0093] The RF unit 501 can be used to receive and send signals during information reception or call processes. Specifically, after receiving the downlink information of the base station, it is given to the processor 510 for processing; in addition, the uplink data is sent to the base station. Usually, the RF unit 501 includes, but is not limited to, antennas, at least one amplifier, a transceiver, a coupler, a low-noise amplifier, a duplexer, etc. In addition, the RF unit 501 can also communicate with the network and other devices through wireless communication. The above wireless communication can use any communication standard or protocol, including but not limited to GSM (Global System of Mobile communication), GPRS (General Packet Radio Service), CDMA2000 (Code Division Multiple Access 2000), WCDMA (Wideband Code Division Multiple Access), TD-SCDMA (Time Division-Synchronous Code Division Multiple Access), FDD-LTE (Frequency Division Duplexing-Long Term Evolution), TDD-LTE (Time Division Duplexing-Long Term Evolution), and 5G, etc.

[0094] WiFi belongs to short - range wireless transmission technology. Through the WiFi module 502, the mobile terminal can help users send and receive emails, browse the web, and access streaming media, etc. It provides users with wireless broadband Internet access. Although Figure 5 the WiFi module 502 is shown, it can be understood that it does not belong to the essential components of the mobile terminal and can be completely omitted within the scope of not changing the essence of this application as needed.

[0095] The audio output unit 503 can convert the audio data received by the radio frequency unit 501 or the WiFi module 502 or stored in the memory 509 into an audio signal and output it as sound when the mobile terminal 500 is in call signal reception mode, call mode, recording mode, voice recognition mode, broadcast reception mode, and other modes. Moreover, the audio output unit 503 can also provide audio output related to specific functions executed by the mobile terminal 500 (such as call signal reception sound, message reception sound, etc.). The audio output unit 503 can include a speaker, a buzzer, etc.

[0096] The A / V input unit 504 is used to receive audio or video signals. The A / V input unit 504 can include a Graphics Processing Unit (GPU) 5041 and a microphone 5042. The graphics processor 5041 processes the image data of still pictures or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The processed image frames can be displayed on the display unit 506. The processed image frames can be stored in the memory 509 (or other storage media) or transmitted via the radio frequency unit 501 or the WiFi module 502. The microphone 5042 can receive sounds (audio data) via the microphone 5042 in call mode, recording mode, voice recognition mode, and other operating modes, and can process such sounds into audio data. The processed audio (voice) data can be output in a format that can be transmitted to the mobile communication base station via the radio frequency unit 501 in the case of call mode. The microphone 5042 can implement various types of noise cancellation (or suppression) algorithms to eliminate (or suppress) the noise or interference generated during the reception and transmission of audio signals.

[0097] The mobile terminal 500 further includes at least one sensor 505, such as a light sensor, a motion sensor, and other sensors. Optionally, the light sensor includes an ambient light sensor and a proximity sensor. Optionally, the ambient light sensor can adjust the brightness of the display panel 5061 according to the brightness of the ambient light, and the proximity sensor can turn off the display panel 5061 and / or the backlight when the mobile terminal 500 is moved to the ear. As a kind of motion sensor, the accelerometer sensor can detect the magnitude of acceleration in each direction (generally three axes), and can detect the magnitude and direction of gravity when stationary, and can be used in applications for identifying the posture of the mobile phone (such as horizontal and vertical screen switching, related games, magnetometer attitude calibration), vibration recognition related functions (such as pedometers, tapping), etc.; as for other sensors that the mobile phone can also be configured with, such as fingerprint sensors, pressure sensors, iris sensors, molecular sensors, gyroscopes, barometers, hygrometers, thermometers, infrared sensors, etc., they will not be elaborated here.

[0098] The display unit 506 is used to display information input by the user or information provided to the user. The display unit 506 may include a display panel 5061, and the display panel 5061 can be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), etc.

[0099] The user input unit 507 can be used to receive input digital or character information, and generate key signal inputs related to the user settings and function controls of the mobile terminal. Optionally, the user input unit 507 may include a touch panel 5071 and other input devices 5072. The touch panel 5071, also known as a touch screen, can collect touch operations of the user on or near it (such as operations of the user using a finger, a stylus, or any suitable object or accessory on or near the touch panel 5071), and drive the corresponding connection device according to a pre-set program. The touch panel 5071 can include two parts: a touch detection device and a touch controller. Optionally, the touch detection device detects the touch position of the user and detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into contact coordinates, and then sends it to the processor 510, and can receive and execute commands sent by the processor 510. In addition, the touch panel 5071 can be implemented in multiple types such as resistive, capacitive, infrared, and surface acoustic wave. In addition to the touch panel 5071, the user input unit 507 may further include other input devices 5072. Optionally, the other input devices 5072 may include, but are not limited to, one or more of a physical keyboard, function keys (such as volume control keys, power on / off keys, etc.), a trackball, a mouse, a joystick, etc., and specific details are not limited here.

[0100] Optionally, the touch panel 5071 may cover the display panel 5061. After the touch panel 5071 detects a touch operation on or near it, it is transmitted to the processor 510 to determine the type of touch event. Subsequently, the processor 510 provides a corresponding visual output on the display panel 5061 according to the type of touch event. Although in Figure 5 , the touch panel 5071 and the display panel 5061 are implemented as two independent components to realize the input and output functions of the mobile terminal, but in some embodiments, the touch panel 5071 and the display panel 5061 can be integrated to realize the input and output functions of the mobile terminal, and the specific implementation here is not limited.

[0101] The interface unit 508 serves as an interface through which at least one external device can be connected to the mobile terminal 500. For example, the external device may include a wired or wireless headset port, an external power supply (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device with an identification module, an audio input / output (I / O) port, a video I / O port, a headset port, and so on. The interface unit 508 can be used to receive inputs from external devices (such as data information, power, etc.) and transmit the received inputs to one or more components within the mobile terminal 500 or can be used to transmit data between the mobile terminal 500 and external devices.

[0102] The memory 509 can be used to store software programs and various data. The memory 509 mainly includes a program storage area and a data storage area. Optionally, the program storage area can store an operating system, applications required for at least one function (such as a sound playback function, an image playback function, etc.); the data storage area can store data created according to the use of the mobile phone (such as audio data, phone book, etc.). In addition, the memory 509 can include high-speed random access memory and can also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices.

[0103] The processor 510 is the control center of the mobile terminal, connecting various parts of the entire mobile terminal using various interfaces and lines. By running or executing software programs and / or modules stored in the memory 509, and calling data stored in the memory 509, it performs various functions of the mobile terminal and processes data, thereby monitoring the mobile terminal as a whole. The processor 510 may include one or more processing units; preferably, the processor 510 may integrate an application processor and a modem processor. Optionally, the application processor mainly processes the operating system, user interface, and application programs, etc., and the modem processor mainly processes wireless communication. It can be understood that the above-mentioned modem processor may not be integrated into the processor 510.

[0104] The mobile terminal 500 may further include a power source 511 (such as a battery) for powering each component. Preferably, the power source 511 may be logically connected to the processor 510 through a power management system, so as to implement functions such as management of charging, discharging, and power consumption management through the power management system.

[0105] Although Figure 5 not shown, the mobile terminal 500 may further include a Bluetooth module, etc., which will not be elaborated here.

[0106] It can be understood that the above scenarios are only examples and do not constitute a limitation on the application scenarios of the technical solutions provided by the embodiments of the present application. The technical solutions of the present application can also be applied to other scenarios. For example, as is known to those of ordinary skill in the art, with the evolution of the system architecture and the emergence of new service scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0107] The technical features of the technical solutions of the present application can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope recorded in the present application.

[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip packaging structure, characterized in that, include: A circuit board comprising a packaging area, wherein the width of the packaging area is 0 to 8.2 mm, and the length of the packaging area is 0 to 12.4 mm; An LPDDR chip is packaged in the packaging area, the LPDDR chip having a plurality of pins, wherein the plurality of pins are electrically connected to the circuit board via a plurality of electrical balls; wherein one pin is connected to one electrical ball, and one electrical ball corresponds to one signal point; The packaging area includes a first area and a second area, and a plurality of grounding points and suspended points are arranged in the second area.

2. The chip packaging structure according to claim 1, wherein, The width of the packaging area is 8.2 mm, and the length of the packaging area is 6.2 mm.

3. The chip packaging structure according to claim 1 or 2, wherein The first area and the second area are both flush with the same edge of the circuit board, and the first area is arranged around a portion of the outside of the second area; data input / output points, power input / output points, write clock points, read clock points and differential synchronization signal points are arranged in the first area.

4. The chip packaging structure according to claim 3, wherein The first region includes a first sub-region, a second sub-region, and a third sub-region, wherein the first sub-region and the second sub-region are arranged sequentially along a first direction, and the third sub-region is adjacently arranged on the same side of the first sub-region and the second sub-region along a second direction. Along the first direction, the entire region formed by the first sub-region and the second sub-region occupies at least a portion of the third sub-region; Along the second direction, the second region is arranged between the first sub-region and the third sub-region; the first direction and the second direction are perpendicular to each other.

5. The chip package structure according to claim 4, characterized in that, In the first direction, one side edge of the first sub-region, the second region, and the third sub-region are all flush with the same side edge of the circuit board; the edge of the first sub-region facing the second sub-region is flush with the edge of the second region close to the second sub-region; the other side edge of the third sub-region is flush with the edge of the second sub-region facing away from the first sub-region.

6. The chip packaging structure according to claim 5, wherein, The first sub-area is provided with five rows and eight columns of signal points, the second sub-area is provided with seven rows and five columns of signal points; the third sub-area is provided with four rows and thirteen columns of signal points; and / or The first sub-area and the third sub-area are both provided with a plurality of data input and output points and a plurality of power input and output points, at least one of the first sub-area and the third sub-area is provided with a write clock point and a read clock point, and at least one of the first sub-area and the third sub-area is provided with a differential synchronization signal point.

7. The chip packaging structure according to claim 6, wherein The positions of any two data input and output points in the first sub-area can be interchanged; and / or, Positions of any two data input and output points in the third sub-area can be interchanged.

8. The chip packaging structure according to claim 6, wherein At least one of the first sub-region and the third sub-region has at least one hanging point; or, At least one of the power input / output points in at least one of the first sub-area and the third sub-area is configured as a floating point.

9. The chip packaging structure according to claim 8, wherein The at least one floating point is configured to be grounded.

10. An electronic device, characterized in that, Including the chip packaging structure according to any one of claims 1 to 9.

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