Double gate oxide MOS structure

Abstract

The utility model provides a double-gate oxide MOS (Metal Oxide Semiconductor) structure, which comprises a substrate, a high-voltage well region and a low-voltage well region, the low-voltage well region comprises a thin gate oxide layer and a low-voltage side gate which are located on the surface of the low-voltage well region, and low-voltage side source / drain regions which are located in the low-voltage well region and located on the two sides of the low-voltage side gate, and the high-voltage well region comprises a high-voltage side gate oxide layer and a high-voltage side gate which are located on the surface, a drift region located in the high-voltage well region, and high-voltage side source / drain regions located on the two sides of the high-voltage side gate oxide layer; the high-voltage side gate oxide layer comprises a thick gate oxide layer and a first field oxide layer which are arranged in an overlapped mode in the gate length direction and only covers the high-voltage side gate instead of covering the whole high-voltage well region, so that a thick film layer exists in a region corresponding to the high-voltage side gate in the follow-up manufacturing process of the polycrystalline silicon gate, and when the polycrystalline silicon layer is etched to form the two gates, the high-voltage side gate oxide layer is formed. The residual film difference of other regions is small, so that LDD injection and the injection dose and depth of the source / drain region can be accurately controlled, and the electrical performance and reliability of the double-gate oxide MOS structure are further improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and particularly relates to a double-gate-oxide MOS structure. Background Art

[0002] The double-gate-oxide process is one of the important processes for manufacturing MOS integrated circuits. It can fabricate MOS devices with two voltage levels on the same wafer substrate to meet the requirements of high- and low-voltage applications of the overall circuit. Among them, the gate breakdown voltage is the key factor for distinguishing high- and low-voltage MOS devices. The thickness of the gate oxide layer of the low-voltage MOS device is less than that of the high-voltage MOS device.

[0003] However, for the device structure formed according to the existing technology, when the thickness difference between the gate oxide layer of the low-voltage MOS device and that of the high-voltage MOS device is relatively large, for example, the thickness of the thin gate oxide layer in a 5V low-voltage MOS device is about 120 angstroms, and the thickness of the thick gate oxide layer in a 40V high-voltage MOS device is about 550 angstroms, with a difference of about 430 angstroms between them, the difference in the residual film thickness after polysilicon etching will inevitably be relatively large. The existence of this situation will not only affect the dose and depth of the lightly doped drain (LDD) implantation in the subsequent high- and low-voltage MOS devices, but also cause deviations in the dose and depth of the source and drain regions in the high- and low-voltage MOS devices from the target values, thereby affecting the electrical performance and reliability of the double-gate-oxide MOS structure. Summary of the Utility Model

[0004] In order to overcome the above defects, the utility model provides a double-gate-oxide MOS structure, which can effectively solve the above problems brought about by the large difference in the residual film thickness after polysilicon etching between the low-voltage MOS device and the high-voltage MOS device, and improve the electrical performance and reliability of the double-gate-oxide MOS structure.

[0005] The double-gate-oxide MOS structure provided by the utility model includes:

[0006] A substrate, including a low-voltage region and a high-voltage region. A low-voltage well region extending from one surface of the substrate into the substrate is provided in the low-voltage region, and a high-voltage well region extending from one surface of the substrate into the substrate is provided in the high-voltage region, and the low-voltage well region and the high-voltage well region are arranged at intervals;

[0007] A low-voltage MOS device located in the low-voltage region, including a thin gate oxide layer and a low-voltage side gate electrode stacked on the surface of the low-voltage well region, and a low-voltage side source region and a low-voltage side drain region located in the low-voltage well region, and the low-voltage side source region and the low-voltage side drain region are respectively located on both sides of the low-voltage side gate electrode;

[0008] The high-voltage MOS device located in the high-voltage region includes a high-voltage side gate oxide layer and a high-voltage side gate electrode stacked on the surface of the high-voltage well region, a drift region disposed in the high-voltage well region, and a high-voltage side source region and a high-voltage side drain region located in the high-voltage well region. The high-voltage side source region and the high-voltage side drain region are respectively located on both sides of the high-voltage side gate oxide layer. The high-voltage side source region is located outside the drift region, and the high-voltage side drain region is located inside the drift region.

[0009] Among them, the high-voltage side gate oxide layer includes a thick gate oxide layer and a first field oxide layer overlapping along the gate length direction. The thickness of the thick gate oxide layer is greater than the thickness of the thin gate oxide layer, and the thickness of the first field oxide layer is greater than the thickness of the thick gate oxide layer. The positive projection of the high-voltage side gate electrode on the substrate surface is located within the positive projection of the high-voltage side gate oxide layer on the substrate surface.

[0010] Further, in the double-gate-oxide MOS structure described above, one side of the thick gate oxide layer away from the first field oxide layer extends beyond the same-side edge of the high-voltage side gate electrode by a predetermined distance. One side of the first field oxide layer away from the thick gate oxide layer extends beyond the same-side edge of the high-voltage side gate electrode.

[0011] Further, in the double-gate-oxide MOS structure described above, the predetermined distance is set in a ratio of 3:4 to 3:5 with the thickness of the thick gate oxide layer.

[0012] Further, in the double-gate-oxide MOS structure described above, the positive projection of the thick gate oxide layer on the substrate surface partially overlaps with the positive projection of the drift region on the substrate surface.

[0013] Further, in the double-gate-oxide MOS structure described above, a first doped region is provided in the low-voltage well region. The doping type of the first doped region is the same as that of the low-voltage well region, and the doping concentration of the first doped region is greater than that of the low-voltage well region. The first doped region extends from the substrate surface into the substrate. The shape of the positive projection of the first doped region on the substrate surface is annular and surrounds the low-voltage side source region and the low-voltage side drain region.

[0014] A second doped region is provided in the high-voltage well region. The doping type of the second doped region is the same as that of the high-voltage well region, and the doping concentration of the second doped region is greater than that of the high-voltage well region. The second doped region extends from the substrate surface into the substrate. The shape of the positive projection of the second doped region on the substrate surface is annular and surrounds the high-voltage side source region and the high-voltage side drain region.

[0015] Further, in the double-gate-oxide MOS structure described above, a second field oxide layer is further provided on the surface of the low-voltage well region. The positive projection of the second field oxide layer on the substrate surface is annular and located inside the positive projection of the first doped region on the substrate surface, and surrounds the low-voltage side source region and the low-voltage side drain region;

[0016] A third field oxide layer is further provided on the surface of the high-voltage well region. The projection of the third field oxide layer on the substrate surface is annular and located inside the positive projection of the second doped region on the substrate surface, and surrounds the high-voltage side source region and the high-voltage side drain region.

[0017] Further, in the double-gate-oxide MOS structure described above, an isolation structure is further included, and the isolation structure isolates the low-voltage well region and the high-voltage well region.

[0018] Further, in the double-gate-oxide MOS structure described above, the isolation structure includes an isolation region located in the high-voltage region, and the high-voltage well region is located in the isolation region.

[0019] Further, in the double-gate-oxide MOS structure described above, the isolation structure further includes a fourth field oxide layer, and the fourth field oxide layer is located at the junction of the low-voltage region and the high-voltage region.

[0020] Further, in the double-gate-oxide MOS structure described above, a fifth field oxide layer is further provided on the surface of the high-voltage well region, and the fifth field oxide layer is located between the isolation region and the high-voltage well region.

[0021] In the double-gate-oxide MOS structure provided by the present invention, a high-voltage side gate oxide layer that only surrounds the high-voltage side gate is provided in the high-voltage well region. The high-voltage side gate oxide layer includes a thick gate oxide layer and a first field oxide layer that are overlapped along the gate length direction, and the high-voltage side gate oxide layer is located between the high-voltage side source region and the high-voltage side drain region, rather than covering the entire high-voltage well region. During the subsequent process of fabricating the polysilicon gate, after the polysilicon layer is formed, there is a relatively thick silicon oxide film layer in the region corresponding to the high-voltage side gate. When etching the polysilicon layer to form the high-voltage side gate and the low-voltage side gate, except for the region covered by LOCOS, the difference in the residual silicon oxide film on the surface of other regions is relatively small. In this way, when performing source / drain region implantation and possible LDD implantation, the implantation dose and depth can be controlled more accurately, thereby improving the electrical performance and reliability of the double-gate-oxide MOS structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Referring to the accompanying drawings, the disclosure of the present invention will become more understandable. It is easy for those skilled in the art to understand that these drawings are only for the purpose of illustration and are not intended to limit the protection scope of the present invention. In addition, similar numbers in the drawings are used to represent similar structures or regions, where:

[0023] Figure 1It is a schematic plan view of an existing double-gate-oxide MOS structure;

[0024] Figure 2 It is a schematic plan view of a double-gate-oxide MOS structure according to an embodiment of the present invention;

[0025] Figure 3 It is a sectional view of a double-gate-oxide MOS structure according to an embodiment of the present invention;

[0026] Figure 4a It is a schematic diagram of the side drilling phenomenon occurring at the edge position of the contact surface between the thick gate oxide layer and the high-voltage side gate;

[0027] Figure 4b It is a schematic diagram of a partial structure of a double-gate-oxide MOS structure according to an embodiment of the present invention;

[0028] Figures 5a to 5j It is to form Figure 3 The structure schematic diagram corresponding to some process steps of the shown double-gate-oxide MOS structure. Detailed implementation manners

[0029] To make the above objects, features and advantages of the present invention more obvious and understandable, the following will describe the detailed implementation manners of the present invention in conjunction with the accompanying drawings. Many specific details are set forth in the following description in order to fully understand the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0030] In the description of the present invention, terms such as "first", "second", etc. are only used for descriptive and distinguishing purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. In addition, in the present invention, unless otherwise clearly specified and limited, terms such as "connected" and "coupled" should be understood in a broad sense. For example, they can be directly connected or indirectly connected through an intermediate medium, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0031] For MOS devices, since different gate voltages need to be applied in different application scenarios, it is required that MOS devices can withstand different high and low voltages. The double-gate-oxide process can fabricate MOS devices with two voltage levels on the same wafer substrate to meet the requirements of the overall circuit for high- and low-voltage applications.

[0032] Figure 1 It is a schematic plan view of an existing double-gate-oxide MOS structure, as Figure 1As shown in the figure, the double-gate-oxide MOS structure includes a low-voltage MOS device located on the left side of the substrate 10 in the figure, a high-voltage MOS device on the right side, and an isolation region 21 for isolation. Among them, the low-voltage MOS device includes a source region and a drain region (collectively referred to as the low-voltage side source / drain region 13a) located in the low-voltage well region 17a and a low-voltage side gate 11a located on the surface of the low-voltage well region 17a. In addition, a first doping region 20a is also provided in the low-voltage well region 17a. The doping type of the first doping region 20a is the same as that of the low-voltage well region 17a, and it is used to connect the source electrode and the low-voltage well region 17a serving as the body region. Similarly, the high-voltage MOS device includes a source region and a drain region (collectively referred to as the high-voltage side source / drain region 13b) located in the high-voltage well region 17b and a high-voltage side gate 11b located on the surface of the high-voltage well region 17b. In addition, a second doping region 20b and a drift region 15 are also provided in the high-voltage well region 17b. The second doping region 20b is used to connect the source electrode and the high-voltage well region 17b serving as the body region; the drain region of the high-voltage MOS device is located in the drift region 15, and the source region is located outside the drift region 15, that is, this high-voltage MOS device is an asymmetric structure.

[0033] Continuing to refer to Figure 1 , for the high-voltage MOS device, the entire surface of the high-voltage well region 17b is covered by the oxide layer 18'. In this way, during the subsequent process of fabricating the polysilicon gate, when etching the polysilicon layer to simultaneously form the low-voltage side gate 11a and the high-voltage side gate 11b, since the film layer in the region other than the region corresponding to the high-voltage well region 17b is thinner, the remaining film after etching is also relatively thinner, while the film layer in the region corresponding to the high-voltage well region 17b is thicker, and the remaining film after etching is relatively thicker. If the difference in the gate oxide layer thickness between the low-voltage MOS device and the high-voltage MOS device is large, it will cause a large difference in the remaining film thickness between the low-voltage MOS device and the high-voltage MOS device after polysilicon etching. In this way, it will not only affect the dose and depth of the LDD implantation of the high-low voltage MOS structure, but also cause a deviation between the implantation dose and depth of the source / drain region and the target value, thereby affecting the electrical performance and reliability of the double-gate-oxide MOS structure.

[0034] To solve the above technical problems, the present utility model optimizes the existing double-gate-oxide MOS structure, and the following is a detailed description in conjunction with the accompanying drawings.

[0035] Figure 2 and Figure 3 are respectively a plan view and a cross-sectional view of a double-gate-oxide MOS structure according to an embodiment of the present utility model. As Figures 2 to 3 shown, the double-gate-oxide MOS structure includes a substrate 10, and the substrate 10 includes a low-voltage region L and a high-voltage region H. Among them, a low-voltage well region 17a is provided in the low-voltage region L, and a high-voltage well region 17b is provided in the high-voltage region H. Both the low-voltage well region 17a and the high-voltage well region 17b extend from the surface on one side of the substrate 10 (i.e., the so-called front side) to the surface on the other side of the substrate 10 (i.e., the so-called back side).

[0036] It should be noted that the "high-pressure region" and the "low-pressure region" are only named for convenience of description and distinction, representing different regions. Additionally, although in the figure the high-pressure region H is located on the right side of the low-pressure region L and they are adjacent to each other, in reality, this is not limited to this. The low-pressure region L can also be located in other orientations of the high-pressure region H, and even they may not be adjacent.

[0037] The dual-gate-oxide MOS structure provided in this embodiment includes a low-voltage MOS device located in the low-pressure region L and a high-voltage MOS device located in the high-pressure region H. Among them, the structure of the low-voltage MOS device is similar to that of the low-voltage MOS device in the existing dual-gate-oxide MOS structure, including a low-voltage side source / drain region 13a located in the low-voltage well region 17a. The low-voltage side source / drain region 13a is a general term for the low-voltage side source region and the low-voltage side drain region, and both extend from the surface of the low-voltage well region 17a into the low-voltage well region 17a. Between the low-voltage side source region and the low-voltage side drain region is the channel region of the low-voltage MOS device. On the surface of the low-voltage well region 17a, a thin gate oxide layer 12a and a low-voltage side gate 11a are stacked. The thin gate oxide layer 12a and the low-voltage side gate 11a are located between the low-voltage side source region and the low-voltage side drain region. In other words, the thin gate oxide layer 12a covers the channel region, and the low-voltage side gate 11a covers the thin gate oxide layer 12a.

[0038] A first doping region 20a is also provided in the low-voltage well region 17a. The doping type of the first doping region 20a is the same as that of the low-voltage well region 17a, and the doping concentration is higher than that of the low-voltage well region 17a, which is used to electrically connect the source electrode and the low-voltage well region 17a as the body region. The first doping region 20a extends from the surface of the substrate 10 into the substrate 10. The positive projection of the first doping region 20a on the surface of the substrate 10 is annular and surrounds the positive projections of the low-voltage side source / drain region 13a and the low-voltage side gate 11a on the surface of the substrate 10.

[0039] A second field oxide layer 182 is also provided in the low-pressure region L to isolate the low-voltage side source / drain region 13a and the first doping region 20a. The positive projection of the second field oxide layer 182 on the surface of the substrate 10 is annular. The positive projection of the first doping region 20a on the surface of the substrate 10 surrounds the positive projection of the second field oxide layer 182 on the surface of the substrate 10, and the positive projection of the second field oxide layer 182 on the surface of the substrate 10 surrounds the low-voltage side source / drain region 13a.

[0040] In this embodiment, the low-voltage MOS device may also include sidewalls located on both sides of the low-voltage side gate 11a and an LDD region 22 located below the low-voltage side gate 11a. The specific structures of the sidewalls and the LDD region 22 can refer to the prior art and are not particularly limited.

[0041] Such as Figure 2 and Figure 3As shown in the figure, the high-voltage MOS device includes a drift region 15 and a high-voltage side source / drain region 13b located within the high-voltage well region 17b. Both the drift region 15 and the high-voltage side source / drain region 13b extend from the surface of the high-voltage well region 17b into the high-voltage well region 17b. Among them, the doping concentration of the drift region 15 is higher than that of the high-voltage well region 17b. The high-voltage side source / drain region 13b is a general term for the high-voltage side source region and the high-voltage side drain region. The high-voltage side drain region is located within the drift region 15, and the high-voltage side source region is located outside the drift region 15. The channel region is between the high-voltage side source region and the drift region 15. In other words, this high-voltage MOS device has an asymmetric structure. A high-voltage side gate oxide layer 18 is provided on the surface of the high-voltage well region 17b. The high-voltage side gate oxide layer 18 is located between the high-voltage side source region and the high-voltage side drain region, that is, the high-voltage side gate oxide layer 18 covers the channel region between the high-voltage side source region and the high-voltage side drain region; a high-voltage side gate electrode 11b is provided on the high-voltage side gate oxide layer 18.

[0042] Different from the prior art, in this embodiment, the high-voltage side gate oxide layer 18 in the high-voltage MOS device only partially covers the high-voltage well region 17b. Specifically, in the positive projection on the surface of the substrate 10, the high-voltage side gate oxide layer 18 is located between the high-voltage side source region and the high-voltage side drain region and extends beyond the high-voltage side source region and the high-voltage side drain region along the gate width direction.

[0043] Furthermore, the high-voltage side gate oxide layer 18 includes a thick gate oxide layer 12b and a first field oxide layer 181, and the two overlap partially in the gate length direction, that is, in the geometric sense, the first field oxide layer 181 and the thick gate oxide layer 12b penetrate into each other. Among them, the thickness of the first field oxide layer 181 is greater than the thickness of the thick gate oxide layer 12b, and the thickness of the thick gate oxide layer 12b is greater than the thickness of the thin gate oxide layer 12a.

[0044] The high-voltage side gate electrode 11b covers the high-voltage side gate oxide layer 18, and the positive projection of the high-voltage side gate electrode 11b on the surface of the substrate 10 is located within the positive projection of the high-voltage side gate oxide layer 18 on the surface of the substrate 10. Since the thickness of the first field oxide layer 181 is greater than the thickness of the thick gate oxide layer 12b, the high-voltage side gate electrode 11b forms a height difference, that is, a step, in the overlapping region of the first field oxide layer 181 and the thick gate oxide layer 12b. In fact, the part of the high-voltage side gate electrode 11b located above the first field oxide layer 181 functions as a field plate. In this way, when a voltage is applied to the gate, the surface electric field of the substrate 10 can be dispersed, thereby improving the breakdown performance of the high-voltage MOS device.

[0045] Furthermore, the positive projection of the thick gate oxide layer 12b on the surface of the substrate 10 partially overlaps with the positive projection of the drift region 15 on the surface of the substrate 10; the positive projection of the high-voltage side gate electrode 11b on the substrate 10 also partially overlaps with the positive projection of the drift region 15 on the surface of the substrate 10.

[0046] Unless otherwise specified, in the description of this embodiment, the gate length direction refers to the direction from the source region to the drain region or from the drain region to the source region, that is, the gate length direction is consistent with the channel length direction; the gate width direction is perpendicular to the gate length direction, and both are perpendicular to the substrate thickness direction.

[0047] A second doped region 20b is further provided in the high-voltage well region 17b. The doping type of the second doped region 20b is the same as that of the high-voltage well region 17b, and the doping concentration is higher than that of the high-voltage well region 17b, which is used to connect the source electrode and the high-voltage well region 17b as the body region; the second doped region 20b extends from the front surface of the substrate 10 into the substrate 10, and the positive projection on the surface of the substrate 10 is annular, surrounding the positive projections of the high-voltage side source / drain region 13b, the high-voltage side gate 11b, the high-voltage side gate oxide layer 18, and the drift region 15 on the surface of the substrate 10.

[0048] A third field oxide layer 183 is further provided in the high-voltage well region 17b to isolate the high-voltage side source / drain region 13b and the second doped region 20b. The positive projection of the third field oxide layer 183 on the surface of the substrate 10 is annular; the positive projection of the second doped region 20b on the surface of the substrate 10 surrounds the positive projection of the third field oxide layer 183 on the surface of the substrate 10, and the positive projection of the third field oxide layer 183 on the surface of the substrate 10 surrounds the positive projections of the high-voltage side source / drain region 13b, the high-voltage side gate 11b, the high-voltage side gate oxide layer 18, and the drift region 15 on the surface of the substrate 10.

[0049] In a specific implementation process, the first field oxide layer 181, the second field oxide layer 182, and the third field oxide layer 183 are all formed by the LOCOS process, that is, the three can be formed in the same process flow.

[0050] An isolation structure may also be provided between the low-voltage well region 17a and the high-voltage well region 17b. Specifically, a suitable isolation structure can be selected according to actual requirements, so as to effectively isolate the high-voltage MOS device and the low-voltage MOS device, or isolate the high-voltage MOS device from other components. Figure 2 and Figure 3 In the shown embodiment, the high-voltage MOS device and the low-voltage MOS device are arranged adjacent to each other. In fact, in other embodiments, other semiconductor devices may also be provided between the high-voltage MOS device and the low-voltage MOS device. Therefore, the isolation structure can be selected according to actual isolation requirements.

[0051] In this embodiment, the isolation structure includes an isolation region 21 located in the high-voltage region H, and the high-voltage well region 17b is located in the isolation region 21. Specifically, the doping depth of the isolation region 21 is greater than that of the high-voltage well region 17b, and the positive projection of the high-voltage well region 17b on the surface of the substrate 10 is located within the positive projection of the isolation region 21 on the surface of the substrate 10. A fifth field oxide layer 185 may also be provided on the surface of the substrate 20 between the isolation region 21 and the high-voltage well region 17b.

[0052] In addition, the isolation structure may further include a fourth field oxide layer 184, and the fourth field oxide layer 184 covers at least the region where the high-voltage region H and the low-voltage region L meet. In other embodiments, a suitable isolation method may also be selected according to actual conditions, such as STI isolation.

[0053] For the double-gate-oxide MOS structure of this embodiment, in terms of the orthographic projection on the surface of the substrate 10, a thick gate oxide layer 12b and a first field oxide layer 181 that only surround the high-voltage side gate 11b and are overlapped are provided in the high-voltage well region 17b. The thick gate oxide layer 12b and the first field oxide layer 181 are located between the high-voltage side source region and the high-voltage side drain region, rather than covering the entire high-voltage well region 17b. In the subsequent process of fabricating the polysilicon gate, after forming the polysilicon layer, without considering the LOCOS structure, only the region corresponding to the high-voltage side gate 11b has a relatively thick film layer. When over-etching the polysilicon layer to form the high-voltage side gate and the low-voltage side gate, the difference in the remaining oxide film in other regions is relatively small. In this way, when performing source / drain region implantation and possible LDD implantation, the implantation dose and depth can be more accurately controlled, thereby improving the electrical performance and reliability of the high-low voltage MOS structure.

[0054] It should be noted that for Figure 1 the existing structure shown, since the high-voltage side gate oxide layer 18 covers the entire high-voltage well region 17b, in the subsequent self-aligned silicide (Salicide) process, during the process of lithography and etching of the deposited metal silicide barrier layer to expose the silicon and polysilicon regions of the substrate 10 where Salicide needs to be formed, the following problems occur: After the metal silicide barrier layer in the region corresponding to the low-voltage well region 17a is etched away to expose the silicon surface, in the region corresponding to the high-voltage well region 17b, due to the relatively thick remaining film after polysilicon etching, the silicon substrate 10 surface has not been exposed yet and still needs to be etched. In this way, damage to the silicon substrate 10 surface will be caused in the region corresponding to the low-voltage well region 17a, thereby causing deterioration of the performance of the low-voltage MOS device, reduction in reliability, and even failure.

[0055] However, for the double-gate-oxide MOS structure provided in this embodiment, since the difference in the remaining oxide film in the region corresponding to the high-voltage well region 17b and other regions outside the field oxide layer is eliminated when etching the polysilicon layer to form the high-voltage side gate 11b and the low-voltage side gate 11a, the metal silicide barrier layers in other regions can be etched away at the same time to expose the silicon surface, avoiding the influence on the performance and reliability of the low-voltage MOS device.

[0056] In a specific implementation process, when preparing the thick gate oxide layer 12b, usually a silicon oxide layer is first deposited, and then a photoresist layer serving as a mask is formed in the area where the thick gate oxide layer 12b needs to be formed. Then, the silicon oxide layer in the area not covered by the photoresist is wet-etched to remove the silicon oxide layer in this area, and the oxide layer covered by the photoresist layer is retained as the thick gate oxide layer. In practice, when forming the high-voltage side gate 11b subsequently, side-drilling is likely to occur at the edge part where the thick gate oxide layer 12b contacts the high-voltage side gate 11b. Fig. 4 is a schematic diagram of side-drilling occurring at the contact surface between the thick gate oxide layer 12b and the high-voltage side gate 11b. Some device structures are omitted here for the convenience of showing the side-drilling phenomenon, and the side-drilling position is denoted as M.

[0057] Regarding the above side-drilling phenomenon, in this solution, the side of the thick gate oxide layer 12b away from the first field oxide layer 181 extends a predetermined distance s beyond the same-side edge of the high-voltage side gate 12b, as shown in Figure 4b . After verification, when the predetermined distance s and the thickness of the thick gate oxide layer 12b are set in the ratio of 3:4 to 3:5, side-drilling can be effectively avoided.

[0058] Since the first field oxide layer 181 is provided on the other side of the high-voltage side gate 11b, the first field oxide layer 181 extends beyond the high-voltage side gate 11b, and the thickness of the first field oxide layer 181 is greater than the thickness of the thick gate oxide layer 12b. Therefore, during the wet-etching process, side-drilling hardly occurs at the contact surface between the first field oxide layer 181 and the other side of the high-voltage side gate 11b.

[0059] The following will Figures 5a to 5j make a detailed description of some process steps for forming Figures 2 - 3 the double-gate-oxide MOS structure shown.

[0060] S1. In the high-voltage region H of the substrate 10, an isolation region 21 and a high-voltage well region 17b are successively formed, where the high-voltage well region 17b is located within the region defined by the isolation region 21, as shown in Figure 5a .

[0061] Among them, the substrate 10 can be a silicon substrate 10 or other suitable materials. The substrate 10 includes a high-voltage region H and a low-voltage region L. Here, the high-voltage region H and the low-voltage region L are only for convenient description, meaning the regions for fabricating high-voltage MOS devices and low-voltage MOS devices respectively, and the two can be adjacent or non-adjacent. The isolation region 21 can be formed by ion implantation, and the specific doping concentration and doping type are determined according to the required isolation effect; the doping type of the high-voltage well region 17b is the same as that of the substrate 10, and the doping concentration of the high-voltage well region 17b is higher than that of the substrate 10.

[0062] S2. Through photolithography and ion implantation, a drift region 15 is formed in the high-voltage well region 17b, as shown in Figure 5bAs shown, the ion implantation depth of the drift region 15 is less than that of the high-voltage well region 17b. Combining Figure 2 and Figure 3 As shown, considering the double-gate-oxide MOS structure provided in this embodiment, the high-voltage MOS device is an asymmetric structure, that is, there is only one drift region 15 in the high-voltage well region 16, and the subsequently formed drain region is located within the drift region 15 and the source region is located outside the drift region 15. Therefore, in this step, the drift region 15 is not located in the middle region of the high-voltage well region 16, but is biased in the direction away from the low-voltage region L. Among them, the doping type of the drift region 15 is the same as that of the high-voltage well region 17b, and the doping concentration of the drift region 15 is higher than that of the high-voltage well region 17b.

[0063] S3. Deposit silicon nitride or other hard mask materials on the surface of the substrate 10 and perform patterning, and then use the thermal oxidation method to grow a thick oxide layer in the area not covered by the hard mask material. Subsequently, remove the hard mask material to form a LOCOS structure on the surface of the substrate 10 as shown in Figure 5c shown.

[0064] Among them, the thick oxide layer at the junction of the low-voltage region L and the high-voltage region H, that is, the fourth field oxide layer 184, also serves as an isolation structure. In other embodiments, STI or other isolation methods can also be used at the junction of the two. In addition, in the structure shown in this embodiment, the low-voltage region L and the high-voltage region H are adjacent, but this is not limited thereto. <——

[0065] In the thick oxide layer located in the low-voltage region L, the second field oxide layer 182 projects in a ring shape on the surface of the substrate 10 and is also located within the subsequently formed low-voltage well region 17a, and is used to isolate the subsequently formed first doping region 20a and the low-voltage side source / drain region 13a.

[0066] In the thick oxide layer located in the high-voltage region H, the middle first field oxide layer 181 is located between the subsequently formed high-voltage side source / drain regions 13b; in the thick oxide layer surrounding the first field oxide layer 181, in the order from the inside to the outside, the third field oxide layer 183 is used to isolate the second doping region 20b and the high-voltage side source / drain region 13b, and the subsequent fifth field oxide layer 185 is located between the high-voltage well region 17b and the isolation region 21, and the outermost thick oxide layer surrounds the isolation region 21.

[0067] S4. Through photolithography and ion implantation, form a low-voltage well region 17a in the low-voltage region L of the substrate 10, as shown in Figure 5d shown. The ion doping type of the low-voltage well region 17a is the same as that of the substrate 10, and the doping concentration of the low-voltage well region 17a is higher than that of the substrate 10. The low-voltage well region 17a and the isolation region 21 are arranged at intervals, and the two are separated by the fourth field oxide layer 184. The ion implantation depth of the low-voltage well region 17a can be lower than that of the high-voltage well region 17b.

[0068] S5. First gate oxide layer growth: The first gate oxide layer is grown by a thermal oxidation method, such as wet oxidation, as shown in Figure 5e . The thickness of the first gate oxide layer is greater than the target thickness of the thin gate oxide layer 12a and slightly less than the thickness of the thick gate oxide layer 12b. For example, if the target thickness of the thick gate oxide layer 12b is 550 ± 50 Å, the thickness of the first gate oxide layer can be 480 - 490 Å. At this time, the entire surface of the substrate 10 is covered with an oxide layer, including the first gate oxide layer formed in this step and the LOCOS field oxide layer formed in step S4, that is, the patterns of the two formed oxide layers are complementary. Since the thickness of the LOCOS is much greater than the thickness of the first gate oxide layer, during the growth of the first gate oxide layer, the diffusion rate of the oxidant in the LOCOS field oxide layer is relatively slow. Therefore, the influence of the growth of the first gate oxide layer on the LOCOS field oxide layer can be ignored.

[0069] S6. Form a patterned photoresist layer on the first gate oxide layer, as shown in Figure 5f . Among them, the patterned photoresist layer is used to define the thick gate oxide layer 12b located on the surface of the high-voltage well region 17b.

[0070] S7. Wet-etch the oxide layer not covered by the photoresist layer. Using the patterned photoresist layer as a mask, wet-etch the first gate oxide layer and the LOCOS field oxide layer. Since the thickness of the LOCOS is much greater than the thickness of the first gate oxide layer, after wet-etching, the thickness of the LOCOS structure decreases but still remains. Finally, the structure shown in Figure 5g is formed, and then the patterned photoresist layer is completely removed to form the structure shown in Figure 5h . It is not difficult to understand that the remaining first gate oxide layer partially overlaps with the first field oxide layer 181, and the two form a whole.

[0071] S8. Perform the growth of the second gate oxide layer to form the structure shown in Figure 5i . Through the growth of the second gate oxide layer, the thickness of the oxide layer on the surface of the substrate 10, especially the oxide layer that partially overlaps with the first field oxide layer 181, increases to the target value to form the thick gate oxide layer 12b. The thick gate oxide layer 12b and the first field oxide layer 181 are still an integral structure as the high-voltage side gate oxide layer 18; the thickness of the oxide layer in the remaining area (except LOCOS) on the surface of the substrate 10 reaches the target thickness of the thin gate oxide layer 12a.

[0072] In a specific implementation process, the growth of the gate oxide layer is carried out twice using a thermal oxidation process method, such as wet oxidation. By controlling the reaction conditions of wet oxidation, such as temperature, pressure, and the composition of the oxidant, the growth rate and thickness of the gate oxide layer can be precisely regulated. During the two growth processes, these conditions can be independently optimized to ensure that the thickness of the gate oxide layer grown each time meets the expectations. By superimposing the thicknesses of the gate oxides grown twice, the thick gate oxide layer 12b in the high-voltage well region 17b can be precisely controlled to be, for example, 550 ± 50 Å, and the thickness of the gate oxide layer in the low-voltage well region 17a can be precisely controlled to be 120 ± 10 Å through single-time wet oxidation growth, ultimately achieving effective control of the performance of high-voltage MOS devices and low-voltage MOS devices.

[0073] S9. Deposit a polysilicon layer on the surface of the substrate 10 and perform patterning on the polysilicon layer to obtain the gates of the device, including the high-voltage side gate 11b and the low-voltage side gate 11a, as Figure 5j shown.

[0074] It should be noted that to ensure complete etching of the polysilicon layer, an over-etching method is usually required, that is, etching a part of the oxide layer under the polysilicon layer. The remaining oxide layer acts as a barrier layer during the subsequent ion implantation process; if there are significant differences in the thickness of the barrier layer in different regions on the surface of the substrate 10, it is difficult to accurately control the depth and dose of ion implantation. Due to the design of step S8, the difference in the thickness of the remaining oxide layer after etching the polysilicon layer is controlled. Specifically, except for the regions corresponding to the thick gate oxide layer 12b and the LOCOS structure, the other regions are all the second gate oxide layers with uniform thickness. In this way, after over-etching the polysilicon, the thickness of the remaining second gate oxide layer is still relatively consistent. Therefore, during the subsequent processes such as ion implantation to form source / drain regions, the dose and depth of ion implantation can be effectively controlled and can be closer to or even reach the target values.

[0075] In addition, as Figure 5j and Figure 4b shown, there is a predetermined distance between the edge of the high-voltage side gate 11b and the left edge of the thick gate oxide layer 12b, and this predetermined distance is set according to 3:4 to 3:5 with the thickness of the thick gate oxide layer 12b.

[0076] S10. Perform processes such as LDD implantation, sidewall process, and source / drain implantation to obtain the Figure 3 double-gate-oxide MOS structure shown, where these processes can refer to existing related technologies and will not be elaborated here.

[0077] S11. Perform the Salicide process. First, deposit a metal silicide barrier layer. After lithography and etching processes, the substrate silicon and polysilicon regions where Salicide needs to be formed are exposed. Here, there is no residual film difference in the high- and low-pressure well regions after polysilicon etching. After the metal silicide barrier layer in the low-pressure well region 17a is etched to expose the surface of the substrate 10, the metal silicide barrier layer in the high-pressure well region 17b is also etched to completion to expose the surface of the substrate 10. Therefore, the design of this double-gate oxide MOS structure can effectively avoid the problem of performance degradation of low-voltage MOS devices caused by residual film differences after etching. Among them, the Salicide process can refer to existing related technologies and will not be elaborated here.

[0078] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the protection scope of the present invention.

Claims

1. A dual-gate-oxide MOS structure, characterized in that Including: A substrate including a low-voltage region and a high-voltage region. A low-voltage well region extending from one surface of the substrate into the substrate is provided in the low-voltage region, and a high-voltage well region extending from one surface of the substrate into the substrate is provided in the high-voltage region. The low-voltage well region and the high-voltage well region are spaced apart. A low-voltage MOS device located in the low-voltage region, including a thin gate oxide layer and a low-voltage side gate electrode stacked on the surface of the low-voltage well region, and a low-voltage side source region and a low-voltage side drain region located in the low-voltage well region. The low-voltage side source region and the low-voltage side drain region are respectively located on both sides of the low-voltage side gate electrode. A high-voltage MOS device located in the high-voltage region, including a high-voltage side gate oxide layer and a high-voltage side gate electrode stacked on the surface of the high-voltage well region, a drift region provided in the high-voltage well region, and a high-voltage side source region and a high-voltage side drain region located in the high-voltage well region. The high-voltage side source region is located outside the drift region, the high-voltage side drain region is located inside the drift region, and the high-voltage side source region and the high-voltage side drain region are respectively located on both sides of the high-voltage side gate oxide layer. Wherein, the high-voltage side gate oxide layer includes a thick gate oxide layer and a first field oxide layer overlapping along the gate length direction. The thickness of the thick gate oxide layer is greater than the thickness of the thin gate oxide layer, and the thickness of the first field oxide layer is greater than the thickness of the thick gate oxide layer. The positive projection of the high-voltage side gate electrode on the substrate surface is located within the positive projection of the high-voltage side gate oxide layer on the substrate surface.

2. The dual-gate oxide MOS structure according to claim 1, wherein One side of the thick gate oxide layer away from the first field oxide layer extends beyond the same-side edge of the high-voltage side gate electrode by a predetermined distance. One side of the first field oxide layer away from the thick gate oxide layer extends beyond the same-side edge of the high-voltage side gate electrode.

3. The double-gate-oxide MOS structure according to claim 2, wherein The predetermined distance and the thickness of the thick gate oxide layer are set in a ratio of 3:4 to 3:

5.

4. The double-gate-oxide MOS structure according to claim 1, characterized in that, The positive projection of the thick gate oxide layer on the substrate surface partially overlaps with the positive projection of the drift region on the substrate surface.

5. The double-gate-oxide MOS structure according to any one of claims 1 to 4, characterized in that, A first doping region is provided in the low-voltage well region. The doping type of the first doping region is the same as that of the low-voltage well region, and the doping concentration of the first doping region is greater than that of the low-voltage well region. The first doping region extends from the substrate surface into the substrate, and the shape of the positive projection of the first doping region on the substrate surface is annular and surrounds the low-voltage side source region and the low-voltage side drain region. A second doping region is provided in the high-voltage well region. The doping type of the second doping region is the same as that of the high-voltage well region, and the doping concentration of the second doping region is greater than that of the high-voltage well region. The second doping region extends from the substrate surface into the substrate, and the shape of the positive projection of the second doping region on the substrate surface is annular and surrounds the high-voltage side source region and the high-voltage side drain region.

6. The double-gate-oxide MOS structure according to claim 5, wherein A second field oxide layer is further provided on the surface of the low-voltage well region. The positive projection of the second field oxide layer on the substrate surface is annular and located inside the positive projection of the first doping region on the substrate surface, and surrounds the low-voltage side source region and the low-voltage side drain region. A third field oxide layer is further provided on the surface of the high-voltage well region. The projection of the third field oxide layer on the substrate surface is annular and located inside the positive projection of the second doping region on the substrate surface, and surrounds the high-voltage side source region and the high-voltage side drain region.

7. The double-gate-oxide MOS structure according to any one of claims 1 to 4, characterized in that, It further includes an isolation structure, and the isolation structure isolates the low-voltage well region and the high-voltage well region.

8. The double-gate-oxide MOS structure according to claim 7, wherein The isolation structure includes an isolation region located in the high-voltage region, and the high-voltage well region is located within the isolation region.

9. The double-gate-oxide MOS structure according to claim 8, wherein The isolation structure further includes a fourth field oxide layer, and the fourth field oxide layer is located at the junction of the low-voltage region and the high-voltage region.

10. The dual-gate-oxide MOS structure according to claim 8, characterized in that, A fifth field oxide layer is further provided on the surface of the high-voltage well region, and the fifth field oxide layer is located between the isolation region and the high-voltage well region.

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