Liquid crystal display (LCD) bias source driving circuit
By controlling the switching timing and using LCD parasitic capacitors as filter capacitors, the ripple problem caused by multiple capacitors in the prior art is solved, and the LCD display quality is improved.
Patent Information
- Application Number
- CN202422277386.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-18
- Publication Date
- 2025-08-05
- Estimated Expiration
- 2034-09-18
AI Technical Summary
The existing LCD bias drive circuit requires multiple filter capacitors to generate a multi-voltage bias voltage, resulting in a large discharge depth of capacitors, which generates ripple, affects the display quality.
The parasitic capacitor of the LCD is used as the filter capacitor, and the timing working cycle of the switch is controlled to charge the large-period capacitor and discharge it in small-period cycles to reduce the discharge depth, and use parasitic capacitors to replace the traditional filter capacitors.
It realizes that without increasing the number of capacitors, reduce the discharge depth, avoid the influence of ripple, and improve the LCD display quality.
Smart Images
Figure CN223193534U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to an LCD bias source driving circuit, and more particularly to a bias generator for a liquid crystal display, in which the highest potential stabilizing capacitor value can be built into an integrated circuit to provide a capacitive bias drive for the LCD, thereby reducing the number of peripheral electronic components in the LCD bias source driving circuit. Background Art
[0002] The LCD bias driving circuits in the prior art all need to be equipped with a variety of bias voltage values (thresholds) as the multiple voltage driving circuits for the LCD, such as Figure 1 The figure shows the bias voltage waveform of the existing 3-fold voltage (V1, V2, V3) threshold. Figure 2 and Figure 3 The figure shows the existing 3 times threshold timing control circuit diagram and bias voltage circuit diagram. Since the bias voltage of 3 times voltage needs to be generated, most of them use capacitor voltage division or voltage technology to generate it. Therefore, each bias voltage needs a filter capacitor to store charge. Figure 4 As shown in FIG. 1 , it is a timing waveform diagram of 3 times the bias voltage.
[0003] As shown in Table 1 below Figure 3 Switching timing table of bias voltage circuit:
[0004] Table 1
[0005] Time S1 S2 S3 S4 S5 S6 illustrate t0 ON OFF OFF OFF ON OFF <![CDATA[C1 charging, potential V1 (V C1 Potential = V1)]]> t1 OFF ON OFF ON OFF OFF <![CDATA[V C2 =V C1 +V1=V1+V1=2*V1]]> t2 ON OFF OFF OFF ON OFF <![CDATA[V C1 Potential = V1 t3 OFF OFF ON OFF OFF ON <![CDATA[V C3 =V C2 +V1=2*V1+V1=3*V1]]>
[0006] Please also refer to Figures 2 to 4 As shown in Table 1, the potential difference between the two ends of the C1 filter capacitor is V C1 =V CB -V CA At t0, the S6 switch is in OFF state, V C3 The voltage needs to be maintained by the capacitor C3. When the timing is t1, the switch S3 is OFF, and V C2 The voltage needs to be maintained by the capacitor C2. When the timing is t2, the switches S3 and S6 are OFF, and V C2 、V C3 The voltage needs to be maintained by capacitors C2 and C3. When the timing is t3, the switches S1, S2, S4, and S5 are in the OFF state, and V C1 The voltage needs to be maintained by capacitor C1, V C2 The voltage needs to be maintained by the C2 capacitor and V C3 The voltage needs to be maintained by capacitor C3.
[0007] Therefore, when the capacitance value is fixed, the longer the switch OFF time is, the greater the discharge depth will be than 1 times V1. The greater the discharge depth, the greater the ripple. The V C3 、V C2The size of the ripple caused by charging and discharging is affected by the size of the filter capacitors C2 and C3. The larger the capacitance, the smaller the ripple, and vice versa. The larger the ripple, the worse the LCD display quality. Utility Model Content
[0008] To address these shortcomings, the present invention aims to provide an LCD bias source driver circuit that utilizes a sequential duty cycle to control switching, enabling multiple bias voltages to be generated by long-cycle capacitor charging and short-cycle discharge. This allows the parasitic capacitance on the LCD to serve as a multiplier filter capacitor, eliminating the need for a single capacitor compared to conventional designs. Because the clock duty cycle is significantly longer than the filter capacitor's discharge time, the filter capacitor's discharge depth is minimal, eliminating ripples caused by the small capacitance of the parasitic capacitor, which can affect LCD display quality.
[0009] To achieve the above-mentioned object, the present invention provides an LCD bias source driving circuit, comprising: a first switch connected between a ground terminal and a voltage doubling capacitor, the voltage doubling capacitor having a bias terminal and a voltage doubling terminal; a second switch connected between the bias terminal and a reference potential terminal; a third switch connected between the reference potential terminal and the voltage doubling terminal; a first capacitor connected between the reference potential terminal and the ground terminal, one end of the voltage doubling capacitor being connected to the voltage doubling capacitor; and a voltage doubling switch, wherein when the first switch is on and the second switch is off, the first capacitor is charged to a reference potential. When the first and third switches are on and the second switch is off, the voltage doubling capacitor is charged to the reference potential. When the first and third switches are off and the second switch is on, the potential at the voltage doubling end is the reference potential plus the charging voltage of the voltage doubling capacitor. The voltage doubling switch is coupled to the parasitic capacitor in the LCD as a filter capacitor. The parasitic capacitor can filter the potential at the voltage doubling end, thereby achieving the purpose of replacing the filter capacitor with the parasitic capacitor of the LCD, and by reducing the capacitor discharge time period, the discharge depth is very small without generating ripples due to too small capacitance.
[0010] In one embodiment of the above-mentioned LCD bias source driving circuit of the present invention, it also includes: a fourth switch connected between the bias terminal and a voltage doubling filter terminal; a second capacitor connected between the voltage doubling filter terminal and the ground terminal; and a fifth switch connected between the voltage doubling filter terminal and the voltage doubling terminal. When the fourth switch is turned on, the second capacitor is charged with twice the reference potential; and when the fifth switch is turned on and the fourth switch is turned off, the second capacitor begins to discharge slowly, forming a filter with twice the reference potential.
[0011] In one embodiment of the LCD bias source driving circuit of the present invention, the first, second, third, fourth, fifth switches and the voltage doubling switch can be packaged into an integrated circuit (IC), which only has pins for the voltage doubling capacitor, the first capacitor, the second capacitor and the parasitic capacitor.
[0012] In an embodiment of the present invention, the voltage doubling switch is connected to the bias terminal of the voltage doubling capacitor.
[0013] In one embodiment of the present invention, the output potential of the voltage doubler terminal is twice the reference potential.
[0014] In one embodiment of the present invention, the first switch and the third switch are controlled by a clock signal, and the second switch and the voltage doubling switch are controlled by an inverse clock signal.
[0015] In an embodiment of the present invention, the duty cycle of the clock signal is greater than 50%.
[0016] In an embodiment of the present invention, the reverse clock signal is formed by the clock signal passing through an inverter, and the duty cycle of the reverse clock signal is greater than that of the clock signal.
[0017] In one embodiment of the present invention, a discharge depth of the parasitic capacitor can be changed by adjusting the duty cycle of the clock signal of the first switch to the third switch and the voltage doubling switch, so that the longer the duty cycle of the clock signal, the shorter the discharge time of the parasitic capacitor and the smaller the discharge depth.
[0018] In an embodiment of the present invention, the voltage doubling switch is connected to the voltage doubling end of the voltage doubling capacitor.
[0019] In one embodiment of the present invention, the output potential of the voltage doubler terminal is three times the reference potential.
[0020] In one embodiment of the present invention, the first switch, the third switch and the fifth switch are controlled by a first clock signal, and the second switch, the fourth switch and the voltage doubling switch are controlled by a second clock signal, and the duty cycle of the first clock signal is twice that of the second clock signal. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 This is the bias voltage waveform of the existing 3-fold voltage (V1, V2, V3) threshold.
[0022] Figure 2 This is the timing control circuit diagram of the existing 3 times threshold.
[0023] Figure 3 This is the circuit diagram of the bias voltage that is 3 times the existing threshold.
[0024] Figure 4 This is the timing waveform diagram of the existing 3 times threshold.
[0025] Figure 5 This is a double voltage driving circuit diagram of the first embodiment of the utility model.
[0026] Figure 6 for Figure 5 2x voltage drive timing waveform.
[0027] Figure 7 This is a diagram of a triple voltage driving circuit according to the second embodiment of the present invention.
[0028] Figure 8 for Figure 7 3 times the voltage drive timing waveform.
[0029] Figure 9 This is a schematic diagram of the integrated circuit circuit of the utility model.
[0030] Explanation of reference numerals: 11 - first switch (S1); 12 - voltage-doubling capacitor (C BIAS ); 13- second switch (S2); 14- first capacitor (C1); 15- third switch (S3); 16- voltage doubling switch (S BIAS ); 17- ground terminal (GND); 18- bias terminal (V CA ); 19-voltage-multiplier terminal (V CB ); 20 - reference potential terminal (V1); 21 - parasitic capacitance (C3); 22 - fourth switch (S4); 23 - voltage doubling filter terminal (V2); 24 - second capacitor (C2); 25 - fifth switch (S5); 26 - integrated circuit; V1 - reference potential; CLK - clock signal; CLKB - reverse clock signal; V C1 - first capacitor (C1) potential; V C2 -The potential of the second capacitor (C2); V C3 - Parasitic capacitance (C3) potential; V CA -Bias terminal potential; V CB -The potential of the voltage doubler terminal. DETAILED DESCRIPTION
[0031] Since the LCD bias driver circuit needs to be matched with a driver circuit with multiple bias voltage values such as 2x voltage, 3x voltage, etc., please refer to Figure 5 and Figure 6 As shown in FIG. 1 , it is a double voltage driving circuit diagram and double voltage driving timing waveform diagram of the first embodiment of the present invention. The LCD bias source driving circuit of the present invention can generate double bias voltage, and is composed of a first switch (S1) 11, a voltage doubling capacitor (C BIAS ) 12, a second switch (S2) 13, a first capacitor (C1) 14, a third switch (S3) 15 and a voltage doubling switch (S BIAS ) 16, wherein the first switch 11 is connected between a ground terminal (GND) 17 and a voltage-doubling capacitor 12, and the voltage-doubling capacitor 12 has a bias terminal (V CA )18 and one-time voltage terminal (VCB )19.
[0032] Please also refer to Figure 5 and Figure 6 As shown, the second switch 13 is connected between the bias terminal 18 and a reference potential terminal 20, and the first capacitor 14 is connected between the reference potential terminal 20 and the ground terminal 17. When the first switch is ON (conducting) and the second switch is OFF (disconnected), the first capacitor 14 is charged to a reference potential V1. The first switch 11 is controlled by a clock signal CLK, and the second switch 13 is controlled by an inverted clock signal CLKB. The inverted clock signal CLKB is generated by passing the clock signal CLK through an inverter (not shown). The duty cycle of the clock signal CLK is greater than 50%, and the duty cycle of the inverted clock signal CLKB is slightly greater than that of the clock signal CLK.
[0033] The third switch 15 is connected between the reference potential terminal 20 and the voltage doubling terminal 19. When the first and third switches are turned on and the second switch is turned off, the voltage doubling capacitor 12 is charged to the reference potential V1. When the first and third switches are turned off and the second switch is turned on, the potential of the voltage doubling terminal 19 (V CB ) is the reference potential V1 plus the charging voltage of the voltage-doubling capacitor 12, that is, twice the reference potential 2*V1.
[0034] In this embodiment, one end of the voltage doubling switch 16 is connected to the bias terminal 18 of the voltage doubling capacitor 12, and the other end of the voltage doubling switch 16 is coupled to the parasitic capacitor 21 in the LCD as a filter capacitor. The parasitic capacitor 21 can adjust the potential (V CB ) for filtering. The third switch is controlled by the clock signal (CLK), while the voltage doubling switch is controlled by the reverse clock signal (CLKB). Figure 6 As shown in Table 2 below, Table 2 is the switching timing table for 2 times the bias voltage:
[0035] Table 2
[0036] Time S1 S2 S3 <![CDATA[S BIAS ]]> illustrate t0 ON OFF ON OFF <![CDATA[C B Charging V1 potential (VC BIAS Potential difference = V1) t1 OFF ON OFF ON <![CDATA[V CB Potential = VC BIAS +V1=V1+V1=2*V1
[0037] The discharge depth of the parasitic capacitor 21 can be changed by adjusting the duty cycle of the clock signal (CLK) of the first to third switches (S1-S3) and the voltage doubler switch 16. The greater the duty cycle of the clock signal (CLK), the shorter the discharge time of the parasitic capacitor and the smaller the discharge depth. CB , and the smaller the discharge depth, the less likely it is to produce ripples due to too small a capacitance.
[0038] See also Figure 7 and Figure 8As shown, it is a 3x voltage driving circuit diagram and a 3x voltage driving timing waveform diagram of the second embodiment of the present invention. Compared with the 2x voltage driving circuit, the 3x voltage driving circuit of the present invention has a fourth switch (S4) 22, a voltage doubling filter terminal (V2) 23, a second capacitor (C2) 24 and a fifth switch (S5) 25. The fourth switch 22 is connected between the bias terminal 18 and the voltage doubling filter terminal (V2) 23, and the second capacitor 24 is connected between the voltage doubling filter terminal 23 and the ground terminal 17. When the fourth switch is turned on, a 2x reference potential (2*V1) charges the second capacitor 24.
[0039] The fifth switch 25 is connected between the voltage doubling filter terminal 23 and the voltage doubling terminal 19. When the fifth switch 25 is ON (conducting) and the fourth switch 22 is OFF (disconnected), the discharge period of the second capacitor 24 is short, forming a filter with a voltage potential twice that of the reference potential. In this embodiment, the voltage doubling switch 16 is connected to the voltage doubling terminal 19 of the voltage doubling capacitor 12. The output potential (V CB ) is 3 times the reference potential (3*V1).
[0040] Please refer to Figure 8 As shown in Table 3 below, Table 3 is the switching timing table of 3 times the bias voltage:
[0041] Table 3
[0042]
[0043] The first, third and fifth switches 11, 15 and 25 are controlled by a first clock signal CLK1, while the second and fourth switches 13 and 22 and the voltage doubling switch 16 are controlled by a second clock signal CLK2. The duty cycle of the first clock signal CLK1 is twice that of the second clock signal CLK2. In this embodiment, the voltage doubling capacitor (C BIAS ) 12 is replaced by parasitic capacitor 21, because in the working cycle (Frame) of the first clock CLK1, the voltage doubling capacitor (C BIAS )12 has a very short discharge time in the timing. If the ratio of the duty cycle of the first clock CLK1 to the duty cycle of the second clock CLK2 is 1:9, then the voltage doubling capacitor (C BIAS )12 has a discharge time of only 15%. If the ratio of the duty cycle of the first clock CLK1 to the duty cycle of the second clock CLK2 is 1:99, then the voltage doubling capacitor (C BIAS )12 has a discharge time of only 1.5%. Similarly, the larger the ratio of the duty cycle of the first clock CLK1 to the duty cycle of the second clock CLK2, the longer the voltage doubling capacitor (C BIAS )12, the shorter the discharge time, the voltage doubling capacitor (C BIAS )12 is replaced by parasitic capacitor 21 and no ripple will be generated.
[0044] See also Figure 9 Figure 2 shows a schematic diagram of an integrated circuit circuit of the present invention. The first, second, third, fourth, and fifth switches, as well as the voltage doubling switch, are packaged within an integrated circuit (IC) 26. This IC 26 only has pins for the voltage doubling capacitor 12, the first capacitor 14, the second capacitor 24, and the parasitic capacitor 21. Similarly, if a 4x voltage bias drive circuit is required, only 3 capacitors are required, achieving an N-1 voltage-multiplying LCD drive circuit architecture.
Claims
1. An LCD bias source driving circuit capable of generating multiple bias voltages, characterized in that: include: a first switch connected between a ground terminal and a voltage-doubling capacitor, wherein the voltage-doubling capacitor has a bias terminal and a voltage-doubling terminal; a second switch connected between the bias terminal and a reference potential terminal; a first capacitor connected between the reference potential terminal and the ground terminal, configured to charge the first capacitor to a reference potential when the first switch is on and the second switch is off; a third switch connected between the reference potential terminal and the voltage-doubling terminal, configured to charge the voltage-doubling capacitor to the reference potential when the first and third switches are on and the second switch is off, and to set the potential of the voltage-doubling terminal to the reference potential plus the charging voltage of the voltage-doubling capacitor when the first and third switches are off and the second switch is on; and A voltage doubling switch has one end connected to the voltage doubling capacitor and is coupled to a parasitic capacitor in the LCD as a filter capacitor. The parasitic capacitor can filter the potential of the voltage doubling end.
2. The LCD bias source driving circuit according to claim 1, wherein: The voltage doubling switch is connected to the bias terminal of the voltage doubling capacitor.
3. The LCD bias source driving circuit according to claim 2, wherein: The output potential of the voltage doubler terminal is twice the reference potential.
4. The LCD bias source driving circuit according to claim 1, wherein: The first switch and the third switch are controlled by a clock signal, and the second switch and the voltage doubling switch are controlled by an inverse clock signal.
5. The LCD bias source driving circuit according to claim 4, wherein: The duty cycle of the clock signal is greater than 50%.
6. The LCD bias source driving circuit according to claim 5, wherein: The reverse clock signal is formed by the clock signal passing through an inverter, and the duty cycle of the reverse clock signal is greater than that of the clock signal.
7. The LCD bias source driving circuit according to claim 6, wherein: A discharge depth of the parasitic capacitor can be changed by adjusting the duty cycle of the clock signal of the first switch to the third switch and the voltage doubler switch, so that the longer the duty cycle of the clock signal is, the shorter the discharge time of the parasitic capacitor is and the smaller the discharge depth is.
8. The LCD bias source driving circuit according to claim 1, wherein: Also includes: a fourth switch connected between the bias terminal and a voltage doubling filter terminal; a second capacitor connected between the voltage doubler filter terminal and the ground terminal, for charging the second capacitor with a voltage twice the reference potential when the fourth switch is turned on; and A fifth switch is connected between the voltage doubling filter terminal and the voltage doubling terminal, so that when the fifth switch is on and the fourth switch is off, the discharge period of the second capacitor is short, thereby forming a filter with twice the reference potential.
9. The LCD bias source driving circuit according to claim 8, wherein: The voltage doubling switch is connected to the voltage doubling end of the voltage doubling capacitor.
10. The LCD bias source driving circuit according to claim 9, wherein: The output potential of the voltage doubler terminal is three times the reference potential.
11. The LCD bias source driving circuit according to claim 8, wherein: The first switch, the third switch and the fifth switch are controlled by a first clock signal, and the second switch, the fourth switch and the voltage doubling switch are controlled by a second clock signal. The duty cycle of the first clock signal is twice that of the second clock signal.
12. The LCD bias source driving circuit according to claim 8, wherein: The first switch, the second switch, the third switch, the fourth switch, the fifth switch and the voltage doubling switch are packaged in an integrated circuit. The integrated circuit has pins for the voltage doubling capacitor, the first capacitor, the second capacitor and the parasitic capacitor.