Power module
By embedding the power chip and integrating two single-phase power zones through a full-bridge method, using silicon gel or epoxy resin shell, the problem of high packaging cost and large space of existing motor drive modules is solved, and the efficient integration and stability of the power module is achieved.
Patent Information
- Application Number
- CN202422344888.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2025-08-05
- Estimated Expiration
- 2034-09-25
AI Technical Summary
The existing motor-driven power modules have problems such as high packaging cost, complex packaging process and large space.
The power chip is embedded in the full bridge method. By integrating two single-phase power zones, multiple power chips are directly packaged together, and silicon gel or epoxy resin is used as the shell material to save the shell and simplify the process.
The power module is small assembled, low cost and high power applicability, which improves the reliability and stability of the packaging structure, simplifies heat dissipation and circuit power consumption, and avoids failure caused by a single power chip due to differences in electrical performance.
Smart Images
Figure CN223193815U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of power semiconductors, in particular to a power module. Background Art
[0002] In existing motor-driven power modules, there are multiple ways to achieve power inversion (DC-AC-DC). Based on the differences in motor terminal applications, there are also different ways to achieve power inversion. Currently, the power modules that achieve terminal motor drive include:
[0003] One approach is to combine multiple power chip single-transistor devices in series and parallel according to the corresponding bridge power structure, leveraging the switching characteristics of each single-transistor device for terminal motor drive. However, the use of a combination of TO single-transistor devices for drive requires a large amount of PCB space on the PCB drive control board, resulting in significant interference between devices and high PCB board stray emissions, placing higher demands on the PCB's heat dissipation capabilities. Furthermore, each single-transistor device must be individually connected to a heat sink, making installation complex and unfavorable for integrated heat dissipation. Furthermore, each single-transistor device requires processes such as wire bonding and plastic encapsulation, which is costly.
[0004] The second type is plastic-encapsulated integrated 2-in-1, 3-in-1, and 6-in-1 modules based on the Quad Flat Package (QFP) process. These modules are similar to single-tube packages encapsulated with epoxy molding. However, plastic-encapsulated integrated modules using the QFP process are complex, have long processing cycles, and are expensive due to their plastic encapsulation.
[0005] The third is to use high-power modules packaged in existing mature plastic shells such as HPD and HP1. On the one hand, their size is large and requires a larger space for layout in the motor; on the other hand, the packaging cost of this module is relatively high.
[0006] Therefore, existing motor-driven power modules have problems such as high packaging cost, complex packaging process, and large space occupation. Utility Model Content
[0007] The embodiment of the present application solves the technical problems of high packaging cost, complex packaging process and large space occupied by motor-driven power modules in the prior art by providing a power module, and realizes the advantages of small assembly volume, low cost and high power applicability of the power module, so that the power module can realize large-scale integration of power devices, avoiding the technical effects such as large space occupied, high cost and unsuitable power brought by integrated power modules or single-tube combination driving motors.
[0008] In a first aspect, an embodiment of the present invention provides a power module, comprising: a power substrate, and a housing packaged and connected to the power substrate;
[0009] Two single-phase power areas are provided on the front metal layer of the power substrate; each of the single-phase power areas includes N power chips, and a phase current power output pin, a first gate pin, a second gate pin, a first source pin, and a second source pin connected to the N power chips, where N is a positive even number greater than 3;
[0010] In each of the single-phase power zones, the N power chips include a first power chips group and a second power chips group, the number of power chips in the first power chips group and the second power chips group are both N / 2, the power chips of the first power chips group are connected one-to-one with the power chips of the second power chips group, the phase current power output pin, the first gate pin and the first source pin are all connected to the first power chips group, and the second gate pin and the second source pin are both connected to the second power chips group.
[0011] Preferably, in the first power chipset of each of the single-phase power zones, the gate of each power chip of the first power chipset is commonly connected to the first gate pin; the source of each power chip of the first power chipset is commonly connected to the first source pin and the phase current power output pin, and the drain of each power chip of the first power chipset is commonly connected.
[0012] Preferably, in the second power chipset of each of the single-phase power zones, the gate of each power chip of the second power chipset is commonly connected to the second gate pin, the source of each power chip of the second power chipset is commonly connected to the second source pin, and the drain of a power chip of the second power chipset is connected to the source of a power chip of the first power chipset of the single-phase power zone.
[0013] Preferably, it also includes: a negative region and at least one positive region, the positive region is provided with a positive region pin, the negative region is provided with a negative region pin, the drain of each power chip of the first power chipset group of each single-phase power region is commonly connected to the positive region pin, and the source of each power chip of the second power chipset group of each single-phase power region is commonly connected to the negative region pin.
[0014] Preferably, it further comprises: at least one thermistor and a temperature sampling pin for each thermistor, wherein the thermistor is arranged in the first power chipset and / or the second power chipset in the single-phase power area.
[0015] Preferably, it further comprises: a current sensing resistor and a current sampling pin of the current sensing resistor, wherein the current sensing resistor is arranged in the negative electrode area.
[0016] Preferably, it also includes: a fixed bubble point, which is arranged on the front metal layer and the back metal layer of the power substrate, and the thickness of the fixed bubble point is less than the thickness of the front metal layer and less than the thickness of the back metal layer.
[0017] Preferably, the method further comprises: a stress release hole, wherein the stress release hole is arranged between the power chips.
[0018] Preferably, the material of the shell is at least one of silicone gel and epoxy resin.
[0019] Preferably, the power chip is a MOSFET chip or an IGBT chip and an FRD chip connected in parallel, and the power substrate is any one of a DBC ceramic substrate, a TFC ceramic substrate, a TPC ceramic substrate, an aluminum substrate, an AMB ceramic substrate, a DPC ceramic substrate and a LAM ceramic substrate.
[0020] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:
[0021] In this embodiment, by setting the packaging structure of the power module, a power chip is embedded in each single-phase power zone in a full-bridge manner, which greatly increases the output power of a single phase zone and provides a power module solution for three-phase motor drive of more than 2kW. Each single-phase power zone integrates multiple power chips. By integrating two single-phase power zones, multiple power chips are further rationally designed and directly packaged and integrated together, thereby realizing large-scale integration of power devices and improving the reliability and stability of the packaging structure of the power module. Compared with traditional power devices, the assembly volume of the power module packaging structure is greatly reduced, the product process is simplified, and the shell material is saved. In this way, the packaging structure of the power module is highly integrated, the creepage gap is reduced, and it is more conducive to heat dissipation of the entire device. Compared with the single-tube power chip device arranged on the circuit board, the power module of this embodiment highly integrates multiple power chips, reduces the internal resistance of multiple power chips stacked together, reduces the power consumption of multiple chips to the circuit, reduces the creepage distance, and avoids the increase in circuit power consumption caused by the large internal resistance of multiple power chips and the impact of large creepage distance on operation. To a certain extent, it solves the problems of single device failure caused by uneven power consumption and poor heat dissipation due to individual differences of single power chip 102 devices (small electrical performance differences between single-tube power chips 102 and single-tube power chips 102). BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. Throughout the accompanying drawings, the same reference figures denote the same components. In the accompanying drawings:
[0023] Figure 1 The figure shows the appearance and structure of the power module in the embodiment of the present utility model;
[0024] Figure 2 A schematic structural diagram of a power substrate in an embodiment of the present utility model is shown;
[0025] Figure 3 Shows a circuit schematic diagram of a power module in an embodiment of the present utility model;
[0026] Figure 4 The circuit principle diagram of the packaging structure of the power module with N=4 in the embodiment of the present utility model is shown.
[0027] In the accompanying drawings, 101 is a power substrate; 200 is a housing; 102 is a power chip; 103 is a phase current power output pin; 104 is a first gate pin; 105 is a second gate pin; 106 is a first source pin; 107 is a second source pin; 108 is a positive region pin; 109 is a negative region pin; 110 is a thermistor; 111 is a temperature sampling pin; 112 is a current sensing resistor; 113 is a current sampling pin; and 114 is a bubble point. DETAILED DESCRIPTION
[0028] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
[0029] Example 1
[0030] The first embodiment of the present utility model provides a power module, such as Figure 1 and Figure 2 As shown, it includes: a power substrate 101, and a packaging shell 200 that is packaged and connected to the power substrate 101. Figure 2As shown, two single-phase power zones are provided on the front metal layer of the power substrate 101. Each single-phase power zone includes N power chips 102, and phase current power output pins 103, first gate pins 104, second gate pins 105, first source pins 106, and second source pins 107 connected to the N power chips 102. N is a positive even number greater than 3. N can be 4 or 6.
[0031] In each single-phase power zone, the N power chips 102 include a first power chips group and a second power chips group. The number of power chips 102 in the first power chips group and the second power chips group is N / 2. The power chips 102 of the first power chips group are connected one-to-one with the power chips 102 of the second power chips group. The phase current power output pin 103, the first gate pin 104 and the first source pin 106 are all connected to the first power chips group, and the second gate pin 105 and the second source pin 107 are both connected to the second power chips group.
[0032] It should be noted that in this embodiment Figure 1-Figure 3 In the figure, N=6 power chips 102 are used to illustrate the structure and connection relationship of the single-phase power area. Figure 2 In the figure, the pins represented by the letter G are gate pins. G1 and G2 respectively represent the first gate pin 104 of each single-phase power zone. G1 is the first gate pin 104 of the first single-phase power zone, and G2 is the first gate pin 104 of the second single-phase power zone. G3 and G4 respectively represent the second gate pin 105 of each single-phase power zone. G3 is the second gate pin 105 of the first single-phase power zone, and G4 is the second gate pin 105 of the second single-phase power zone.
[0033] The pins represented by the letter S are source pins. S1 and S2 represent the first source pin 106 of each single-phase power zone, respectively. S1 is the first source pin 106 of the first single-phase power zone, and S2 is the first source pin 106 of the second single-phase power zone. S3 and S4 represent the second source pin 107 of each single-phase power zone, respectively. S3 is the second source pin 107 of the first single-phase power zone, and S4 is the second source pin 107 of the second single-phase power zone. The pins represented by the letter I are phase current power output pins 103. I1 and I2 are the phase current power output pins 103 of each single-phase power zone, respectively. I1 is the phase current power output pin 103 of the first single-phase power zone, and I2 is the phase current power output pin 103 of the second single-phase power zone.
[0034] In this embodiment, by setting the packaging structure of the power module, a power chip 102 is embedded in each single-phase power zone in a full-bridge manner, which greatly increases the output power of a single phase zone and provides a power module solution for three-phase motor drive of more than 2kW. Each single-phase power zone integrates multiple power chips. By integrating two single-phase power zones, multiple power chips 102 are further rationally designed and directly packaged and integrated together, thereby realizing large-scale integration of power devices and improving the reliability and stability of the packaging structure of the power module. In addition, compared with traditional power devices, the assembly volume of the packaging structure of the power module is greatly reduced, the product process is simplified, and the shell material is saved. In this way, the packaging structure of the power module is highly integrated, the creepage gap is reduced, and it is more conducive to heat dissipation of the entire device. Compared with the single-tube power chip device arranged on the circuit board, the power module of this embodiment highly integrates multiple power chips 102, reduces the internal resistance of the multiple power chips 102 stacked, reduces the power consumption of the multiple chips 102 to the circuit, reduces the creepage distance, and avoids the increase in circuit power consumption caused by the large internal resistance of the multiple power chips 102 and the impact of the large creepage distance on the operation. To a certain extent, it solves the problems of single device failure caused by uneven power consumption and poor heat dissipation due to individual differences of single power chip devices (small electrical performance differences between single-tube power chips).
[0035] Next, combine Figure 1-2 The structure of the power module of this embodiment is described in detail:
[0036] The power substrate 101 of the present invention includes a front metal layer, a ceramic layer, and a back metal layer stacked in sequence. The power substrate 101 is used for soldering the power chip 102 and dissipating heat from the devices on the power substrate 101. The power chip 102 is electrically connected to the power substrate 101. The power substrate 101 can be a substrate with electrical transmission and insulation and heat dissipation capabilities. Examples include thin film ceramic substrates (TFC), thick film printed ceramic substrates (TPC), direct bonded copper ceramic substrates (DBC), active metal brazing ceramic substrates (AMB), direct plated copper ceramic substrates (DPC), laser activated metallization ceramic substrates (LAM), and aluminum substrates. The power substrate of the present invention is preferably a ceramic substrate with low cost, good performance, and simple manufacturing process, and is more preferably a DBC ceramic substrate.
[0037] like Figure 2 As shown, the first power chipset group of each single-phase power zone is located in the first area on the front metal layer, indicating that the first power chipset group of each single-phase power zone is located on the same side of the front metal layer. The second power chipset group of each single-phase power zone is located in the second area on the front metal layer, indicating that the second power chipset group of each single-phase power zone is located on the other side of the front metal layer. The first area and the second area are arranged correspondingly. For example, half of the area of the front metal layer is the first area, and the other half of the area is the second area. In this way, the power chips 102 and multiple pins of each front metal layer phase power zone and each front metal layer phase power zone are reasonably and concisely distributed, which facilitates device wiring, simplifies the structure of the power module, reduces the cost of the power module, and reduces the assembly volume of the power module.
[0038] like Figure 3 As shown, in the first power chipset of each single-phase power zone, the gate of each power chip 102 of the first power chipset is commonly connected to the first gate pin 104. The source of each power chip 102 of the first power chipset is commonly connected to the first source pin 106 and the phase current power output pin 103, and the drain of each power chip 102 of the first power chipset is commonly connected. For example, Figure 3In the first power chipset of the first single-phase power zone, the gate of each power chip 102 of the first power chipset is commonly connected to the first gate pin 104 (i.e., G1) of the first single-phase power zone. The source of each power chip 102 of the first power chipset is commonly connected to the first source pin 106 (i.e., S1) of the first single-phase power zone and the phase current power output pin 103 (i.e., I1) of the first single-phase power zone. The drain of each power chip 102 of the first power chipset is commonly connected to the positive zone pin 108 (i.e., VDD) of the positive zone. The connection relationship of the first power chipset of the second single-phase power zone is similar.
[0039] like Figure 3 As shown, in the second power chipset of each single-phase power zone, the gate of each power chip 102 of the second power chipset is connected to the second gate pin 105. The source of each power chip 102 of the second power chipset is connected to the source of a power chip 102 of the first power chipset. Figure 3 In the second power chipset of the first single-phase power zone, the gate of each power chip 102 of the second power chipset is commonly connected to the second gate pin 105 (i.e., G3) of the first single-phase power zone. The source of each power chip 102 of the second power chipset is commonly connected to the second source pin 107 (i.e., S3) of the first single-phase power zone and also commonly connected to the negative region pin 109 (i.e., VSS) of the negative region. The drain of a power chip 102 of the second power chipset is connected to the source of a power chip 102 of the first power chipset of the first single-phase power zone. The connection relationship of the second power chipset of the second single-phase power zone is similar.
[0040] The connection structure of the power chips 102 of the first power chipset and the second power chipset in each single-phase power zone is configured. In each single-phase power zone, the power chips 102 are embedded in a full-bridge manner, significantly increasing the output power of a single phase zone and providing a power module solution for three-phase motor drives exceeding 2 kW. This allows multiple power chips 102 to be rationally designed and directly packaged and integrated together, thereby achieving large-scale integration of power devices and improving the reliability and stability of the power module. This also allows for a reasonable and concise distribution of the power chips 102 and multiple pins in each single-phase power zone, facilitating device wiring, simplifying the power module structure, reducing the cost of the power module, and reducing the assembly volume of the power module.
[0041] The power module of this embodiment further includes: a negative region and at least one positive region, the positive region is provided with a positive region pin 108, the negative region is provided with a negative region pin 109, the drain of each power chip 102 of the first power chipset group of each single-phase power region is connected to the positive region pin 108, and the source of each power chip 102 of the second power chipset group of each single-phase power region is connected to the negative region pin 109. In the drawings of this embodiment, VDD represents the positive region pin 108 of the positive region, and VSS represents the negative region pin 109 of the negative region. Figure 2 In the front metal layer, the positive region connects to a phase power region, while the negative region can be a separate area, achieving electrical connection between each region. This rational and concise arrangement of the positive region, positive region pin 108, and the negative region, negative region pin 109 facilitates device wiring, simplifies the power module structure, reduces the cost of the power module, and reduces the assembly volume of the power module.
[0042] The power module of this embodiment further includes: at least one thermistor 110 and a temperature sampling pin 111 of each thermistor 110. The thermistor 110 is provided in the first power chipset and / or the second power chipset in the single-phase power region. In the drawings of this embodiment, T1 and T2 represent two temperature sampling pins 111 of the thermistor 110. Figure 2-3 As shown, the thermistor 110 is set next to S2. The thermistor 110 is used to detect the temperature of the power module, which can achieve more efficient control of the power module. Figure 2-3 The thermistor 110 arrangement shown can more efficiently, quickly and conveniently detect the temperature in the area corresponding to the first power chipset in each single-phase power zone and the temperature in the area corresponding to the second power chipset in each single-phase power zone.
[0043] The power module of this embodiment further includes: a current sensing resistor 112 and a current sampling pin 113 of the current sensing resistor 112, and the current sensing resistor 112 is arranged in the negative electrode area. Figure 2-3 As shown, R1 and R2 represent two current sampling pins 113 of the current sensing resistor 112. By setting the current sensing resistor 112, the current magnitude of the power module can be detected in real time, and the performance of the power module can be further judged by the current magnitude.
[0044] The power module of this embodiment further includes: a bubble point 114, which is arranged on the front metal layer and the back metal layer of the power substrate 101. The thickness of the bubble point 114 is smaller than the thickness of the front metal layer and smaller than the thickness of the back metal layer. Specifically, Figure 2As shown, the bubble point 114 is set in the power area of the front metal layer, such as each single-phase power area, the power area of thermistor 110, or the power area of the current sensing resistor 112. The bubble point 114 is set in the heat dissipation area of the back metal layer, such as the edge area of the back metal layer.
[0045] In this embodiment, the bubble points 114 are used to increase the adhesion and cohesion between the metal layer and the ceramic layer, thereby improving the adhesion. This can solve the problem of ceramic cracking of the power substrate 101 when the power pins on the power substrate 101 and the power chip 102 are ultrasonically bonded. The bubble points 114 are point-shaped, spherical, or other shapes, i.e., blind holes. The diameter of the bubble points 114 can be selected to be 0.2 to 0.8 mm. It should be noted that the bubble points 114 of this embodiment are only pinned on the metal layer of the power substrate 101 through a pinning process, and do not completely penetrate the metal layer.
[0046] The power module of this embodiment further includes stress relief holes, which are provided between the power chips 102. The stress relief holes are used to relieve or eliminate stress generated when the power chips 102 are soldered to the power region, preventing cracking of the power substrate 101. This further improves the reliability of the device manufacturing process, reduces the process damage rate, and increases the production yield of the power module product.
[0047] In the power module of this embodiment, the power chip 102 is a MOSFET chip or an IGBT chip and an FRD chip connected in parallel. In the drawings of this embodiment, the power chip 102 is shown as a MOSFET chip.
[0048] like Figure 4 As shown, Figure 4 The circuit connection relationship of each single-phase power zone is illustrated using N=4 power chips 102. Figure 4 , G1 is the first gate pin 104 of the first single-phase power zone, G2 is the first gate pin 104 of the second single-phase power zone. G3 is the second gate pin 105 of the first single-phase power zone, and G4 is the second gate pin 105 of the second single-phase power zone. S1 is the first source pin 106 of the first single-phase power zone, and S2 is the first source pin 106 of the second single-phase power zone. S3 is the second source pin 107 of the first single-phase power zone, and S4 is the second source pin 107 of the second single-phase power zone. I1 is the phase current power output pin 103 of the first single-phase power zone, and I2 is the phase current power output pin 103 of the second single-phase power zone.
[0049] exist Figure 4In the first power chipset of the first single-phase power zone, the gate of each power chip 102 of the first power chipset is commonly connected to the first gate pin 104 (i.e., G1) of the first single-phase power zone. The source of each power chip 102 of the first power chipset is commonly connected to the first source pin 106 (i.e., S1) of the first single-phase power zone and the phase current power output pin 103 (i.e., I1) of the first single-phase power zone. The drain of each power chip 102 of the first power chipset is commonly connected to the positive zone pin 108 (i.e., VDD) of the positive zone. The connection relationship of the first power chipset of the second single-phase power zone is similar.
[0050] exist Figure 4 In the second power chipset of the first single-phase power zone, the gate of each power chip 102 of the second power chipset is commonly connected to the second gate pin 105 (i.e., G3) of the first single-phase power zone. The source of each power chip 102 of the second power chipset is commonly connected to the second source pin 107 (i.e., S3) of the first single-phase power zone and also commonly connected to the negative region pin 109 (i.e., VSS) of the negative region. The drain of a power chip 102 of the second power chipset is connected to the source of a power chip 102 of the first power chipset of the first single-phase power zone. The connection relationship of the second power chipset of the second single-phase power zone is similar.
[0051] A current sensing resistor 112 and a current sampling pin 113 (ie, R1 and R2) of the current sensing resistor 112 are provided in the negative electrode region. Figure 4 As shown, a thermistor 110 and a temperature sampling pin 111 (ie, T1 and T2 ) of each thermistor 110 are provided beside the second power chipset of the second single-phase power zone.
[0052] In this embodiment, various power pins (such as the phase current power output pin 103, the first gate pin 104, the second gate pin 105, the first source pin 106, the second source pin 107 and the polar region pin), the temperature sampling pin 111 and the current sampling pin 113 can be Z-shaped, S-shaped, pin-shaped, etc. The power pins, temperature sampling pins 111 and current sampling pins 113 are all connected to the corresponding areas by ultrasonic bonding or welding sheet / solder welding. The power chip 102 is connected to the power pin or the copper layer where the power pin is located by bonding metal wires (optionally aluminum wires, copper wires) or bonding metal sheets (optionally copper sheets), and the power areas are connected by bonding metal wires (optionally aluminum wires, copper wires) or bonding metal sheets (optionally copper sheets).
[0053] like Figure 1As shown, housing 200 is made of an electrically insulating material such as silicone gel or epoxy resin. Specifically, the housing is made of at least one of silicone gel and epoxy resin, preferably silicone gel, to directly encapsulate power substrate 101. This eliminates the need for a packaging frame, reduces costs, and simplifies the power module structure, lowers costs, and reduces assembly volume. Housing 200 also protects power chip 102, isolating it from moisture and dust.
[0054] It should be understood by those skilled in the art that although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.
[0055] Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if such modifications and variations fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.
Claims
1. A power module, characterized in that: include: A power substrate and a housing connected to the power substrate; Two single-phase power areas are provided on the front metal layer of the power substrate; each of the single-phase power areas includes N power chips, and a phase current power output pin, a first gate pin, a second gate pin, a first source pin, and a second source pin connected to the N power chips, where N is a positive even number greater than 3; In each of the single-phase power zones, the N power chips include a first power chips group and a second power chips group, the number of power chips in the first power chips group and the second power chips group are both N / 2, the power chips of the first power chips group are connected one-to-one with the power chips of the second power chips group, the phase current power output pin, the first gate pin and the first source pin are all connected to the first power chips group, and the second gate pin and the second source pin are both connected to the second power chips group.
2. The power module according to claim 1, wherein: In the first power chipset of each of the single-phase power zones, the gate of each power chip of the first power chipset is commonly connected to the first gate pin; the source of each power chip of the first power chipset is commonly connected to the first source pin and the phase current power output pin, and the drain of each power chip of the first power chipset is commonly connected.
3. The power module according to claim 2, wherein: In the second power chipset of each of the single-phase power zones, the gate of each power chip of the second power chipset is commonly connected to the second gate pin, the source of each power chip of the second power chipset is commonly connected to the second source pin, and the drain of a power chip of the second power chipset is connected to the source of a power chip of the first power chipset of the single-phase power zone.
4. The power module according to claim 3, wherein: Also includes: A negative region and at least one positive region, the positive region is provided with a positive region pin, the negative region is provided with a negative region pin, the drain of each power chip of the first power chipset group of each single-phase power region is commonly connected to the positive region pin, and the source of each power chip of the second power chipset group of each single-phase power region is commonly connected to the negative region pin.
5. The power module according to claim 4, wherein: Also includes: At least one thermistor and a temperature sampling pin of each thermistor, wherein the thermistor is provided in the first power chipset and / or the second power chipset in the single-phase power region.
6. The power module according to claim 4, wherein: Also includes: A current sensing resistor and a current sampling pin of the current sensing resistor, wherein the current sensing resistor is arranged in the negative electrode area.
7. The power module according to claim 1, wherein: Also includes: The bubble point is arranged on the front metal layer and the back metal layer of the power substrate, and the thickness of the bubble point is less than the thickness of the front metal layer and less than the thickness of the back metal layer.
8. The power module according to claim 1, wherein: Also includes: A stress release hole is provided between the power chips.
9. The power module according to claim 1, wherein: The shell is made of at least one of silicone gel and epoxy resin.
10. The power module according to any one of claims 1 to 9, wherein: The power chip is a MOSFET chip or an IGBT chip and an FRD chip connected in parallel, and the power substrate is any one of a DBC ceramic substrate, a TFC ceramic substrate, a TPC ceramic substrate, an aluminum substrate, an AMB ceramic substrate, a DPC ceramic substrate and a LAM ceramic substrate.