Area array VCSEL with high heat dissipation efficiency

Abstract

The utility model relates to the technical field of semiconductor lasers, in particular to an area array VCSEL (Vertical Cavity Surface Emitting Laser) with high heat dissipation efficiency, which comprises a light-emitting unit array which is periodically arranged, and a deeper etching gully exists between adjacent light-emitting units. Each light-emitting unit is provided with a substrate, a DBR (Distributed Bragg Reflector) structure, an active layer, a current limiting layer, an electrode and an insulating layer arranged on the side surface and a communication region of each light-emitting unit, graphene is plated on all regions of the insulating layer, or graphene is only plated on a heat distribution region according to a thermal simulation result to form a patterned graphene heat dissipation layer. According to the utility model, the local heat dissipation problem of the area array VCSEL can be effectively optimized, the temperature difference between different light-emitting units is balanced, and the situation that the performance of a device is reduced due to serious local heating of a chip is avoided.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor lasers, and specifically provides a planar array VCSEL with high heat dissipation efficiency. Background Art

[0002] The vertical-cavity surface-emitting semiconductor laser (VCSEL) was first proposed by Professor Iga of the Tokyo Institute of Technology in Japan in 1977. Unlike traditional edge-emitting semiconductor lasers, the VCSEL's epitaxial structure primarily consists of top and bottom multilayer Bragg reflectors (DBRs), a conductive confinement region, an active region, and a semiconductor substrate. Feedback from the upper and lower DBRs allows the laser beam within the cavity to be emitted perpendicular to the substrate. VCSELs offer numerous advantages, including low threshold current, a circular beam spot, wide modulation bandwidth, single-longitudinal-mode lasing, ease of fabrication for high-density two-dimensional arrays, and low manufacturing costs. Over the past three decades, VCSELs have become the primary light source for high-speed data communications and sensing applications due to their compact structure, fast response speed, and high energy conversion efficiency. Driven in particular by applications such as facial recognition (Face ID), infrared illumination, time-of-flight (ToF) proximity sensing, and 3D sensing in devices like smartphones, tablets, and robots, the production of VCSEL chips and modules has reached an unprecedented level of billions. As detection range increases, point cloud density decreases, limiting resolution. To reconstruct long-range 3D scans, high-quality laser beams with higher power density and lower divergence angles are required. LiDAR and 3D sensing are expanding into new applications in the consumer electronics, automotive, and industrial markets. These new applications and capabilities demand smaller devices, higher power, and higher efficiency. Compared to existing devices, single- and multi-junction VCSEL arrays offer lower power consumption, higher slope efficiency, and higher peak optical power. The peak optical power, low thermal dissipation, and small size of these new multi-single- and multi-junction VCSEL arrays are crucial for expanding their application in high-performance, all-solid-state mid- and long-range LiDARs. Because the DBR portion of a VCSEL is formed by alternating dozens of cycles of two materials with a large energy band gap, the VCSEL structure inherently exhibits high series resistance (approximately 80-100Ω), resulting in significant chip heating and reduced device performance. Especially for large-area VCSEL arrays, thermal crosstalk between the individual light-emitting points leads to high center temperatures, hindering effective heat dissipation. First, the large temperature difference between the center and the outer ring leads to different optoelectronic performance in different areas of the chip, making the output light intensity of the array chip uneven, affecting the chip performance of the entire VCSEL array. Secondly, the high center temperature leads to concentrated heat and ineffective heat dissipation, making the center of the array VCSEL chip prone to burning, leading to premature chip failure. Currently, the main way to improve the heat dissipation of single / multi-junction VCSEL chips in area arrays is to electroplate a thicker metal layer on the surface, and use the higher thermal conductivity of the metal to improve the heat dissipation efficiency on both sides of the center temperature area. The metals with high thermal conductivity in the electroplating process are mainly high-priced metals such as gold, silver, and copper. In order to improve the lateral heat dissipation efficiency, the thickness of the electroplated metal layer is generally increased.However, an excessively thick metal layer can introduce significant stress to the chip surface, leading to risks such as splitting and shedding between film layers. Furthermore, the cumulative stress mismatch caused by an excessively thick film layer can negatively impact the long-term use of the chip, potentially leading to premature chip failure. Furthermore, an excessively thick film layer significantly increases plating solution consumption, increasing chip processing costs. Utility Model Content

[0003] To solve the above problems, the present invention provides a planar array VCSEL with high heat dissipation efficiency. By growing graphene material with high lateral thermal conductivity on the surface of the array VCSEL chip, the heat dissipation efficiency of the array VCSEL chip is improved, the junction temperature of the central area of each light-emitting unit is reduced, and the electro-optical conversion efficiency of the VCSEL chip is improved.

[0004] The utility model provides a high heat dissipation efficiency area array VCSEL, comprising:

[0005] Substrate and first DBR provided on the substrate

[0006] The first DBR is provided with a plurality of light-emitting units, the light-emitting units including:

[0007] An active layer, which is used to provide laser gain, with spacer layers provided above and below the active layer;

[0008] a current limiting layer, which is provided in the active layer and is used to limit the current path;

[0009] a second DBR, which is provided on an upper surface of the current confinement layer above the active layer, wherein the light reflectivity of the second DBR is lower than the light reflectivity of the first DBR;

[0010] A first electrode and a second electrode are respectively provided on the lower surface of the substrate and the upper surface of the second DBR;

[0011] An insulating layer is provided on the side surface of the light-emitting unit and the bottom communicating plane of the adjacent light-emitting units, and a graphene heat dissipation layer is provided on the insulating layer.

[0012] Preferably, the substrate comprises at least one material selected from the group consisting of GaAs, InP, and GaSb.

[0013] Preferably, the first DBR is a multi-period N-type DBR structure in which high and low refractive index semiconductor materials are alternately grown, and the second DBR is a multi-period P-type DBR structure in which high and low refractive index semiconductor materials are alternately grown.

[0014] Preferably, the active layer is a multi-quantum well structure.

[0015] Preferably, the band gap of the spacer layer is larger than the quantum well band gap of the active layer.

[0016] Preferably, the first electrode is an N-type contact electrode, the second electrode is a P-type contact electrode, and a P-type doped ohmic contact layer is provided between the second DBR and the first electrode.

[0017] Preferably, the heat distribution area of the insulating layer of all the light-emitting units is obtained based on thermal simulation, and the graphene heat dissipation layer covers the heat distribution area to obtain a patterned graphene heat dissipation layer.

[0018] Compared with the prior art, the present invention can achieve the following beneficial effects:

[0019] On the one hand, the present invention improves the heat dissipation performance of the array VCSEL chip and reduces the junction temperature in the center area of the array by growing graphene material with high lateral thermal conductivity on the surface of the area array VCSEL chip, thereby improving the electro-optical conversion efficiency of the chip. Compared with the existing electroplated metal layer method, the graphene heat dissipation layer adopted by the present invention has higher lateral thermal conductivity. The lateral thermal conductivity of graphene is more than 10 times that of metal. Therefore, the required thickness of the graphene heat dissipation layer is also much smaller than the electroplated metal layer. Reducing the thickness of the film on the surface of the area array VCSEL chip can avoid the problem of excessive stress and stress mismatch on the chip surface caused by excessive film thickness. Reducing the film thickness also reduces the preparation cost of the area array VCSEL chip.

[0020] On the other hand, the graphene on the surface of the area array VCSEL chip of the present invention can be patterned, and the graphene heat dissipation layer can be designed according to the single-tube layout and heat distribution of the array chip, which can improve the local heat dissipation problem, reduce the temperature difference between the light-emitting units in the array, ensure the uniform heat distribution of the light-emitting units in the VCSEL chip, and thus improve the uniformity of the light intensity distribution of the output light array; the high heat dissipation efficiency area array VCSEL of the present invention is suitable for the needs of single / multi-junction high-power VCSEL chips in scenarios such as laser radar and 3D sensing. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a structural diagram of a planar array VCSEL with high heat dissipation efficiency provided in Example 1 of the present utility model;

[0022] Figure 2 This is a structural diagram of a planar array VCSEL with high heat dissipation efficiency using a patterned graphene heat dissipation layer provided in Example 2 of the present invention.

[0023] Reference numerals include:

[0024] Substrate 100 , N-type DBR 101 , spacer layer 102 , active layer 103 , current limiting layer 104 , P-type DBR 105 , ohmic contact layer 106 , insulating layer 107 , P-type contact electrode 108 , N-type contact electrode 109 , graphene heat dissipation layer 110 . DETAILED DESCRIPTION

[0025] Hereinafter, the embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same modules are represented by the same reference numerals. In the case of the same reference numerals, their names and functions are also the same. Therefore, their detailed description will not be repeated.

[0026] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and do not constitute a limitation of the present invention.

[0027] Since the multiple light-emitting units of the area array VCSEL are circular table-shaped structures formed by etching, there are deep etched grooves between adjacent light-emitting units. In order to meet the high power density requirements of area array VCSELs in application scenarios such as lidar and 3D sensing, it is necessary to increase the power density by reducing the etching spacing between the light-emitting units. This makes it difficult for heat on the surface of the light-emitting units in the etched grooves to be conducted laterally, exacerbating heat accumulation in the center area of the area array VCSEL, reducing chip performance, and even causing the area array VCSEL to burn out.

[0028] To improve the heat dissipation efficiency of area array VCSEL, please refer to Figure 1 In Example 1 of the present invention, a high-heat-dissipating-efficiency area array VCSEL based on graphene material is provided, which mainly includes a common substrate of the area array VCSEL and a plurality of periodically arranged light-emitting units thereon. In Example 1 of the present invention, the common substrate mainly includes a substrate 100 and an N-type DBR 101 grown on the upper surface of the substrate 100. The substrate 100 can be made of a III-V semiconductor material such as GaAs, InP, or GaSb. The substrate 100 can be made of a single material or a mixture of multiple materials. The wavelength bands that the substrate 100 can cover include visible light, near infrared, mid-infrared, etc. A multi-period N-type DBR 101 composed of two semiconductor materials with different refractive indices grown alternately is provided on the upper surface of the substrate 100. A high refractive index material and a low refractive index material are alternately grown once for one period. The thickness of the high refractive index material layer and the low refractive index material layer are both one-quarter of the optical thickness of the corresponding material. The N-type DBR 101 usually has 35 to 40 periods to ensure that the light reflectivity of the N-type DBR 101 can meet the design requirements. Under normal circumstances, it is believed that the reflectivity of the N-type DBR 101 should be greater than 99.9%.

[0029] The light-emitting units on the common substrate all have the same structure, and only differ in their spatial arrangement positions. Therefore, only the structure of any one of the light-emitting units will be described in detail.

[0030] Specifically, the light-emitting unit mainly includes: a spacer layer 102, an active layer 103, a current limiting layer 104 and a P-type DBR 105, wherein the active layer 103 is a key part for achieving high-efficiency electro-optical conversion, which is used to provide the laser gain required for laser emission. In an embodiment of the present utility model, the active layer 103 is preferably designed as a multi-quantum well structure. In the quantum well, electrons and holes are confined in a very small space, resulting in a quantum size effect, so that the energy levels of electrons and holes are quantized to form discrete energy levels. These quantized energy levels help to improve the optical gain of the laser, and photons can be generated more efficiently when electrons and holes recombine.

[0031] A lattice-matched spacer layer 102 is provided on both the upper and lower sides of the active layer 103. Specifically, the spacer layer 102 below the active layer 103 is grown on the upper surface of the N-type DBR 101, and the spacer layer 102 above the active layer 103 is grown on the upper surface of the active layer 103. The lattice-matched spacer layer 102 can reduce stress and maintain the stability of the crystal structure. In addition, the design purpose of the spacer layer 102 is mainly to adjust the cavity length of the VCSEL laser to ensure that the laser wavelength meets the design requirements. It is understandable that the laser cavity length can be adjusted by changing the thickness of the spacer layer 102 on both sides of the active layer 103, thereby achieving the designed laser wavelength. In addition, the band gap of the spacer layer 102 must be larger than the band gap of the quantum well in the active layer 103, so that the carrier confinement effect can be achieved, thereby improving the performance of the laser.

[0032] Furthermore, a ring-shaped current limiting layer 104 is provided in the spacer layer 102 above the active layer 103. The current limiting layer 104 is prepared by lateral oxidation of the spacer layer 102. Different lateral oxidation depths are achieved by changing the oxidation conditions, and finally a current limiting layer 104 with different ring widths is obtained. The inner ring center area of the current limiting layer 104 is an unoxidized hole area, and the oxidized part forms a high resistance area. The current injected into the laser will be limited to pass only through the central unoxidized hole area, so as to limit the injected current path and improve the carrier density of the active area 103.

[0033] A multi-period P-type DBR105 is grown on the upper surface of the spacer layer 102 above the active layer 103. The P-type DBR105 is also composed of two semiconductor materials with different refractive indices grown alternately. One period is the alternating growth of a high refractive index material and a low refractive index material. The thickness of the high refractive index material layer and the low refractive index material layer are both one-quarter of the optical thickness of the corresponding material. Since the planar array VCSEL involved in the embodiment of the present invention is a top-emitting structure, the reflectivity of the P-type DBR105 should be designed to be less than the reflectivity of the N-type DBR101. It can be understood that it can ensure that the laser is emitted from the P-type DBR105.

[0034] N-type contact electrodes 109 and P-type contact electrodes 108 are provided on the lower surface of substrate 100 and the upper surface of P-type DBR 105, respectively, corresponding to the positive and negative electrodes of the area array VCSEL. These electrodes drive the laser. Furthermore, to reduce the Schottky barrier at the metal-semiconductor interface, an embodiment of the present invention also grows a ring-shaped ohmic contact layer 106 on P-type DBR 105 and P-type contact electrode 108. This layer is made of a highly doped P-type semiconductor material, forming an ohmic contact between P-type DBR 105 and P-type contact electrode 108. This reduces the voltage drop at the contact interface, thereby reducing laser power loss.

[0035] Furthermore, the side surface of the light-emitting unit is cylindrical. An insulating layer 107 is provided on this cylindrical surface and on the connecting plane at the bottom of different light-emitting units on the upper surface of the N-type DBR 101. It is understood that, on the upper surface of the area array VCSEL, except for the P-type contact electrode 108 and the light outlet area, all other areas are provided with the insulating layer 107. The function of the insulating layer 107 is to prevent accidental current leakage between different light-emitting units, ensuring that each light-emitting unit can operate independently. The spatial area between adjacent light-emitting units is the etched grooves that remain after processing. As the power density of the area array VCSEL increases, the etched grooves between adjacent light-emitting units continue to shrink. This prevents the heat generated by the light-emitting units from being effectively conducted laterally, increasing the heat dissipation pressure of the area array VCSEL. In an embodiment of the present invention, a graphene heat sink layer 110 is integrated onto the insulating layer 107. Compared to metal thermal conductive layers, graphene has superior heat dissipation performance, with a lateral heat dissipation efficiency at least ten times greater than that of metal thermal conductive layers. This prevents excessively thick heat sink layers from being plated on the sidewalls of the light-emitting units, which can lead to unbalanced extrusion stress on the sidewalls. Excessive internal stress in the chip can reduce the chip's lifespan and reliability. According to tests, when the graphene heat sink layer 110 is 500nm thick, its heat dissipation capacity exceeds that of a traditional 5-8μm electroplated metal layer. Based on the design requirements for chip heat dissipation efficiency, the thickness of the graphene heat sink layer 110 can be further increased. In terms of process feasibility, and considering the mesa depth of a single diode in the array chip, a graphene heat sink layer 110 thickness of less than 5μm is well compatible with existing VCSEL array chip structures.

[0036] See also Figure 2 In Example 2 of the present invention, a planar VCSEL with a patterned heat dissipation layer and high heat dissipation efficiency is provided, which differs from Example 1 only in that:

[0037] The graphene heat dissipation layer 110 integrated on the insulating layer 107 is a patterned design. First, a thermal simulation is performed on the array VCSEL to obtain the distribution of heat dissipation on the insulating layer 107 of all light-emitting units, and the areas that need auxiliary heat dissipation are divided. Then, according to different array shapes, heat dissipation is only performed on specific areas. That is, according to the simulation results, graphene is only covered in the areas with severe heat generation to form a patterned graphene heat dissipation layer 110. Figure 2 The two VCSEL arrays with different geometries shown in the figure first grow graphene on an insulating layer 107. The graphene growth areas are then customized based on thermal distribution. A lift-off technique is then used to remove the non-patterned areas, removing the graphene from areas where auxiliary heat dissipation is not required. The patterned graphene heat dissipation layer 110 can specifically improve the local heat dissipation of the array VCSELs, reducing temperature differences between the light-emitting units in the array and achieving more uniform thermal distribution and light intensity across the chip.

[0038] Based on the above structural description, in the embodiment of the present invention, a high heat dissipation efficiency area array VCSEL with a wavelength of 850nm is taken as an example to illustrate its preparation process, which specifically includes the following steps:

[0039] S1: The substrate 100 is made of N-type GaAs material, and Al (aluminum) with different Al (aluminum) components are alternately grown on the N-type GaAs substrate 100 using organic metal chemical vapor deposition technology (MOCVD). x Ga 1-x As (aluminum gallium arsenide) semiconductor material. In this process, the high Al component x is usually between 0.9 and 1, while the low Al component x is between 0.1 and 0. The typical number of DBR growth cycles is about 35 to 40 cycles. In this way, a high-reflectivity N-type DBR 101 (distributed Bragg reflector) can be prepared on an N-type GaAs substrate 100. The reflectivity of the final prepared N-type DBR 101 is required to be greater than 99.9%.

[0040] S2: epitaxially growing a spacer layer 102 of a certain thickness on the upper surface of the N-type DBR 101. The material of the spacer layer 102 is lattice-matched to the GaAs substrate 100.

[0041] S3: Continue epitaxially growing the active layer 103 of the multi-quantum well structure on the upper surface of the spacer layer 102. The typical quantum well structure with a wavelength of 850nm is GaAs / Al x Ga 1-x As, where the value of x is between 0.2 and 0.4, by adjusting the thickness of the quantum well or the Al composition of the barrier, the light emitting band of the active layer 103 can be adjusted to cover 850 nm.

[0042] S4: Continue to epitaxially grow the remaining thickness of the spacer layer 102 on the upper surface of the active layer 103 until a specific thickness is reached, that is, the overall optical thickness of the two parts of the spacer layer 102 (including the thickness of the current limiting layer 104 to be prepared later) and the active layer 103 is designed to be half the wavelength of an integer multiple of 850nm, so as to meet the standing wave condition of the laser. This design ensures that the laser can achieve efficient laser emission at a specific wavelength.

[0043] S5: Continue to grow P-type DBR 105 on the spacer layer 102 above the active layer 103. The P-type DBR 105 is composed of Al with high and low Al components. x Ga 1-x The thickness of each layer of As semiconductor material is alternately grown according to the optical thickness of one-quarter of the material. The typical high Al composition x=0.9~1, the low Al composition x=0.1~0, the typical number of cycles is about 20~25 cycles, and the reflectivity of P-type DBR105 is lower than that of N-type DBR101, so that light is emitted from the top.

[0044] S6: An ohmic contact layer 106 of a P-type highly doped GaAs material is grown on the upper surface of the P-type DBR 105. The design of the ohmic contact layer 106 can reduce the Schottky barrier generated by the contact between the metal electrode and the semiconductor material, thereby reducing resistance.

[0045] S7: After completing S1 to S6, the epitaxial growth process of the high-heat dissipation-efficiency area array VCSEL has been completed. The etching preparation process of the light-emitting unit is further carried out. First, the sample obtained in S6 is coated with a resin, photolithography, and development is performed to form the mask pattern of the area array VCSEL. Then, an ICP etching device is used to dry-etch the VCSEL mesa until the upper surface of the N-type DBR 101 is exposed. During the etching process, a mixture of Cl2 / BCl3 / Ar gas can be used as the etching gas for GaAs. These gases can effectively remove the GaAs material while maintaining the flatness of the sidewalls.

[0046] S8: Use wet nitrogen oxidation equipment to perform lateral oxidation on the position of the preset current limiting layer 104 on the spacer layer 102, control the oxidation rate by adjusting parameters such as oxidation temperature, water vapor temperature, pressure, flow rate, and control the lateral oxidation depth by controlling time, and finally form a central unoxidized hole area in the spacer layer 102 above the active layer 103, and the oxidized part forms a high resistance area, namely the current limiting layer 104, and the current injected into the laser will be limited to pass only through the central hole area.

[0047] S9: After the current limiting layer 104 is prepared, an insulating material is deposited on the surface of the sample using PECVD equipment. Typical insulating materials are SiO2 or Si3N4.

[0048] S10: The sample is photolithographically processed again, and after the steps of coating, photolithography, and development, the active layer 103 that needs to be exposed on the side of the light-emitting unit and the spacer layer 102 under the active layer 103 are determined, and dry etching is performed using RIE equipment until the etching reaches the set depth, that is, an insulating layer 107 is formed on the side of the light-emitting unit and the bottom connecting plane of the adjacent light-emitting units. The typical SiO2 or Si3N4 etching gas used for etching can be CF4 / O2.

[0049] S11: The sample undergoes a third photolithography process. After the coating, photolithography, and development steps, the ohmic contact layer 106 and the P-type contact electrode 108 are deposited using electron beam evaporation or magnetron sputtering. The P-type contact electrode 108 is the positive electrode of the area array VCSEL and is typically made of Ti / Pt / Au. After the deposition is complete, the sample undergoes a lift-off process in an acetone solution to remove the unnecessary portion of the preset light output port above the P-type DBR 105, ultimately forming the P-type contact electrode 108.

[0050] S12: The sample undergoes a fourth photolithography process. After the steps of coating, photolithography, and development, the area where graphene is to be grown is determined. A graphene heat dissipation layer 110 is grown on the sample surface using a CVD device. The typical growth temperature of graphene can be controlled between 50°C and 300°C. If the patterned graphene heat dissipation layer 110 is to be formed only in the designated area, the sample after graphene growth needs to undergo another stripping process to obtain the desired patterned graphene heat dissipation layer 110.

[0051] S13: The bottom of the sample substrate 100 is thinned and polished, and then a negative electrode is deposited using electron beam evaporation or magnetron sputtering. Specifically, an N-type DBR 101 is deposited on the bottom of the substrate 100. Typical negative electrode materials are Au-Ge / Ni / Au. This completes the high-heat dissipation efficiency area array VCSEL provided by this embodiment of the utility model.

[0052] Although the embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and cannot be understood as limiting the present invention. Those skilled in the art may make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

[0053] The above specific embodiments of the present invention do not constitute a limitation on the scope of protection of the present invention. Any other corresponding changes and modifications made based on the technical concept of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A planar VCSEL with high heat dissipation efficiency, comprising a substrate and a first DBR disposed on the substrate, characterized in that: The first DBR is provided with a plurality of light-emitting units, and the light-emitting units include: An active layer for providing laser gain, wherein spacer layers are provided above and below the active layer; a current limiting layer, disposed in the active layer and configured to limit a current path; a second DBR, which is provided on an upper surface of the current confinement layer above the active layer, wherein the light reflectivity of the second DBR is lower than the light reflectivity of the first DBR; A first electrode and a second electrode are respectively provided on the lower surface of the substrate and the upper surface of the second DBR; An insulating layer is provided on the side surface of the light-emitting unit and the bottom communicating plane of the adjacent light-emitting units, and a graphene heat dissipation layer is provided on the insulating layer.

2. The high heat dissipation efficiency area array VCSEL according to claim 1, characterized in that: The substrate includes at least one material selected from GaAs, InP, and GaSb.

3. The high heat dissipation efficiency area array VCSEL according to claim 1, characterized in that: The first DBR is a multi-period N-type DBR structure in which high and low refractive index semiconductor materials are alternately grown, and the second DBR is a multi-period P-type DBR structure in which high and low refractive index semiconductor materials are alternately grown.

4. The high heat dissipation efficiency area array VCSEL according to claim 1, characterized in that: The active layer is a multi-quantum well structure.

5. The high heat dissipation efficiency area array VCSEL according to claim 4, characterized in that: The band gap of the spacer layer is larger than the quantum well band gap of the active layer.

6. The high heat dissipation efficiency area array VCSEL according to claim 1, characterized in that: The first electrode is an N-type contact electrode, the second electrode is a P-type contact electrode, and a P-type doped ohmic contact layer is provided between the second DBR and the first electrode.

7. The high heat dissipation efficiency area array VCSEL according to claim 1, characterized in that: The heat distribution area of the insulating layer of all the light-emitting units is obtained based on thermal simulation, and the graphene heat dissipation layer covers the heat distribution area to obtain the patterned graphene heat dissipation layer.

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