Motor control equipment

Abstract

The utility model discloses motor control equipment which comprises a logic wave sealing circuit, a processor, a chip monitoring circuit, an overcurrent monitoring circuit, an overvoltage monitoring circuit and a driving circuit. The pulse signal output end of the processor is connected with the logic wave sealing circuit; the processor outputs a pulse signal to the logic wave sealing circuit; an active short circuit ASC command port of the processor is connected with a command input port of the logic wave sealing circuit; the chip monitoring circuit is connected with the processor, and sends a fault signal to a chip monitoring port of the logic wave sealing circuit when the processor is monitored to have a fault; the output ends of the over-current monitoring circuit and the over-voltage monitoring circuit are connected with an electrical parameter monitoring port of the logic wave sealing circuit; the output end of the logic wave sealing circuit is connected with a switching tube of the driving circuit, and the signal detection end of the driving circuit is connected with the driving chip detection input end of the logic wave sealing circuit; the logic wave sealing circuit outputs a pulse signal or blocks the pulse signal to the driving circuit, the hardware of the scheme responds, the speed is increased, and the safety is ensured.

Description

Technical Field

[0001] The present application relates to the field of motor control technology, and in particular to a motor control device. Background Art

[0002] New energy vehicles are driven by electric motors. The operation of the motor is controlled by a motor control device, commonly known as a motor controller. The motor control device includes a processor and a drive circuit. Specifically, the processor controls the switching transistors in the drive circuit, which converts the energy of the power battery into AC power to drive the motor. The actual operating conditions of the motor control device are relatively complex. For example, various fault signals are sent to the processor. The processor outputs a PWM signal based on the fault type, entering an active short circuit (ASC), controlled, or wave-blocking state (all six power transistors in the upper and lower arms are shut down). There is a response delay problem, and it is impossible to quickly enter a safe state (ASC or wave-blocking). When the processor fails or the software runs incorrectly, it is not feasible to enter a safe state through software control, and therefore the safe operation of the motor control device cannot be guaranteed. Utility Model Content

[0003] In view of this, the present application provides a motor control device that can respond through a hardware circuit when a fault occurs, thereby improving the response speed and ensuring the safety of the motor control device.

[0004] The present application provides a motor control device, comprising: a logic envelope circuit, a processor, a chip monitoring circuit, an overcurrent monitoring circuit, an overvoltage monitoring circuit and a drive circuit; the pulse signal output end of the processor is connected to the logic envelope circuit; the processor is used to output a pulse signal to the logic envelope circuit; the active short circuit ASC command port of the processor is connected to the command input port of the logic envelope circuit; the chip monitoring circuit is connected to the processor, and the chip monitoring circuit is used to monitor the processor and send a fault signal to the chip monitoring port of the logic envelope circuit when a fault occurs; the output end of the overcurrent monitoring circuit and the output end of the overvoltage monitoring circuit are both connected to the electrical parameter monitoring port of the logic envelope circuit; the output end of the logic envelope circuit is connected to the switch tube in the drive circuit, and the signal detection end of the drive circuit is connected to the drive chip detection input end of the logic envelope circuit; the logic envelope circuit is used to output the pulse signal to the drive circuit, or block the pulse signal to the drive circuit.

[0005] In one possible implementation, the logic encapsulation circuit includes: a shutdown logic circuit, an active short-circuit ASC logic circuit, a shutdown path circuit and an active short-circuit ASC path circuit; the input end of the shutdown logic circuit is connected to the chip monitoring circuit, the output end of the overcurrent monitoring circuit, the output end of the overvoltage monitoring circuit, the active short-circuit ASC command port of the processor and the signal detection end of the drive circuit; the input end of the active short-circuit ASC logic circuit is connected to the output end of the overvoltage monitoring circuit and the signal detection end of the drive circuit; the first input end of the shutdown path circuit is connected to the output end of the shutdown logic circuit, and the second input end of the shutdown path circuit is connected to the pulse signal output end of the processor; the first input end of the active short-circuit ASC path circuit is connected to the output end of the active short-circuit ASC logic circuit, and the second input end of the active short-circuit ASC path circuit is connected to the output end of the shutdown path circuit.

[0006] In one possible implementation, the shutdown logic circuit is used to output a shutdown signal to the first input end of the shutdown path circuit based on the fault signal of the chip monitoring circuit, the signal at the output end of the overcurrent monitoring circuit, the signal at the output end of the overvoltage monitoring circuit, the signal at the active short-circuit ASC command port of the processor, and the signal at the signal detection end of the drive circuit; the active short-circuit ASC logic circuit is used to output a short-circuit signal to the first input end of the active short-circuit ASC path circuit based on the signal at the output end of the overvoltage monitoring circuit and the signal at the signal detection end of the drive circuit.

[0007] In one possible implementation, the shutdown path circuit includes: an upper bridge shutdown path circuit and a lower bridge shutdown path circuit; the first input end of the upper bridge shutdown path circuit is connected to the upper bridge output end of the shutdown logic circuit, and the second input end of the upper bridge shutdown path circuit is connected to the upper bridge pulse signal output end of the processor; the first input end of the lower bridge shutdown path circuit is connected to the lower bridge output end of the shutdown logic circuit, and the second input end of the lower bridge shutdown path circuit is connected to the lower bridge pulse signal output end of the processor.

[0008] In one possible implementation, the active short-circuit ASC path circuit includes: an upper bridge active short-circuit ASC path circuit and a lower bridge active short-circuit ASC path circuit; the first input end of the upper bridge active short-circuit ASC path circuit is connected to the upper bridge output end of the active short-circuit ASC logic circuit, and the second input end of the upper bridge active short-circuit ASC path circuit is connected to the upper bridge output end of the shutdown path circuit; the first input end of the lower bridge active short-circuit ASC path circuit is connected to the lower bridge output end of the active short-circuit ASC logic circuit, and the second input end of the lower bridge active short-circuit ASC path circuit is connected to the lower bridge output end of the shutdown path circuit.

[0009] In a possible implementation, the shutdown logic circuit is configured to control the shutdown path circuit to block the pulse signal when the signal detection terminal of the driving circuit outputs a low level.

[0010] In one possible implementation, the active short-circuit ASC logic circuit is used to control the lower bridge active short-circuit ASC path circuit of the active short-circuit ASC path circuit to actively short-circuit when the signal detection end of the driving circuit outputs a high level and the output end of the overvoltage detection circuit outputs a low level.

[0011] In one possible implementation, the shutdown logic circuit is used to control the shutdown path circuit to block the pulse signal when the signal detection end of the driving circuit outputs a high level and the output end of the overcurrent detection circuit outputs a low level.

[0012] In one possible implementation, the active short-circuit ASC logic circuit is used to output a high level at the signal detection end of the drive circuit, the output end of the overvoltage detection circuit outputs a high level, the output end of the overcurrent detection circuit outputs a high level, the chip monitoring circuit outputs a high level, and when the active short-circuit ASC command port of the processor outputs a low level of the upper bridge active short-circuit ASC command, control the upper bridge active short-circuit ASC path circuit to short-circuit the upper bridge arm switch tube of the drive circuit; the active short-circuit ASC logic circuit is used to output a high level at the signal detection end of the drive circuit, the output end of the overvoltage detection circuit outputs a high level, the output end of the overcurrent detection circuit outputs a high level, the chip monitoring circuit outputs a high level, and when the active short-circuit ASC command port of the processor outputs a low level of the lower bridge active short-circuit ASC command, control the lower bridge active short-circuit ASC path circuit to short-circuit the lower bridge arm switch tube of the drive circuit.

[0013] In one possible implementation, the logic encapsulation circuit is also connected to the software enable terminal of the processor; when the software enable terminal outputs a high level, the logic encapsulation circuit is enabled to actively short-circuit; when the software enable terminal outputs a low level, the logic encapsulation circuit is enabled to encapsulate.

[0014] The motor control device provided in the embodiment of the present application includes a logic wave blocking circuit, which includes various logic gates and can perform logical operations on the signals of various monitoring circuits. When a fault occurs, the wave blocking can be achieved in time, that is, the pulse signal output by the processor is blocked, and the pulse signal cannot drive the switch tube to operate, thereby ensuring the safety of the driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of a motor control device provided in an embodiment of the present application;

[0016] Figure 2 A schematic diagram of another motor control device provided in an embodiment of the present application;

[0017] Figure 3 A schematic diagram of another motor control device provided in an embodiment of the present application;

[0018] Figure 4 A schematic diagram of another motor control device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0020] See also Figure 1 , which is a schematic diagram of a motor control device provided in an embodiment of the present application.

[0021] The motor control device provided in the embodiment of the present application includes: a logic envelope circuit 100, a processor 200, a chip monitoring circuit 300, a driving circuit 400, an overcurrent monitoring circuit 500 and an overvoltage monitoring circuit 600.

[0022] The embodiment of the present application does not specifically limit the implementation method of the processor 200, for example, it can be a single-chip microcomputer or a microprocessor.

[0023] The pulse signal output terminal of processor 200 is connected to logic envelop circuit 100. Processor 200 is used to output pulse signals to logic envelop circuit 100. The active short circuit (ASC) command port of processor 200 is connected to the command input port of logic envelop circuit 100. ASC is the abbreviation for active short circuit, and for convenience, it will be used in the following description.

[0024] The drive circuit 400 is generally a three-phase drive circuit, and the corresponding bridge arm circuit is a full-bridge inverter circuit. Each bridge arm includes an upper bridge arm and a lower bridge arm, and the three-phase bridge arm includes at least six switching transistors. The pulse signal corresponding to the six switching transistors is a PWM signal as an example for description.

[0025] Figure 1The processor 200 outputs pulse signals corresponding to six switching tubes: PWM_UH, PWM_VH, PWM_WH, PWM_UL, PWM_VL, and PWM_WL. These six pulses correspond to the PWM signals of the U-phase upper bridge, V-phase upper bridge, W-phase upper bridge, U-phase lower bridge, V-phase lower bridge, and W-phase lower bridge of the three-phase bridge arm, respectively. It should be understood that the six pulse signals output by the processor 200 are not necessarily output to the drive circuit 400. The logic encapsulation circuit 100 needs to perform logical operations based on various monitoring signals to determine whether to output the pulse signal sent by the processor 200 to the drive circuit 400. When the monitoring signal determines that encapsulation is necessary, the logic encapsulation circuit 100 will block the pulse signal, and the drive circuit 400 will not operate, effectively protecting the safety of the motor control device.

[0026] The pulse signals output by the logic envelope circuit 100 include PWMH_U, PWMH_V, PWMH_W, PWML_U, PWML_V, and PWML_W, which correspond to the driving signals of the switching tubes of the U-phase upper bridge, V-phase upper bridge, W-phase upper bridge, U-phase lower bridge, V-phase lower bridge, and W-phase lower bridge of the driving circuit 400, respectively.

[0027] Chip monitoring circuit 300 monitors chip operation. When software crashes or other issues occur, chip monitoring circuit 300 outputs a fault signal, Micro_failure. For example, a low level in Micro_failure indicates a fault, while a high level indicates normal operation. Chip monitoring circuit 300 can be implemented using a watchdog circuit or chip.

[0028] Overcurrent monitoring circuit 500 monitors the three-phase current output by the motor control device for overcurrent. It outputs HV_OC if overcurrent occurs. A low level indicates overcurrent, while a high level indicates normal current. The high and low levels above are merely illustrative. It should be understood that the motor control device outputs three-phase current to the motor.

[0029] The overvoltage monitoring circuit 600 is used to monitor whether the bus voltage of the motor control device is overvoltage, and outputs HV_OV when overvoltage occurs. For example, a low level of HV_OV indicates overvoltage, and a high level of HV_OV indicates normal voltage. The above high and low levels are only examples.

[0030] The embodiments of the present application do not specifically limit the specific implementation methods of the overcurrent monitoring circuit 500 and the overvoltage monitoring circuit 600. It should be understood that the chip monitoring circuit 300, the overcurrent monitoring circuit 500 and the overvoltage monitoring circuit 600 are all existing technologies and are not specifically limited here.

[0031] In addition to the bridge arm circuit, the driver circuit 400 also includes a driver chip. The driver circuit 400 outputs monitoring signals for the driver chip. HW_GFLT_H and HW_GFLT_L represent the driver chip's upper bridge fault signal and lower bridge fault signal, respectively. For example, a low level indicates a fault, while a high level indicates normal operation. HW_GFLT_H and HW_GFLT_L serve as input signals for the logic envelope circuit 100.

[0032] The processor 200's active short-circuit ASC command ports SW_CMDH and SW_CMDL, respectively, output command signals from the processor 200 and input them into the command input ports of the logic encapsulation circuit 100. SW_CMDH and SW_CMDL implement software encapsulation, upper bridge ASC, or lower bridge ASC functions. For example, when both SW_CMDH and SW_CMDL are low, pulse signals are normally output. When both SW_CMDH and SW_CMDL are high, encapsulation is implemented. When SW_CMDH is high and SW_CMDL is low, upper bridge ASC is implemented. When SW_CMDH is low and SW_CMDL is high, lower bridge ASC is implemented.

[0033] The chip monitoring circuit 300 is connected to the processor 200 . The chip monitoring circuit 300 is used to monitor the processor 200 and send a fault signal to the chip monitoring port of the logic envelope circuit 100 when a fault occurs.

[0034] The output end of the overcurrent monitoring circuit 500 and the output end of the overvoltage monitoring circuit 600 are both connected to the electrical parameter monitoring port of the logic envelope circuit 100; the output end of the logic envelope circuit 100 is connected to the switch tube in the drive circuit 400, and the signal detection end of the drive circuit 400 is connected to the drive chip detection input end of the logic envelope circuit 100.

[0035] The logic envelope circuit 100 is used to output a pulse signal to the driving circuit 400 or block the pulse signal to the driving circuit 400 .

[0036] The logic envelope circuit 100 provided in the embodiments of the present application can be implemented using logic gates, such as, but not limited to, a combination of AND gates, NOT gates, or gates. It can also include passive components, such as resistors and capacitors. Resistors can be used to limit current, and a combination of resistors and capacitors can be used to delay time. When the lower bridge ASC is required, the three upper bridge switches are first turned off, followed by a delay, before entering the lower bridge ASC. This prevents the logic envelope circuit from simultaneously outputting high-level signals for both the upper and lower bridge drive signals. The principles for the upper bridge ASC are the same as above and will not be elaborated upon here.

[0037] The motor control device provided in the embodiments of the present application includes a logic encapsulation circuit. The logic encapsulation circuit comprises various logic gates that can perform logical operations on the signals from various monitoring circuits. When a fault occurs, the circuit can promptly encapsulate the pulse signal output by the processor, blocking it from driving the switch, thereby ensuring the safety of the drive circuit. Because the logic encapsulation circuit provided in the embodiments of the present application is implemented using hardware logic gate circuits, it has a faster response speed than software control and can provide timely protection when a fault occurs.

[0038] See also Figure 2 , this figure is a schematic diagram of another motor control device provided in an embodiment of the present application.

[0039] In the motor control device provided in the embodiment of the present application, the logic wave blocking circuit 100 is further connected to the software enable terminal of the processor 200; the software enable terminal outputs an enable signal SW_GFLT_ASC_EN, which is a switching signal used to realize whether to block the wave or actively short-circuit.

[0040] For example, when SW_GFLT_ASC_EN is at a high level, the logic envelope circuit 100 is enabled to perform active short circuit; when SW_GFLT_ASC_EN is at a low level, the logic envelope circuit 100 is enabled to perform envelope.

[0041] The internal structure of the logic envelope circuit is described in detail below with reference to the accompanying drawings.

[0042] See also Figure 3 , this figure is a schematic diagram of another motor control device provided in an embodiment of the present application.

[0043] If the motor control device provided in the embodiment of the present application does not distinguish between driving of the upper bridge arm and the lower bridge arm, the logic envelope circuit includes: a shutdown logic circuit 10, an active short-circuit ASC logic circuit 20, a shutdown path circuit and an active short-circuit ASC path circuit.

[0044] The inputs of shutdown logic circuit 10 are connected to the chip monitoring circuit, the outputs of the overcurrent monitoring circuit, the outputs of the overvoltage monitoring circuit, the ASC command port of the processor, and the signal detection terminal of the driver circuit. Specifically, the input signals of shutdown logic circuit 10 include Micro_failure, HW_GFLT_H, HW_GFLT_L, HV_OC, and HV_OV.

[0045] The input terminal of the ASC logic circuit 20 is connected to the output terminal of the overvoltage monitoring circuit and the signal detection terminal of the driving circuit. That is, the input signals of the ASC logic circuit 20 include HW_GFLT_H, HW_GFLT_L and HV_OV.

[0046] A first input terminal of the shutdown path circuit is connected to an output terminal of the shutdown logic circuit 10 , and a second input terminal of the shutdown path circuit 10 is connected to a pulse signal output terminal of the processor.

[0047] A first input terminal of the ASC path circuit is connected to an output terminal of the ASC logic circuit 20 , and a second input terminal of the ASC path circuit is connected to an output terminal of the shutdown path circuit.

[0048] The shutdown logic circuit is used to output a shutdown signal to the first input end of the shutdown path circuit based on the fault signal of the chip monitoring circuit, the signal of the output end of the overcurrent monitoring circuit, the signal of the output end of the overvoltage monitoring circuit, the signal of the ASC command port of the processor and the signal of the signal detection end of the drive circuit.

[0049] The ASC logic circuit is configured to output a short-circuit signal to the first input terminal of the ASC path circuit according to a signal at the output terminal of the overvoltage monitoring circuit and a signal at the signal detection terminal of the driving circuit.

[0050] Continue to see Figure 3 The shutdown path circuit includes: an upper bridge shutdown path circuit 31 and a lower bridge shutdown path circuit 32 .

[0051] A first input end of the upper bridge shutdown path circuit 31 is connected to the upper bridge output end of the shutdown logic circuit, and a second input end of the upper bridge shutdown path circuit 31 is connected to the upper bridge pulse signal output end of the processor.

[0052] A first input terminal of the lower bridge shutdown path circuit 32 is connected to the lower bridge output terminal of the shutdown logic circuit 10 , and a second input terminal of the lower bridge shutdown path circuit 32 is connected to the lower bridge pulse signal output terminal of the processor.

[0053] The states of the SHUTOFF_H and SHUTOFF_L outputs of the shutdown logic circuit 10 are determined by the states of the SW_CMD_H, SW_CMD_L, Micro_failure, HW_OC, HW_OV, HW_GFLT_H, and HW_GFLT_L inputs. SHUTOFF_H is input to the first input of the high-bridge shutdown path circuit 31 , and SHUTOFF_L is input to the first input of the low-bridge shutdown path circuit 32 .

[0054] The ASC path circuit includes an upper bridge ASC path circuit 41 and a lower bridge ASC path circuit 42 .

[0055] The first input end of the upper bridge ASC path circuit 41 is connected to the upper bridge output end ASC_H of the ASC logic circuit 20 , and the second input end of the upper bridge ASC path circuit 41 is connected to the upper bridge output end of the shutdown path circuit, that is, connected to the output end of the upper bridge shutdown path circuit 31 .

[0056] The first input terminal of the lower bridge ASC path circuit 42 is connected to the lower bridge output terminal ASC_L of the ASC logic circuit 20 , and the second input terminal of the lower bridge ASC path circuit 42 is connected to the lower bridge output terminal of the shutdown path circuit, that is, connected to the output terminal of the lower bridge shutdown path circuit 32 .

[0057] In addition, the logic envelope circuit provided in the embodiment of the present application can also receive an enable signal from the processor, see Figure 4 , which is a schematic diagram of another motor control device provided in an embodiment of the present application.

[0058] In the motor control device provided by the embodiment of the present application, the enable signal SW_GFLT_ASC_EN output by the processor is connected to the input end of the ASC logic circuit 20.

[0059] The shutdown logic circuit 10 is used to control the shutdown path circuit to block the pulse signal when the signal detection end of the driving circuit outputs a low level.

[0060] The ASC logic circuit 20 is used to control the lower bridge ASC path circuit of the ASC path circuit to actively short-circuit when the signal detection end of the driving circuit outputs a high level and the output end of the overvoltage detection circuit outputs a low level.

[0061] The shutdown logic circuit 10 is used to control the shutdown path circuit to block the output of the pulse signal when the signal detection end of the driving circuit outputs a high level and the output end of the overcurrent detection circuit outputs a low level.

[0062] The specific working principle is explained below in combination with the truth table of each logic circuit in the logic envelope circuit.

[0063] Table 1

[0064]

[0065]

[0066] In Table 1, the low level of each signal is represented by 0, and the high level is represented by 1. X indicates that both 1 and 0 are acceptable.

[0067] The closed wave means that the six power tubes of the processor or three-phase bridge arm are all turned off;

[0068] The upper bridge ASC indicates that the three power tubes in the upper bridge arm of the processor's three-phase are turned on, and the three power tubes in the lower bridge arm are turned off.

[0069] The lower bridge ASC indicates that the three power tubes in the upper bridge arm of the processor's three-phase are turned off, and the three power tubes in the lower bridge arm are turned on.

[0070] PWM means that the pulse signal output by the logic envelope circuit follows the pulse signal output by the processor, that is, the processor is in normal working state.

[0071] Continue to see Figure 4 , combined with Figure 4 The specific working logic is introduced with the truth table.

[0072] The software upper and lower bridge ASC paths receive the SW_CMD_L / H signal as a high level to enter the ASC, and the low level output PWM signal follows the PWM signal sent by the processor;

[0073] The logic encapsulation circuit provided in the embodiment of the present application also includes a software ASC path, which is also implemented by a logic gate circuit. The software ASC path further includes a software upper bridge ASC path and a software lower bridge ASC path. It should be understood that the input ends of the software upper bridge ASC path and the software lower bridge ASC path are respectively connected to the upper bridge arm pulse signal and the lower bridge arm pulse signal output by the processor. In addition, the upper bridge shutdown path and the lower bridge shutdown path receive the shutdown control signals SHUTOFF_H and SHUTOFF_L respectively. When the level is low, the shutdown path is shut down, and the output PWM signals are all low levels. When the level is high, it is turned on, and the output PWM signal follows the PWM signal of the previous software ASC path.

[0074] When the ASC_H / L signal is high, the output PWM signal is in the ASC state. When the ASC_H / L signal is low, the output PWM signal follows the previous shutdown path to output the PWM signal. The state of the SHUTOFF_H / L signal output by the shutdown logic circuit 10 is determined by the inputs SW_CMD_H / L, Micro_failure, HW_OC, HW_OV, HW_GFLT_H / L, and SW_GFLT_ASC_EN.

[0075] The state of the ASC_H / L signal output by the ASC logic circuit 20 depends on the states of the inputs HW_OC, HW_OV, HW_GFLT_H / L, and SW_GFLT_ASC_EN; the state of the PWM signal output by the logic envelope circuit finally conforms to the truth table logic in Table 1.

[0076] The motor control device provided in the embodiment of the present application classifies various fault signals into different levels. For fault signals with high priority, there is no need to monitor the status of other signals and the signal blocking or ASC is directly performed.

[0077] Level 1 fault signal: HW_GFLT_L, HW_GFLT_H.

[0078] Regardless of the states of the HV_OV, HV_OC, Micro_failure, SW_CMDH, and SW_CMDL signals, when both an upper and lower bridge fault occur in the driver chip within the driver circuit, the shutdown logic circuit enable output SHUTOFF_H / L in the logic encapsulation circuit is low, controlling the upper / lower bridge shutdown path circuit to output a low PWM signal. The ASC logic circuit is disabled, and the logic encapsulation circuit enters the encapsulation state, shutting down all upper and lower bridge power transistors of the inverter. When a lower or upper bridge fault occurs, the shutdown logic circuit enables the upper and lower bridge shutdown path circuits to output a low PWM signal. When the SW_GFLT_ASC_EN signal is enabled (high), the ASC logic circuit enables outputs ASC_H or ASC_L high, controlling the upper and lower bridge ASC path circuits to operate, entering the upper bridge ASC or lower bridge ASC state. The SW_GFLT_EN signal is disabled (low), and the inverter enters the encapsulation state.

[0079] Secondary fault signal: HV_OV.

[0080] When there is no driver chip fault signal, regardless of the status of the HV_OC, Micro_failure, SW_CMDH, and SW_CMDL signals, when overvoltage occurs, the shutdown logic circuit outputs the upper bridge PWM signal as a low-level signal, and the ASC control circuit outputs ASC_L as a high-level signal, controlling the ASC path circuit to enter the lower bridge ASC, that is, the logic encapsulation circuit enters the lower bridge ASC.

[0081] Level 3 fault signal: HV_OC.

[0082] When there is no driver chip and overvoltage fault signal, regardless of the status of Micro_failure, SW_CMDH, and SW_CMDL signals, when overcurrent occurs, the shutdown path circuit receives SHUTOFF_H / L as low level, outputs PWM signal as low level, and the ASC logic circuit outputs ASC_H / L as low level, and the logic wave blocking circuit enters the wave blocking state.

[0083] Level 4 fault signal: Micro_failure.

[0084] There is no driver chip fault signal, overvoltage fault signal, or overcurrent fault signal. Regardless of the status of the software output SW_CMDH and SW_CMDL signals, when a Micro_failure fault occurs, the shutdown path circuit receives SHUTOFF_H / L as low, outputs the PWM signal as low, and the ASC logic circuit outputs ASC_H / L as low, and the logic blocking circuit enters the blocking state.

[0085] Five-level control signal: SW_CMDL, SW_CMDH.

[0086] When there are no driver chip fault signals, overvoltage fault signals, overcurrent fault signals, or reset fault signals, and the processor outputs SW_CMDL and SW_CMDH are both low, the software ASC path is disabled, the output PWM signal follows the processor output PWM signal, the shutdown path circuit and the ASC path circuit are both disabled, the logic envelop circuit is in the PWM state, and the logic envelop circuit output PWM signal follows the processor output PWM signal. When the processor outputs SW_CMDL are low and SW_CMDH are high, the software high-side ASC path outputs are both high, entering the high-side ASC state. The shutdown logic circuit outputs SHUTOFF_H / L are high / low, respectively, and the low-side shutdown path circuit outputs are both low. The high-side shutdown path circuit output PWM signal follows the PWM signal output by the preceding software high-side ASC path, both high. The ASC_H / L signals remain unchanged and both low, the ASC path circuit output PWM signal follows the PWM signal output by the preceding shutdown path circuit, and the logic envelop circuit enters the high-side ASC state. Similarly, when SW_CMDL is high and SW_CMDH is low, it enters the lower bridge ASC. When both SW_CMDL and SW_CMDH are high, it enters the wave blocking state.

[0087] Through the introduction of the above truth table and working principle, it can be known that the motor control device provided in the embodiment of the present application can achieve comprehensive protection of the drive circuit by making the logic envelope circuit respond differently to different fault types.

[0088] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0089] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A motor control device, characterized in that: include: Logic wave envelope circuit, processor, chip monitoring circuit, overcurrent monitoring circuit, overvoltage monitoring circuit and drive circuit; The pulse signal output terminal of the processor is connected to the logic envelope circuit; the processor is used to output a pulse signal to the logic envelope circuit; the active short circuit ASC command port of the processor is connected to the command input port of the logic envelope circuit; The chip monitoring circuit is connected to the processor, and is used to monitor the processor and send a fault signal to the chip monitoring port of the logic envelope circuit when a fault occurs; The output end of the overcurrent monitoring circuit and the output end of the overvoltage monitoring circuit are both connected to the electrical parameter monitoring port of the logic envelope circuit; the output end of the logic envelope circuit is connected to the switch tube in the drive circuit, and the signal detection end of the drive circuit is connected to the detection input end of the drive chip of the logic envelope circuit; The logic encapsulation circuit is used to output the pulse signal to the driving circuit, or to block the pulse signal from being sent to the driving circuit.

2. The device according to claim 1, characterized in that The logic encapsulation circuit includes: a shutdown logic circuit, an active short-circuit ASC logic circuit, a shutdown path circuit and an active short-circuit ASC path circuit; The input end of the shutdown logic circuit is connected to the chip monitoring circuit, the output end of the overcurrent monitoring circuit, the output end of the overvoltage monitoring circuit, the active short circuit ASC command port of the processor and the signal detection end of the drive circuit; The input end of the active short circuit ASC logic circuit is connected to the output end of the overvoltage monitoring circuit and the signal detection end of the driving circuit; The first input end of the shutdown path circuit is connected to the output end of the shutdown logic circuit, and the second input end of the shutdown path circuit is connected to the pulse signal output end of the processor; The first input end of the active short-circuit ASC path circuit is connected to the output end of the active short-circuit ASC logic circuit, and the second input end of the active short-circuit ASC path circuit is connected to the output end of the shutdown path circuit.

3. The device according to claim 2, characterized in that The shutdown logic circuit is configured to output a shutdown signal to the first input terminal of the shutdown path circuit based on the fault signal of the chip monitoring circuit, the signal of the output terminal of the overcurrent monitoring circuit, the signal of the output terminal of the overvoltage monitoring circuit, the signal of the active short circuit ASC command port of the processor, and the signal of the signal detection terminal of the drive circuit; The active short-circuit ASC logic circuit is used to output a short-circuit signal to the first input end of the active short-circuit ASC path circuit according to the signal of the output end of the overvoltage monitoring circuit and the signal of the signal detection end of the driving circuit.

4. The device according to claim 2 or 3, characterized in that The shutdown path circuit includes: an upper bridge shutdown path circuit and a lower bridge shutdown path circuit; The first input end of the upper bridge shutdown path circuit is connected to the upper bridge output end of the shutdown logic circuit, and the second input end of the upper bridge shutdown path circuit is connected to the upper bridge pulse signal output end of the processor; The first input end of the lower bridge shutdown path circuit is connected to the lower bridge output end of the shutdown logic circuit, and the second input end of the lower bridge shutdown path circuit is connected to the lower bridge pulse signal output end of the processor.

5. The device according to claim 2 or 3, characterized in that The active short-circuit ASC path circuit includes: an upper bridge active short-circuit ASC path circuit and a lower bridge active short-circuit ASC path circuit; The first input end of the upper bridge active short-circuit ASC path circuit is connected to the upper bridge output end of the active short-circuit ASC logic circuit, and the second input end of the upper bridge active short-circuit ASC path circuit is connected to the upper bridge output end of the shutdown path circuit; The first input end of the lower bridge active short-circuit ASC path circuit is connected to the lower bridge output end of the active short-circuit ASC logic circuit, and the second input end of the lower bridge active short-circuit ASC path circuit is connected to the lower bridge output end of the shutdown path circuit.

6. The device according to claim 3, characterized in that The shutdown logic circuit is used to control the shutdown path circuit to block the pulse signal when the signal detection end of the driving circuit outputs a low level.

7. The device according to claim 5, characterized in that The active short-circuit ASC logic circuit is used to control the lower bridge active short-circuit ASC path circuit of the active short-circuit ASC path circuit to actively short-circuit when the signal detection end of the driving circuit outputs a high level and the output end of the overvoltage monitoring circuit outputs a low level.

8. The device according to claim 3, characterized in that The shutdown logic circuit is used to control the shutdown path circuit to block the pulse signal when the signal detection end of the driving circuit outputs a high level and the output end of the overcurrent monitoring circuit outputs a low level.

9. The device according to claim 5, characterized in that The active short-circuit ASC logic circuit is configured to control the upper bridge active short-circuit ASC path circuit to short-circuit the upper bridge arm switch tube of the driving circuit when the signal detection terminal of the driving circuit outputs a high level, the output terminal of the overvoltage monitoring circuit outputs a high level, the output terminal of the overcurrent monitoring circuit outputs a high level, the chip monitoring circuit outputs a high level, and the active short-circuit ASC command port of the processor outputs an upper bridge active short-circuit ASC command low level; The active short-circuit ASC logic circuit is used to output a high level at the signal detection end of the drive circuit, the output end of the overvoltage monitoring circuit outputs a high level, the output end of the overcurrent monitoring circuit outputs a high level, the chip monitoring circuit outputs a high level, and when the active short-circuit ASC command port of the processor outputs a low level of the lower bridge active short-circuit ASC command, control the lower bridge active short-circuit ASC path circuit to short-circuit the lower bridge arm switch tube of the drive circuit.

10. The device according to claim 1, characterized in that The logic encapsulation circuit is also connected to the software enable terminal of the processor; when the software enable terminal outputs a high level, the logic encapsulation circuit is enabled to actively short-circuit; when the software enable terminal outputs a low level, the logic encapsulation circuit is enabled to encapsulate.

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