Fractional frequency division mode three-ring structure frequency synthesizer based on SDM structure

Abstract

The utility model discloses a fractional frequency division mode three-ring structure frequency synthesizer based on an SDM structure, comprising a TCXO crystal oscillator circuit, a fractional frequency division PLL circuit, a dot frequency source circuit, a frequency mixing filtering amplification circuit, a main loop PLL circuit and an MCU, the output end of the TCXO crystal oscillator circuit is respectively connected with the input end of the fractional frequency division PLL circuit and the input end of the dot frequency source circuit; the TCXO crystal oscillator circuit is used for providing a crystal oscillator reference signal and taking the crystal oscillator reference signal as reference input of the fractional frequency division PLL circuit and the dot frequency source circuit, output ends of the fractional frequency division PLL circuit and the dot frequency source circuit are respectively connected with an input end of the frequency mixing, filtering and amplifying circuit, an output end of the frequency mixing, filtering and amplifying circuit is connected with an input end of the main loop PLL circuit, and an output end of the main loop PLL circuit is connected with an output end of the frequency mixing, filtering and amplifying circuit. The frequency synthesizer can effectively meet the requirements of the current fields of electronic reconnaissance, frequency spectrum monitoring equipment, broadband receivers, electronic countermeasures, instruments and meters and the like on the frequency synthesizer.

Description

Technical Field

[0001] The utility model belongs to the technical field of radio frequency microwaves, in particular to a three-ring structure frequency synthesizer based on a fractional frequency division mode of an SDM structure. Background Art

[0002] Frequency synthesizers, often called the "heart" of electronic systems and equipment, are essential for electronic reconnaissance, spectrum monitoring equipment, and broadband receivers, all of which require broadband frequency synthesizers as swept-frequency local oscillators.

[0003] Most existing fractional-mode frequency synthesizers on the market use an SDM (Sigma-Delta Modulator) structure. This structure can meet the requirements of wide bandwidth and small step sizes (capable of achieving 2-10Hz steps), but cannot achieve step sizes of 1Hz or lower. Furthermore, using a single-loop SDM structure for fractional-mode frequency synthesizers also presents the disadvantages of high integer boundary spurious emissions and potential for other fractional spurious emissions.

[0004] However, the frequency synthesizer using the fractional frequency division mode of the SDM structure also has the characteristics of low power consumption and simple structure. Utility Model Content

[0005] In order to solve the above technical problems, the utility model proposes a three-ring structure frequency synthesizer based on the fractional frequency division mode of the SDM structure, which can meet the requirements of ultra-small step, low spurious and wide-band output.

[0006] In order to achieve the above purpose, the technical solution adopted by the utility model is:

[0007] A three-ring frequency synthesizer based on a fractional frequency division mode of an SDM structure, characterized by comprising a TCXO crystal oscillator circuit, a fractional frequency division PLL circuit, a point frequency source circuit, a mixing filter amplifier circuit, a main loop PLL circuit and an MCU.

[0008] The fractional frequency PLL circuit, the point frequency source circuit and the main loop PLL circuit are connected to the MCU respectively and controlled by the MCU to work together.

[0009] The output end of the TCXO crystal oscillator circuit is connected to the input end of the fractional-frequency PLL circuit and the point frequency source circuit respectively. The TCXO crystal oscillator circuit is used to provide a crystal oscillator reference signal, and use it as a reference input of the fractional-frequency PLL circuit and the point frequency source circuit. When the crystal oscillator reference signal provided by the TCXO crystal oscillator circuit is input into the fractional-frequency PLL circuit, the fractional-frequency PLL circuit generates a spurious signal. When the crystal oscillator reference signal provided by the TCXO crystal oscillator circuit is input into the point frequency source circuit, the point frequency source circuit generates a point frequency signal.

[0010] The output ends of the fractional frequency PLL circuit and the point frequency source circuit are respectively connected to the input ends of the mixing filter amplifier circuit. The spurious signals and point frequency signals generated by the fractional frequency PLL circuit and the point frequency source circuit are mixed, filtered and amplified by the mixing filter amplifier circuit to output a reference signal.

[0011] The output end of the mixing filter amplifier circuit is connected to the input end of the main loop PLL circuit. When the reference signal enters the main loop PLL circuit, it is used as a reference for the main loop PLL circuit, and the main loop PLL circuit finally outputs a frequency based on the reference.

[0012] Furthermore: the output frequency range of the fractional frequency PLL circuit is F1 to F2, then the bandwidth of the low-frequency signal is ΔF=F2-F1,

[0013] The frequency generated by the point frequency source circuit is LO. After mixing, filtering and amplification by the mixing, filtering and amplifying circuit, the reference frequency generated is: (LO+F1)~(LO+F2), and the bandwidth of the reference signal ΔF=F2-F1.

[0014] Further: When two consecutive frequency synthesized outputs are generated, the following conditions should be met:

[0015] N1*(LO+F2) / R≥N2*(LO+F1) / R(1)

[0016] in,

[0017] N2=N1+1(2)

[0018] F2=F1+ΔF(3)

[0019] Substituting (2) and (3) into (1) we obtain:

[0020] ΔF≥(F1+LO) / N1(4)

[0021] For PLL, the N required for synthesizing the frequency is the smallest at the low end of the output frequency. Therefore, only the frequency output of the two consecutive frequency segments at the lowest end needs to be continuous, and then the entire frequency band is continuous.

[0022] Furthermore: the stray signal is a low-frequency, small-step, low-stray signal.

[0023] Furthermore: the output frequency is an output frequency with ultra-small steps, low spurious signals and X-band wide bandwidth, the ultra-small steps are steps less than 1Hz, low spurious signals are non-harmonic spurious signals less than -70dBc, and the X-band wide bandwidth is a bandwidth of 8 to 12.5G.

[0024] In the above structure: the utility model proposes a three-ring structure frequency synthesizer based on the fractional frequency division mode of the SDM structure, including a TCXO crystal oscillator circuit, a fractional frequency division PLL circuit, a point frequency source circuit, a mixing filter amplifier circuit, a main ring PLL circuit and an MCU, wherein the fractional frequency division PLL circuit, the point frequency source circuit and the main ring PLL circuit are respectively connected to the MCU and controlled by the MCU to work together to realize the data configuration of the above three circuits, thereby meeting the final frequency output.

[0025] The utility model comprises three PLLs. The first PLL is a fractional-frequency PLL circuit that uses a fractional-frequency division mode. The second PLL is a point-frequency source circuit that uses an integer-frequency division mode. The third PLL is a main-loop PLL circuit that uses an integer-frequency division mode. The signal generated by mixing the first and second PLLs serves as a reference for the third PLL.

[0026] The fractional frequency PLL circuit adopts the fractional frequency mode, and then through its internal frequency divider, the fractional frequency mode frequency synthesizer can output a signal with low frequency, small step and high spurious suppression.

[0027] The point frequency source circuit adopts integer frequency division mode and can generate a point frequency signal.

[0028] The fractional frequency PLL circuit and the point frequency source circuit are mixed through a mixing filter amplifier circuit, and the generated signal is used as a reference for the third PLL, namely the main loop PLL circuit.

[0029] The main loop PLL circuit adopts integer frequency division mode, and generates a reference signal by mixing and filtering the signals generated by the first and second PLLs to achieve the entire X-wide bandwidth output, ultra-small step and low spurious requirements.

[0030] Here's how this application works:

[0031] The TCXO crystal oscillator circuit is used to provide a crystal oscillator reference signal, and use it as a reference input for the fractional-frequency PLL circuit and the point frequency source circuit. When the crystal oscillator reference signal provided by the TCXO crystal oscillator circuit is input into the fractional-frequency PLL circuit, the fractional-frequency PLL circuit generates a spurious signal. When the crystal oscillator reference signal provided by the TCXO crystal oscillator circuit is input into the point frequency source circuit, the point frequency source circuit generates a point frequency signal.

[0032] The spurious signals and point frequency signals generated by the fractional frequency PLL circuit and the point frequency source circuit are filtered and amplified by the mixing filter amplifier circuit, and then a reference signal is output.

[0033] When the reference signal enters the main loop PLL circuit, it serves as a reference for the main loop PLL circuit, and the main loop PLL circuit ultimately outputs a frequency according to the reference.

[0034] During the operation of the fractional frequency PLL circuit, the point frequency source circuit and the main loop PLL circuit, the three are controlled by the MCU to achieve coordinated operation and configure the data of the three circuits to meet the final frequency output.

[0035] Specific frequency synthesis:

[0036] The output frequency range of the fractional frequency PLL circuit is F1~F2, so the bandwidth of the low-frequency signal is ΔF=F2-F1. The frequency generated by the point frequency source circuit is LO, so after mixing, filtering and amplification by the mixing filter amplifier circuit, the reference frequency generated is: (LO+F1)~(LO+F2), so the bandwidth of the reference signal ΔF=F2-F1.

[0037] For two consecutive frequency synthesis outputs, the following conditions should be met:

[0038] N1*(LO+F2) / R≥N2*(LO+F1) / R(1)

[0039] in,

[0040] N2=N1+1(2)

[0041] F2=F1+ΔF(3)

[0042] Substituting (2) and (3) into (1) we obtain:

[0043] ΔF≥(F1+LO) / N1(4)

[0044] For PLL, the N required for synthesizing the frequency is the smallest at the low end of the output frequency. Therefore, only the frequency output of the two consecutive frequency segments at the lowest end needs to be continuous, and then the entire frequency band is continuous.

[0045] As mentioned above, by carefully planning the F1 and bandwidth ΔF of the fractional-frequency PLL circuit's output, the spectral purity of the fractional-frequency PLL circuit's output can be very high. According to theoretical and practical testing, the spurious output is better than -94dBc. The spurious output of the reference signal generated by the mixed output of the fractional-frequency PLL circuit and the point-frequency source circuit is also better than -94dBc. The spurious output of the main-loop PLL circuit deteriorates by a maximum of 24dB, ultimately achieving a spurious output better than -70dBc.

[0046] Through the coordinated control of several PLL loops, it is ultimately possible to achieve frequency output with ultra-small steps (steps less than 1Hz), low spurious signals (non-harmonic spurious signals less than -70dBc), and wide X-band bandwidth (bandwidth of 8 to 12.5G).

[0047] Compared with the prior art, the beneficial effects of the present invention are:

[0048] The present invention provides a frequency synthesizer with ultra-small steps, low spurious signals and wide-band output, which has a simple solution, excellent performance and high reliability. It can effectively meet the current demand for frequency synthesizers in electronic reconnaissance, spectrum monitoring equipment, broadband receivers, electronic countermeasures, instrumentation and other fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a link schematic diagram of the utility model;

[0050] Figure 2 This is a schematic diagram of the frequency synthesis of FOUT1 in the present utility model;

[0051] Figure 3 This is a schematic diagram of the frequency synthesis of FOUT2 in the present utility model.

[0052] List of reference numerals:

[0053] 1. TCXO crystal oscillator circuit; 2. Fractional frequency PLL circuit; 3. Point frequency source circuit; 4. Mixer filter amplifier circuit; 5. Main loop PLL circuit. DETAILED DESCRIPTION

[0054] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0055] like Figure 1-3 As shown, the utility model proposes a three-ring structure frequency synthesizer based on the fractional frequency division mode of the SDM structure, including a TCXO crystal oscillator circuit 1, a fractional frequency division PLL circuit 2, a point frequency source circuit 3, a mixing filter amplifier circuit 4, a main loop PLL circuit 5 and an MCU.

[0056] The fractional frequency PLL circuit 2, the point frequency source circuit 3 and the main loop PLL circuit 5 are connected to the MCU respectively and controlled by the MCU to work in coordination.

[0057] The output end of the TCXO crystal oscillator circuit 1 is connected to the input end of the fractional-frequency PLL circuit 2 and the point frequency source circuit 3 respectively. The TCXO crystal oscillator circuit 1 is used to provide a crystal oscillator reference signal, and use it as a reference input of the fractional-frequency PLL circuit 2 and the point frequency source circuit 3. When the crystal oscillator reference signal provided by the TCXO crystal oscillator circuit 1 is input into the fractional-frequency PLL circuit 2, the fractional-frequency PLL circuit 2 generates a spurious signal. When the crystal oscillator reference signal provided by the TCXO crystal oscillator circuit 1 is input into the point frequency source circuit 3, the point frequency source circuit 3 generates a point frequency signal.

[0058] The output ends of the fractional frequency PLL circuit 2 and the point frequency source circuit 3 are respectively connected to the input ends of the mixing filter amplifier circuit 4. The spurious signals and point frequency signals generated by the fractional frequency PLL circuit 2 and the point frequency source circuit 3 are mixed, filtered and amplified by the mixing filter amplifier circuit 4 to output a reference signal.

[0059] The output end of the mixing filter amplifier circuit 4 is connected to the input end of the main loop PLL circuit 5. When the reference signal enters the main loop PLL circuit 5, it is used as a reference for the main loop PLL circuit 5. The main loop PLL circuit 5 finally outputs a frequency based on the reference.

[0060] The output frequency range of the fractional frequency PLL circuit 2 is F1-F2, and the bandwidth of the low-frequency signal is ΔF=F2-F1.

[0061] The frequency generated by the point frequency source circuit 3 is LO, and after mixing, filtering and amplification by the mixing, filtering and amplifying circuit 4, the reference frequency generated is: (LO+F1)~(LO+F2), and the bandwidth of the reference signal ΔF=F2-F1.

[0062] When two consecutive frequency segments are synthesized and output, the following conditions should be met:

[0063] N1*(LO+F2) / R≥N2*(LO+F1) / R(1)

[0064] in,

[0065] N2=N1+1(2)

[0066] F2=F1+ΔF(3)

[0067] Substituting (2) and (3) into (1) we obtain:

[0068] ΔF≥(F1+LO) / N1(4)

[0069] For PLL, the N required for synthesizing the frequency is the smallest at the low end of the output frequency. Therefore, only the frequency output of the two consecutive frequency segments at the lowest end needs to be continuous, and then the entire frequency band is continuous.

[0070] The stray signal is a low-frequency, small-step, low-stray signal.

[0071] The output frequency is an ultra-small step, low spurious and X-band wide-band output frequency, wherein the ultra-small step is a step less than 1 Hz, the low spurious is a non-harmonic spurious less than -70 dBc, and the X-band wide-band is a bandwidth of 8 to 12.5 GHz.

[0072] The utility model proposes a three-ring structure frequency synthesizer based on the fractional frequency division mode of the SDM structure, comprising a TCXO crystal oscillator circuit 1, a fractional frequency division PLL circuit 2, a point frequency source circuit 3, a mixing filter amplifier circuit 4, a main loop PLL circuit 5 and an MCU, wherein the fractional frequency division PLL circuit 2, the point frequency source circuit 3 and the main loop PLL circuit 5 are respectively connected to the MCU and controlled by the MCU to work together to realize the data configuration of the above three circuits, thereby meeting the final frequency output.

[0073] The present invention comprises three PLLs. The first PLL is a fractional-frequency PLL circuit 2, which operates in fractional-frequency mode. The second PLL is a point-frequency source circuit 3, which operates in integer-frequency mode. The third PLL is a main-loop PLL circuit 5, which operates in integer-frequency mode. The signal generated by mixing the first and second PLLs serves as a reference for the third PLL.

[0074] The fractional frequency PLL circuit 2 adopts a fractional frequency mode, and then through its internal frequency divider, the fractional frequency mode frequency synthesizer can output a signal with low frequency, small step and high spurious suppression.

[0075] The point frequency source circuit 3 adopts an integer frequency division mode and can generate a point frequency signal.

[0076] The fractional frequency PLL circuit 2 and the point frequency source circuit 3 are mixed through the mixing filter amplifier circuit 4, and the generated signal is used as a reference for the third PLL, namely the main loop PLL circuit 5.

[0077] The main loop PLL circuit 5 adopts integer frequency division mode, and generates a reference signal by mixing and filtering the signals generated by the first and second PLLs, thereby achieving the entire X-wide bandwidth output, ultra-small step and low spurious requirements.

[0078] Here's how this application works:

[0079] The TCXO crystal oscillator circuit 1 is used to provide a crystal oscillator reference signal, and use it as a reference input for the fractional-frequency PLL circuit 2 and the dot frequency source circuit 3. When the crystal oscillator reference signal provided by the TCXO crystal oscillator circuit 1 is input into the fractional-frequency PLL circuit 2, the fractional-frequency PLL circuit 2 generates a spurious signal. When the crystal oscillator reference signal provided by the TCXO crystal oscillator circuit 1 is input into the dot frequency source circuit 3, the dot frequency source circuit 3 generates a dot frequency signal.

[0080] The spurious signal and the point frequency signal generated by the fractional frequency PLL circuit 2 and the point frequency source circuit 3 are filtered and amplified by the mixing filter amplifier circuit 4, and then a reference signal is output.

[0081] When the reference signal enters the main loop PLL circuit 5, it serves as a reference for the main loop PLL circuit 5, and the main loop PLL circuit 5 finally outputs a frequency according to the reference.

[0082] During the operation of the fractional frequency PLL circuit 2, the point frequency source circuit 3 and the main loop PLL circuit 5, the three are controlled by the MCU to achieve coordinated operation and configure the data of the three circuits to meet the final frequency output.

[0083] Specific frequency synthesis:

[0084] The output frequency range of the fractional frequency PLL circuit 2 is F1~F2, so the bandwidth of the low-frequency signal is ΔF=F2-F1. The frequency generated by the point frequency source circuit 3 is LO, and after mixing, filtering and amplification by the mixing, filtering and amplifying circuit, the reference frequency generated is: (LO+F1)~(LO+F2), so the bandwidth of the reference signal is ΔF=F2-F1.

[0085] For two consecutive frequency synthesis outputs, the following conditions should be met:

[0086] N1*(LO+F2) / R≥N2*(LO+F1) / R(1)

[0087] in,

[0088] N2=N1+1(2)

[0089] F2=F1+ΔF(3)

[0090] Substituting (2) and (3) into (1) we obtain:

[0091] ΔF≥(F1+LO) / N1(4)

[0092] For PLL, the N required for synthesizing the frequency is the smallest at the low end of the output frequency. Therefore, only the frequency output of the two consecutive frequency segments at the lowest end needs to be continuous, and then the entire frequency band is continuous.

[0093] As described above, by carefully planning the output F1 and bandwidth ΔF of fractional-frequency PLL circuit 2, the spectral purity of the output of fractional-frequency PLL circuit 2 is very high. According to theoretical and practical testing, the spurious value is better than -94dBc. The spurious value of the reference signal generated by the mixed output of fractional-frequency PLL circuit 2 and point frequency source circuit 3 is also better than -94dBc. The spurious value of the output frequency of main loop PLL circuit 5 is then degraded by a maximum of 24dB, ultimately achieving a spurious value better than -70dBc.

[0094] Through the coordinated control of several PLL loops, it is ultimately possible to achieve frequency output with ultra-small steps (steps less than 1Hz), low spurious signals (non-harmonic spurious signals less than -70dBc), and wide X-band bandwidth (bandwidth of 8 to 12.5G).

[0095] Based on the above, the present invention provides a frequency synthesizer with a simple solution, excellent performance and high reliability, which has an ultra-small step, low spurious and wide-band output and can effectively meet the current demand for frequency synthesizers in electronic reconnaissance, spectrum monitoring equipment, broadband receivers, electronic countermeasures, instrumentation and other fields.

[0096] The above description is merely a preferred embodiment of the present invention and does not constitute any other limitation to the present invention. Any modification or equivalent variation based on the technical essence of the present invention shall still fall within the scope of protection claimed by the present invention.

Claims

1. A three-ring frequency synthesizer in fractional frequency division mode based on an SDM structure, characterized by: It includes a TCXO crystal oscillator circuit (1), a fractional frequency PLL circuit (2), a point frequency source circuit (3), a mixing filter amplifier circuit (4), a main loop PLL circuit (5) and an MCU. The fractional frequency PLL circuit (2), the point frequency source circuit (3) and the main loop PLL circuit (5) are respectively connected to the MCU and controlled by the MCU to work in coordination. The output end of the TCXO crystal oscillator circuit (1) is connected to the input end of the fractional frequency PLL circuit (2) and the point frequency source circuit (3), respectively. The TCXO crystal oscillator circuit (1) is used to provide a crystal oscillator reference signal, and use it as a reference input of the fractional frequency PLL circuit (2) and the point frequency source circuit (3). When the crystal oscillator reference signal provided by the TCXO crystal oscillator circuit (1) is input into the fractional frequency PLL circuit (2), the fractional frequency PLL circuit (2) generates a stray signal. When the crystal oscillator reference signal provided by the TCXO crystal oscillator circuit (1) is input into the point frequency source circuit (3), the point frequency source circuit (3) generates a point frequency signal. The output ends of the fractional frequency PLL circuit (2) and the point frequency source circuit (3) are respectively connected to the input ends of the mixing filter amplifier circuit (4); the spurious signals and point frequency signals generated by the fractional frequency PLL circuit (2) and the point frequency source circuit (3) are mixed, filtered and amplified by the mixing filter amplifier circuit (4), and then a reference signal is output. The output end of the mixing filter amplifier circuit (4) is connected to the input end of the main loop PLL circuit (5). When the reference signal enters the main loop PLL circuit (5), it is used as a reference for the main loop PLL circuit (5). The main loop PLL circuit (5) finally outputs a frequency based on the reference.

2. The three-ring frequency synthesizer of fractional frequency division mode based on SDM structure according to claim 1, characterized in that: The output frequency range of the fractional frequency PLL circuit (2) is F1-F2, and the bandwidth of the low-frequency signal is ΔF=F2-F1. The frequency generated by the point frequency source circuit (3) is LO, and after mixing, filtering and amplification by the mixing, filtering and amplifying circuit (4), the reference frequency generated is: (LO+F1)~(LO+F2), and the bandwidth of the reference signal ΔF=F2-F1.

3. The three-ring frequency synthesizer of fractional frequency division mode based on SDM structure according to claim 2, characterized in that: When two consecutive frequency segments are synthesized and output, the following conditions should be met: N1*(LO+F2) / R≥N2*(LO+F1) / R(1) in, N2=N1+1(2) F2=F1+ΔF(3) Substituting (2) and (3) into (1) we obtain: ΔF≥(F1+LO) / N1(4) For PLL, the N required for synthesizing the frequency is the smallest at the low end of the output frequency. Therefore, only the frequency output of the two consecutive frequency segments at the lowest end needs to be continuous, and then the entire frequency band is continuous.

4. The three-ring frequency synthesizer of fractional frequency division mode based on SDM structure according to claim 1, characterized in that: The stray signal is a low-frequency, small-step, low-stray signal.

5. The three-ring frequency synthesizer of fractional frequency division mode based on SDM structure according to claim 1, characterized in that: The output frequency is an ultra-small step, low spurious and X-band wide-band output frequency, wherein the ultra-small step is a step less than 1 Hz, the low spurious is a non-harmonic spurious less than -70 dBc, and the X-band wide-band is a bandwidth of 8 to 12.5 GHz.

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