Amplifier circuit

Abstract

The utility model relates to the field of integrated circuits, in particular to an amplifier circuit which comprises a substrate and at least one channel arranged on the substrate, and any channel comprises an operational amplifier and a feedback network. The substrate comprises a first plane and a second plane opposite to the first plane, and is provided with a through hole; the operational amplifier is arranged on a first plane, and part or all components in the feedback network are arranged on a second plane; wherein the components arranged on the first plane are connected with each other through bonding wires; the first plane is provided with a packaging layer covering the components of the first plane; the components are arranged on the second plane and are connected with each other through conduction bands; the component arranged on the first plane and the component arranged on the second plane are connected with each other through a through hole. The amplifier circuit has the advantages of being small in size, light in weight, high in integration degree and high in reliability, and the purposes of light weight, miniaturization and high integration degree of an integrated circuit are achieved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular, to an amplifier circuit. Background Art

[0002] With the rapid advancement of science and technology, the design and manufacturing of integrated circuits, as core components of modern electronic systems, has experienced unprecedented development. Miniaturization, higher performance, and higher integration have become the mainstream trend in the industry, particularly in fields such as mobile communications, the Internet of Things, wearable devices, automotive electronics, and medical electronics. In these applications, signal amplifiers, as a key link in the signal processing chain, are used to increase signal output power. Their performance and size directly impact the overall system performance and device size.

[0003] However, traditional signal amplifier designs often suffer from large size, fixed gain that is difficult to change, and limited integration. This is primarily due to the fact that traditional amplifiers utilize pre-packaged components, combined with discrete components distributed on the same side of the substrate, to achieve signal amplification. While these designs improve amplification, they also increase the board footprint and overall system weight, hindering lightweight and portability. Furthermore, they make it difficult to adjust the amplification factor to suit the user's needs. Therefore, reducing the size of signal amplifiers and improving their integration have become pressing challenges. Utility Model Content

[0004] To address the aforementioned problems in the prior art, an embodiment of the present application provides an amplifier circuit, specifically comprising: a substrate, and at least one channel disposed on the substrate, each channel including an operational amplifier and a feedback network; the substrate including a first plane and a second plane opposite to the first plane, and provided with a through hole; the operational amplifier is disposed on the first plane, and some or all components of the feedback network are disposed on the second plane;

[0005] in,

[0006] Components arranged on the first plane are connected to each other via bonding wires; the first plane is provided with a packaging layer covering the components on the first plane;

[0007] Components arranged on the second plane are connected to each other via the conductive strips;

[0008] The components arranged on the first plane and the components arranged on the second plane are connected to each other through through holes.

[0009] Optionally, any channel further includes a signal input terminal and a signal output terminal provided at an edge of the substrate, a non-inverting input terminal of an operational amplifier is connected to the signal input terminal, and an output terminal of the operational amplifier is connected to the signal output terminal;

[0010] The signal output terminals corresponding to different channels are centrally arranged on one side of the substrate, and the signal input terminals corresponding to different channels are dispersedly arranged on the other side of the substrate.

[0011] Optionally, the feedback network includes a feedback resistor and a feedback capacitor,

[0012] The feedback resistor includes: a first resistor, one end of the first resistor is connected to the inverting input terminal of the operational amplifier, and the other end is grounded; a second resistor, the second resistor is connected in parallel between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier;

[0013] The feedback capacitor includes: a first capacitor connected in parallel between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier.

[0014] Optionally, the feedback resistor includes a membrane resistor, the membrane resistor is arranged on the first plane, and other resistors in the feedback resistor and all capacitors in the feedback capacitor are arranged on the second plane.

[0015] Optionally, the first resistor is a membrane resistor and is arranged on the first plane, and the second resistor and the first capacitor are arranged on the second plane.

[0016] Optionally, a reserved pad is provided on the second plane, and the reserved pad is used for welding the third resistor so that the third resistor is connected in parallel with the second resistor.

[0017] Optionally, the reserved pad is also used to solder a second capacitor, so that the second capacitor is connected in parallel with the first capacitor.

[0018] Optionally, the operational amplifier is a J-FET type operational amplifier in the form of a bare chip, and any channel includes a fourth resistor, one end of the fourth resistor is connected to the non-inverting input terminal of the operational amplifier, and the other end is grounded, and the fourth resistor is arranged on the second plane.

[0019] Optionally, the substrate includes at least one sub-region corresponding to at least one channel;

[0020] The sub-areas include a fixed gain area and a gain adjustable area;

[0021] The fixed gain region sets a first resistor, a second resistor and a first capacitor of the corresponding channel;

[0022] The gain adjustable area is provided with a reserved pad, and the reserved pad is used to set the third resistor and the second capacitor.

[0023] Optionally, the substrate includes a plurality of ground terminals and a ground wire connected between two ground terminals. The ground wire is provided between different sub-regions, and the ground wire is used to isolate signal input terminals of different channels.

[0024] In summary, using the amplifier circuit provided in the embodiments of the present application, by arranging an operational amplifier on the first surface of the substrate and arranging some or all components of the feedback network on the second surface of the substrate, that is, arranging the operational amplifier and some or all components of the feedback network on two opposite surfaces of the substrate, respectively, the amplifier circuit is made more compact in layout, the volume of the amplifier circuit is reduced, and the miniaturization of the amplifier circuit is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0026] Figure 1 It is a side view of the substrate layout of the amplifier circuit provided in an embodiment of the present application.

[0027] Figure 2 Taking one channel as an example, a circuit schematic diagram of the amplifier circuit provided in an embodiment of the present application is shown.

[0028] Figure 3 This is a top view of the second plane layout of the substrate of the amplifier circuit provided by an embodiment of the present application.

[0029] Figure 4 This is a layout diagram of the first plane of the amplifier circuit provided in an embodiment of the present application after the second plane is flipped downward 180 degrees.

[0030] Figure 5 4 is a circuit schematic diagram of an amplifier circuit with three channels provided in an embodiment of the present application.

[0031] Note in the figure:

[0032] 1: Substrate, 2: Operational amplifier, 3: Package layer, 4: Membrane resistor. DETAILED DESCRIPTION

[0033] In this specification, it will also be understood that when an element is referred to as being relative to other elements, such as being "connected to" other elements, the one element may be directly connected to or directly coupled to the one element, or there may also be a third element in between; in addition, in the embodiments of the present application, "connection" is specifically an electrical connection.

[0034] The present application will now be described more fully below with reference to the accompanying drawings. However, the present application can be implemented in many different circuit forms and should not be construed as limited to the embodiments described herein specifically for amplifier circuits. Rather, these embodiments are provided herein to make this application more detailed and complete and to fully convey the scope of this application to those skilled in the art. Like reference numerals throughout the present application represent like objects.

[0035] At least in order to solve the problems existing in the above-mentioned prior art, the embodiment of the present application provides an amplifier circuit, such as Figure 1 As shown, the amplifier circuit includes a substrate 1 and at least one channel arranged on the substrate 1, and any channel includes an operational amplifier (UA) 2 and a feedback network; the substrate 1 includes a first plane 1a and a second plane 1b, and is provided with a through hole; the operational amplifier 2 is arranged on the first plane 1a, and some or all components in the feedback network are arranged on the second plane 1b; wherein, the components arranged on the first plane 1a are connected to each other through bonding wires; the first plane 1a is provided with a packaging layer; the components arranged on the second plane 1b are connected to each other through conduction bands; the components arranged on the first plane 1a and the components arranged on the second plane 1b are connected to each other through through holes.

[0036] The components of the amplifier circuit (e.g., the operational amplifier 2, the resistors and capacitors of the feedback network, etc.) are disposed on the first plane 1a and the second plane 1b of the substrate 1, respectively. The components disposed on the first plane 1a and the components disposed on the second plane 1b are connected via through-holes. This arrangement of the components on two opposing planes of the substrate facilitates reducing the size of the amplifier circuit and improving its integration. It should be understood that the first plane 1a and the second plane 1b refer to the back and front sides of the substrate, respectively. The operational amplifier can be a bare chip, with bonding wires connecting the operational amplifier 2 to the other components. In other embodiments, a metal conductive strip is disposed on the first plane 1a of the substrate 1. Bonding wires can be used to connect the operational amplifier 2 to the metal conductive strip, which in turn connects the operational amplifier 2 to the other components. By disposing the operational amplifier 2 as a bare chip on the first plane 1a, the bare chip is not packaged, significantly reducing its size. This significantly reduces the area occupied by the operational amplifier, further improving the integration of the amplifier circuit. Furthermore, placing the bare chip directly on the metal conductive strip facilitates heat dissipation from the bare chip.

[0037] In this embodiment, conductors are disposed within the through-holes used to connect components on the first plane 1a and the second plane 1b. Components on the first plane 1a and the second plane 1b are connected to the conductors within the through-holes, respectively, to achieve interconnection. For example, components on the second plane 1b are connected to the conductors within the through-holes via conductive strips. The through-holes are provided with pads around the opening on one side of the first plane 1a. The pads are connected to the conductors within the through-holes, and the components on the first plane 1a are connected to the pads via bonding wires.

[0038] In addition, the first plane 1a is provided with an encapsulation layer 3, which encapsulates the operational amplifier 2 and the bonding wires. Since the components located on the first plane 1a are connected to each other via bonding wires, the bonding wires are preferably silicon-aluminum alloy wires. Since the bonding wires are relatively fragile, the encapsulation layer is provided to protect the bonding wires and the bare chip from damage. Optionally, the encapsulation layer 3 is a sealing layer, such as a silicone gel layer, applied to the first plane 1a of the substrate 1, the surfaces of the components located on the first plane 1a, and the bonding wires. The sealing layer not only provides excellent protection for the bare chip and bonding wires, but also prevents corrosion from the external environment, thereby extending the service life of the amplifier circuit. The sealing layer also provides excellent heat dissipation, effectively dissipating heat generated by the components during operation, thereby ensuring the stability and reliability of the amplifier circuit. Furthermore, sealing the bare chip and bonding wires with the encapsulation layer 3 avoids placing the substrate and components in a heavy metal housing, as is done in the prior art, thereby reducing the weight of the entire amplifier circuit.

[0039] Figure 2 shows a circuit diagram of any channel in an amplifier circuit according to some embodiments, Figure 3 and Figure 4 FIG. 1 shows a schematic diagram of the layout of an amplifier circuit including three channels on the second plane and the first plane of the substrate 1 . Figure 2 The first resistor R1, the second resistor R2, the third resistor R3, the first capacitor C1, and the second capacitor C2 shown in FIG correspond to Figure 3 and Figure 4 The first resistors R11, R21 and R31, the second resistors R12, R22 and R32, the third resistors R13, R23 and R33, the first capacitors C11, C21 and C31, and the second capacitors C12, C22 and C32 of the three channels shown in FIG. In some embodiments, optionally, as Figures 2 to 4 As shown, any of the channels further includes a signal input terminal Ui and a signal output terminal Uo provided at the edge of the substrate 1, the non-inverting input terminal "+" of the operational amplifier UA is connected to the signal input terminal Ui, and the output terminal of the operational amplifier UA is connected to the signal output terminal Uo; wherein, the signal output terminals Uo corresponding to different channels are concentrated on one side of the substrate 1, and the signal input terminals Ui corresponding to different channels are dispersedly provided on other sides of the substrate 1. For example Figure 3 and Figure 4In the illustrated embodiment, the amplifier circuit includes three channels. Operational amplifiers U1A, U2A, and U3A for the three channels are disposed on the first plane 1a of the substrate 1. Signal output terminals Uo1, Uo2, and Uo3 for the three channels are all located on the first side, while signal input terminals Ui1, Ui2, and Ui3 for the three channels are located on the other three different sides of the substrate 1. It will be readily understood that the signal input terminals Ui and signal output terminals Uo of the amplifier circuit are disposed in an area near the edge of the substrate for ease of connection. Furthermore, the signal input terminals Ui and signal output terminals Uo of the amplifier circuit can each be a through-hole extending through the entire thickness of the substrate 1. Therefore, the signal input terminals Ui and signal output terminals Uo can also be referred to as signal input through-holes and signal output through-holes, respectively.

[0040] like Figure 2 As shown, when the sensor's output signal is input from the amplifier circuit's signal input terminal Ui into the amplifier circuit, the operational amplifier UA is powered simultaneously by the positive power supply VCC and the negative power supply VEE. The amplifier circuit in this embodiment can be used to convert high-impedance charge signals into low-impedance voltage signals, achieving distortion-free amplification of weak signals. In this embodiment, by arranging the signal input terminals Ui of different channels on different sides of the substrate 1, the distance between the signal input terminals Ui is increased, which helps reduce signal interference from different channel inputs to the signal input terminals Ui of other channels. Furthermore, the terminals for the positive power supply VCC and the negative power supply VEE can also be arranged on the same side of the substrate 1 as the signal output terminal Uo. In other embodiments, the signal input terminals Ui of all channels can be arranged on the same side of the substrate 1, with isolation structures provided between adjacent signal input terminals Ui to prevent signal interference. Furthermore, in embodiments where the signal output terminals Uo are arranged on the same side, isolation structures can also be provided between adjacent signal output terminals Uo to prevent interference between output signals.

[0041] In some embodiments, as Figure 2 As shown, optionally, the feedback network includes a feedback resistor and a feedback capacitor, the feedback resistor includes: a first resistor R1, one end of the first resistor R1 is connected to the inverting input terminal "-" of the operational amplifier UA, and the other end is grounded; a second resistor R2, the second resistor R2 is connected in parallel between the inverting input terminal "-" of the operational amplifier UA and the output terminal of the operational amplifier UA; the feedback capacitor includes: a first capacitor C1, the first capacitor C1 is connected in parallel between the inverting input terminal "-" of the operational amplifier UA and the output terminal of the operational amplifier.

[0042] In some embodiments, optionally, the feedback resistor includes a membrane resistor, which is arranged in the first plane, and the other resistors in the feedback resistor and all the capacitors in the feedback capacitor are arranged in the second plane. Since the membrane resistor is a film-like structure as a whole, its structural strength is relatively low, so it is arranged in the first plane and protected by the packaging layer, which is beneficial to improving the service life of the entire amplifier circuit. Optionally, the first resistor R1 is a membrane resistor and is arranged in the first plane, and the second resistor R2 and the first capacitor C1 are arranged in the second plane 1b. For example, Figure 3 and Figure 4 As shown, the first resistors R11, R21 and R31 in the three channels are arranged on the second plane of the substrate, while the second resistors R12, R22 and R32 in the three channels are arranged on the first plane of the substrate, and the first capacitors C11, C21 and C31 in the three channels are arranged on the first plane of the substrate.

[0043] In some embodiments, as Figure 1 and Figure 2 As shown, optionally, the second plane 1b is provided with a reserved pad (not shown), and the reserved pad is used to solder the third resistor R3 so that the third resistor R3 is connected in parallel with the second resistor R2. Figure 3 and Figure 4 As shown, the third resistors R13, R23 and R33 in the three channels are all connected to the reserved pads on the first plane. When designing the amplifier circuit, the multiple of the amplifier circuit amplifying the signal can be adjusted by configuring the feedback network. Among them, using two parallel resistors (such as the second resistor R2 and the third resistor R3) and connecting them in series with the first resistor R1 can improve the flexibility of the circuit design and ensure the precise control of the amplifier circuit. By setting a reserved pad on the second plane 1b of the substrate 1 for welding the third resistor R3, the core principle of this design is to directly affect the signal amplification factor Av by adjusting the ratio between the equivalent resistance of the second resistor R2 and the third resistor R3 in parallel and the first resistor R1. The expression is:

[0044] Av=1+(R2 / / R3)÷R1;

[0045] Here, “ / / ” indicates the calculation method of parallel resistance, that is, the total resistance value of two resistors connected in parallel is equal to the reciprocal of the sum of the reciprocals of their individual resistance values.

[0046] Resistors R1 and R2 are essential components in this design. Resistors R1, as part of the denominator, contribute directly to the amplification factor calculation, while resistor R2 ensures a basic amplification loop is formed even when resistor R3 is disconnected.

[0047] The flexibility of the aforementioned design allows the circuit to maintain certain functionality even when the third resistor R3 is missing. However, by providing a reserved pad on the substrate 1 and soldering the third resistor R3 to the reserved pad, fine adjustment of the amplification factor is possible. As an optional component, the addition of the third resistor R3 and the selection of its resistance value provide operability for users to customize according to specific application scenarios and amplification requirements. By changing the resistance value of the third resistor R3, users can flexibly adjust the total resistance value of the parallel resistors, thereby changing the amplification factor Av, to meet various needs from weak signal detection to strong signal amplification.

[0048] In some embodiments, the reserved pad is optionally used to solder a second capacitor C2, so that the second capacitor C2 is connected in parallel with the first capacitor C1. By providing a reserved pad on the substrate 1 to adjust the capacitance of the feedback capacitor in the amplifier circuit, the sensitivity of the amplifier circuit's amplified signal can be adjusted. By adjusting the sensitivity of the amplifier circuit according to the actual application scenario, different measurement requirements can be met.

[0049] The first capacitor C1, a necessary capacitor in the feedback loop, is directly related to the sensor's basic operating mechanism and stability. It forms a feedback network that modulates the sensor's output signal, ensuring sufficient stability and accuracy during transmission and processing. The value of the first capacitor C1 is typically determined based on the sensor's design specifications, operating environment, and required sensitivity range to ensure the sensor can operate properly under predetermined conditions. Unlike the first capacitor C1, the second capacitor C2 serves as an optional feedback capacitor, allowing the user to fine-tune the sensor's sensitivity by soldering an additional capacitor to a reserved pad. If the standard first capacitor C1 fails to meet the sensitivity requirements for a specific application, the user can increase or decrease the total capacitance of the feedback loop by soldering a second capacitor C2 to the reserved pad and adjusting its capacitance, thereby changing the sensor's sensitivity characteristics. This design not only increases the flexibility of the amplifier circuit in amplifying signals, but also enables it to be more adaptable to different measurement tasks.

[0050] Preferably, the total capacitance of the first capacitor C1 and the second capacitor C2 in parallel is set in the range of 100 to 10,000 pF. Smaller capacitance values may be suitable for applications requiring fast response and high-frequency characteristics, while larger capacitance values help stabilize the output signal and reduce noise interference, and are suitable for scenarios with high requirements for accuracy and stability.

[0051] In some embodiments, the operational amplifier UA is optionally a junction field-effect transistor operational amplifier (J-FET operational amplifier). Each channel of the amplifier circuit includes a fourth resistor R4, one end of which is connected to the non-inverting input terminal "+" of the operational amplifier UA and the other end is grounded. The fourth resistor R4 is disposed on the second plane. In amplifier circuit design, amplifiers are sensitive to DC drift (also known as offset voltage or zero-point drift) because it directly affects circuit stability and measurement accuracy. High input impedance means that the amplifier has minimal impact on the preceding circuit, thereby reducing voltage drop and signal distortion caused by the internal resistance of the signal source. In addition, the gate current of J-FET devices is extremely low, almost negligible, which helps further reduce current-induced drift. In some cases, even if the input impedance of a J-FET operational amplifier is very high, small currents may flow into or out of its input terminals. These currents may be caused by external noise sources or internal circuit imbalances. The parallel fourth resistor R4 provides a low-impedance path for these small currents, thereby diverting them away from the amplifier input terminal Ui and reducing their impact on the output signal. The fourth resistor R4 can also interact with the bias circuit or feedback network inside the amplifier circuit to help stabilize the bias point of the amplifier and reduce drift caused by temperature changes or other environmental factors.

[0052] Selecting a J-FET operational amplifier with very high input impedance and connecting a high-impedance fourth resistor R4 in parallel not only improves the circuit's anti-drift capability, but also enhances the circuit's stability and measurement accuracy, making it more suitable for high-precision measurement and signal processing applications.

[0053] In some embodiments, as Figures 3 to 5 As shown, the substrate 1 includes at least one sub-region corresponding to at least one channel; the sub-region includes a fixed gain region and a gain adjustable region ( Figure 3The fixed gain area is provided with a first resistor R1, a second resistor R2 and a first capacitor C1 for the corresponding channel; the gain adjustable area is provided with a reserved pad for setting a third resistor R3 and a second capacitor C2. The number of sub-areas provided in the substrate 1 is related to the number of channels of the amplifier circuit required by the integrated circuit. Preferably, each sub-area is provided with one channel; the sub-area includes a fixed gain area and a gain adjustable area, wherein the fixed gain area is provided with a first resistor R1, a second resistor R2 and a first capacitor C1. The first resistor R1 and the second resistor R2 are usually connected in series in the signal path to form a voltage divider circuit for setting a basic, fixed gain value. By adjusting the resistance ratio of the two resistors, a basic signal amplification factor can be preset without changing other parts of the circuit. This design ensures that the signal has a stable initial gain before entering the gain adjustable area; the first capacitor C1 is usually used for filtering or decoupling to eliminate high-frequency noise or DC components in the signal to ensure that the signal entering the gain adjustable area is clean and stable. The choice of capacitor depends on the required filtering effect and signal characteristics. The gain adjustable area is provided with reserved pads, which is beneficial for users to flexibly add or modify circuit components according to actual needs during the production or debugging stage, and facilitate subsequent adjustment of the gain by welding the third resistor R3 and the second capacitor C2 (or other components).

[0054] The above design provides flexibility and scalability, allowing the same product to adapt to the gain requirements of different application scenarios. When the third resistor R3 is soldered to the reserved pad, the third resistor R3 and the other resistor networks in the fixed gain area form a new voltage divider ratio, thereby changing the gain of the corresponding channel. By replacing resistors of different resistance values, users can adjust the gain value to adapt to different signal strengths and processing requirements; when the second capacitor C2 is soldered to the reserved pad, the signal filtering characteristics can be further adjusted or the stability of the circuit can be improved. The addition of capacitance may change the phase or frequency characteristics of the signal. The layout of the fixed gain area and the gain adjustable area not only realizes the basic amplification function of the signal, but also provides a flexible gain adjustment mechanism, so that the amplifier circuit can adapt to diverse application requirements.

[0055] In some embodiments, the substrate optionally includes multiple ground terminals and a ground wire connected between two ground terminals. The ground wire is provided between different sub-regions and is used to isolate interference between signals in different channels. The ground terminal can be arranged at the edge of the substrate 1 or can be a through hole extending through the entire thickness of the substrate 1.

[0056] Figure 5 According to some embodiments Figure 2 and Figure 3 The schematic circuit diagram of the amplifier circuit including three channels is shown in FIG. Figure 5As shown, the amplifier circuit of this embodiment can be applied to the amplifier circuit of a three-axis acceleration sensor. Given the complexity of spatial acceleration, precise decomposition and measurement along the three orthogonal axes of X, Y, and Z are required. Therefore, the amplifier circuit designed specifically for a three-axis acceleration sensor cleverly integrates three completely independent channels, each corresponding to the acceleration signal along a coordinate axis, achieving comprehensive capture and precise analysis of acceleration changes in three-dimensional space. Figure 5 The first, second and third paths correspond to one channel respectively, and the three channels can be set on the same substrate 1, such as Figure 3 and Figure 4 However, the three channels may be provided as three amplifier circuits based on different substrates 1, and the three channels may be connected to each other.

[0057] In some embodiments, as Figure 3 As shown, the substrate 1 uses a PCB (Printed Circuit Board) substrate, and the substrate 1 is a rounded rectangle as a whole, and the size can be 10.6mm×10.6mm×0.5mm. A through hole is provided on the substrate 1 that runs through the entire thickness of the substrate 1, and components related to the amplifier circuit are distributed on the front and back of the substrate 1. The components arranged on the front and back of the substrate 1 are connected through the through holes on the substrate 1. The electronic components on the back of the substrate are electrically connected with metal bonding wires, such as operational amplifiers, and the components and bonding wires arranged on the back of the substrate 1 are protected by the packaging layer 3. In this embodiment, solderable resistors, such as chip resistors with relatively large resistance (such as the second resistor R2), are arranged on the front of the substrate, and film resistors with relatively small resistance (such as the first resistor R1) are arranged on the back of the substrate 1.

[0058] like Figure 3 As shown, the front of the substrate 1 is divided into three sub-areas, and each sub-area is provided with a channel. Each sub-area is provided with a signal input terminal Ui (such as Ui1, Ui2 and Ui3), a signal output terminal Uo (such as Uo1, Uo2 and Uo3), and each sub-area is provided with a fixed gain area and a gain adjustable area ( Figure 3 The dotted line box is the gain adjustable area), where the electronic components in the gain adjustable area are electrically connected by welding for ease of processing. Figure 3As shown, Ui1, Ui2, and Ui3 are the signal input terminals Ui of the three sub-areas respectively, Uo1, Uo2, and Uo3 are the signal output terminals Uo of the three sub-areas respectively, R11, R21, and R31 are the first resistor R1, R12, R22, and R32 are the second resistor R2, R13, R23, and R33 are the third resistor R3, R14, R24, and R34 are the fourth resistor R4, C11, C21, and C31 are the first capacitor C1, and C12, C22, and C32 are the second capacitor C2. The fixed gain area is configured with the first resistor R1, the second resistor R2, the fourth resistor R4, and the first capacitor C1. The gain-adjustable area can be configured with different resistance values for the third resistor R3 and different capacitance values for the second capacitor C2 according to the specific usage environment. It should be understood that the fixed gain area and the gain adjustable area are functional descriptions and do not limit the specific distribution positions. As shown in the figure, the distribution positions of the gain adjustable areas of the three sub-areas are different. As long as the function of the amplifier circuit can be realized and the implementation method is successfully integrated into the substrate 1, it is within the protection scope of this application.

[0059] The three channels are divided by ground wires to provide isolation protection and reduce mutual interference. The signal input terminals Ui of the three sub-areas are respectively arranged on the three sides of the substrate to reduce interference with the input signal. An isolation structure is set between adjacent substrate input terminals Ui. It should be understood that the setting positions of the multiple signal input terminals Ui and signal output terminals Uo corresponding to the multiple sub-areas are not fixed, and can be adjusted according to the specific application environment, such as setting all the signal input terminals Ui on one side of the substrate and setting isolation devices between each other. It should be understood that as long as the signal amplification purpose can be achieved, it is not necessary to consider the specific setting positions of the signal input terminal Ui and the signal output terminal Uo, which are all within the protection scope of this application.

[0060] like Figure 4 As shown, a bare chip JFET (operational amplifier 2) and a thin film resistor 4 (corresponding to first resistor R1) are placed on the reverse side of substrate 1, with precise electrical connections achieved via bonding wires (e.g., silicon-aluminum alloy wires). Because the bare chip is not packaged, its size is significantly reduced, which not only reduces the weight of the entire circuit but also significantly saves space. Furthermore, the high precision and stability of the thin film resistor 4 enable the amplifier circuit to achieve more complex signal processing functions within a smaller footprint.

[0061] The circuit for signal amplification in this embodiment has electronic components arranged on the front and back sides of the substrate 1, with a compact layout, thereby achieving miniaturization of the product. At the same time, reserved pads are provided in the gain adjustable area, thereby facilitating the change of the amplification gain and sensitivity, reflecting the flexibility of the product. At the same time, no metal packaging is required, thereby achieving the goal of miniaturization and lightweight of the product.

[0062] The specific steps for making the amplifier circuit in this application include:

[0063] First, prepare the PCB substrate 1 and use etching technology to form the required metal conductive strip patterns on both sides of the substrate 1 to ensure good conductivity and reasonable layout;

[0064] Then, on the front side of the substrate 1, follow the welding process standards to weld key components such as resistors and capacitors. In particular, a flexible soldering pad area is reserved to allow users to adjust the capacitance and resistance values of resistors and capacitors according to specific needs, achieving personalized customization of gain and sensitivity.

[0065] On the back of substrate 1, a hybrid integrated circuit assembly technology is used to bond the bare chip (J-FET) and film resistor to the designated position. A silicon-aluminum alloy wire bonding process is used to achieve a high-reliability electrical connection between the bare chip and other components on the back of the substrate.

[0066] In order to ensure the stable operation and long-term reliability of the circuit, the encapsulation glue dispensing technology is used to fully cover all components and silicon-aluminum alloy wire bonding wires on the back of the substrate 1, and the encapsulation glue is uniformly dispensed and heated for multiple times to solidify.

[0067] Through the above steps, a compact, gain-adjustable amplifier circuit is obtained. This circuit not only achieves miniaturization and lightweighting, but also retains a high degree of flexibility, allowing users to easily adjust gain and sensitivity via reserved solder pads on the front. Furthermore, the through-hole design around the substrate 1 facilitates the connection of input and output signals, meeting signal amplification requirements.

[0068] Users can precisely adjust the circuit's gain and sensitivity by soldering resistors and capacitors of varying values onto the reserved pads. Furthermore, the amplifier circuit can be integrated into an integrated system through simple input and output signal connections. Alternatively, a metal or plastic housing can be added to provide additional physical protection for the entire circuit, ensuring stable operation in a variety of complex environments.

[0069] The above descriptions are only some specific embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the embodiments of the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. An amplifier circuit, characterized in that: A device comprising a substrate and at least one channel disposed on the substrate, wherein any of the channels comprises an operational amplifier and a feedback network; the substrate comprises a first plane and a second plane opposite to the first plane and provided with a through hole; the operational amplifier is disposed on the first plane, and some or all components of the feedback network are disposed on the second plane; in, The components arranged on the first plane are connected to each other through bonding wires; the first plane is provided with a packaging layer covering the components on the first plane; The components arranged on the second plane are connected to each other via the conductive strips; The components arranged on the first plane and the components arranged on the second plane are connected to each other through the through holes.

2. The circuit according to claim 1, wherein: Any of the channels further comprises a signal input terminal and a signal output terminal provided at an edge of the substrate, the non-inverting input terminal of the operational amplifier being connected to the signal input terminal, and the output terminal of the operational amplifier being connected to the signal output terminal; in, The signal output terminals corresponding to different channels are centrally arranged on one side of the substrate. The signal input terminals corresponding to different channels are dispersedly arranged on other sides of the substrate.

3. The circuit according to claim 1 or 2, characterized in that The feedback network includes a feedback resistor and a feedback capacitor, The feedback resistor includes: a first resistor, one end of the first resistor is connected to the inverting input terminal of the operational amplifier, and the other end is grounded; a second resistor, the second resistor is connected in parallel between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier; The feedback capacitor includes: a first capacitor connected in parallel between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier.

4. The circuit according to claim 3, characterized in that The feedback resistor includes a membrane resistor, and the membrane resistor is arranged on the first plane. Other resistors in the feedback resistor and all capacitors in the feedback capacitor are arranged on the second plane.

5. The circuit according to claim 4, characterized in that The first resistor is a membrane resistor and is disposed on the first plane. The second resistor and the first capacitor are disposed on the second plane.

6. The circuit according to claim 3, characterized in that The second plane is provided with a reserved pad, and the reserved pad is used for welding a third resistor so that the third resistor is connected in parallel with the second resistor.

7. The circuit according to claim 6, characterized in that The reserved pad is also used for soldering a second capacitor so that the second capacitor is connected in parallel with the first capacitor.

8. The circuit according to claim 1, wherein: The operational amplifier is a J-FET type operational amplifier in the form of a bare chip; Any of the channels includes a fourth resistor, one end of the fourth resistor is connected to the non-inverting input terminal of the operational amplifier, and the other end is grounded, and the fourth resistor is arranged on the second plane.

9. The circuit according to claim 7, characterized in that The substrate includes at least one sub-region corresponding to the at least one channel; The sub-areas include a fixed gain area and a gain adjustable area; The fixed gain region is provided with a first resistor, a second resistor and a first capacitor of a corresponding channel; The gain adjustable area is provided with the reserved pad, and the reserved pad is used to set the third resistor and the second capacitor.

10. The circuit according to claim 9, characterized in that The substrate includes a plurality of ground terminals and a ground wire connected between two of the ground terminals; The ground line is arranged between different sub-areas to isolate signals in different channels.

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