Silicon carbide VDMOS with high drain voltage overshoot resistance

Abstract

The utility model provides a silicon carbide VDMOS with high drain voltage overshoot resistance. The silicon carbide VDMOS is characterized in that a first drift layer is connected to a silicon carbide substrate; the first N-type region is connected to the first drift layer; the second N-type region is connected to the first N-type region; the P-type well region is connected to the first N-type region, the P-type well region is connected to the second N-type region, and an N-type source region is arranged on the P-type well region; a first through hole is formed in the P-type well region; the second drift layer is arranged in the first through hole, the second drift layer is connected to the first N-type region, and a second through hole is formed in the second drift layer; the insulating layer is connected with the first N-type region and is arranged in the second through hole; the gate dielectric layer is respectively connected with the N-type source region, the P-type well region, the second drift layer and the insulating layer; the source metal layer is respectively connected with the second N-type region, the P-type well region and the N-type source region; the gate metal layer is connected to the gate dielectric layer; the drain metal layer is connected to the silicon carbide substrate, so that impact of drain voltage overshoot on the grid is suppressed, heat concentration is avoided, and the reliability of the device is improved.

Description

Technical Field

[0001] The utility model relates to a silicon carbide VDMOS with high resistance to drain voltage overshoot. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and is widely used in electric vehicles, aerospace, power conversion and other fields.

[0003] In applications such as motor control systems or load switching, a short circuit in the motor or load causes the VDMOS to connect directly to the bus voltage. Since the VDMOS is in the on-state at this time, a transient short-circuit current of hundreds of amperes is generated, resulting in a significant internal transient temperature rise. Therefore, there is an urgent need to provide a silicon carbide power VDMOS with sufficiently low on-resistance and heat dissipation. Utility Model Content

[0004] The technical problem to be solved by the present invention is to provide a silicon carbide VDMOS with high tolerance to drain voltage overshoot. An insulating layer is constructed inside the device to effectively suppress the impact of drain voltage overshoot on the gate; at the same time, a first N-type region and a second N-type region are constructed to equalize the current from the body diode and the device conductive channel, avoid heat concentration, and improve device reliability.

[0005] In a first aspect, the present invention provides a silicon carbide VDMOS with high tolerance to drain voltage overshoot, comprising:

[0006] Silicon carbide substrate,

[0007] a first drift layer, wherein a lower side of the first drift layer is connected to an upper side of the silicon carbide substrate;

[0008] a first N-type region, wherein a lower side surface of the first N-type region is connected to an upper side surface of the first drift layer;

[0009] a second N-type region, wherein a lower side surface of the second N-type region is connected to an upper side surface of the first N-type region;

[0010] A P-type well region, wherein the lower side of the P-type well region is connected to the first N-type region, the outer side of the P-type well region is connected to the inner side of the second N-type region, an N-type source region is provided on the P-type well region; and a first through hole is provided in the P-type well region;

[0011] a second drift layer, wherein the second drift layer is disposed in the first through-hole, a lower side of the second drift layer is connected to an upper side of the first N-type region, and a second through-hole is disposed in the second drift layer;

[0012] an insulating layer, wherein a lower side of the insulating layer is connected to an upper side of the first N-type region, and the insulating layer is disposed in the second through-hole;

[0013] a gate dielectric layer, wherein the lower side of the gate dielectric layer is respectively connected to the upper side of the N-type source region, the upper side of the P-type well region, the upper side of the second drift layer, and the upper side of the insulating layer;

[0014] a source metal layer, the source metal layer being connected to the second N-type region, the P-type well region, and the N-type source region respectively;

[0015] a gate metal layer connected to the gate dielectric layer;

[0016] and a drain metal layer connected to the lower side of the silicon carbide substrate.

[0017] The advantages of the present invention are:

[0018] First, the present invention constructs an insulating layer directly below the gate metal layer. The thickness of this insulating layer is consistent with that of the P-type well region. When the drain is subjected to a large voltage, the insulating layer, together with the space charge region formed by the P-type well region and the second drift layer, withstands the drain voltage shock. This structure does not form a space charge region with the N-type drift layer, so it does not affect the conductive path of the device during normal conduction and does not introduce additional on-resistance to the device.

[0019] Second, the present invention constructs a second N-type region inside the device, which is used to form a Schottky contact with the source metal layer to form a Schottky diode, thereby improving the reverse recovery speed of the device and reducing the body diode conduction voltage drop of the device;

[0020] 3. The utility model constructs a first N-type region inside the device, which is distributed in the P-type well region, the second N-type region and under the insulating layer of the device. When the device is not turned on and requires body diode freewheeling, the electrons from the second N-type region can be redistributed, so that the electrons are more evenly distributed laterally in the device body. When the device is normally turned on, the electrons from the left and right sides of the insulating layer can be redistributed. The redistribution of electrons can reduce the on-resistance of the device and avoid heat concentration. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0022] Figure 1 This is a schematic diagram of a silicon carbide VDMOS with high tolerance to drain voltage overshoot according to the present invention.

[0023] Figure 2 This is a cross-sectional view of the process of a silicon carbide VDMOS with high tolerance to drain voltage overshoot in this utility model. Figure 1 .

[0024] Figure 3 This is a cross-sectional view of the process of a silicon carbide VDMOS with high tolerance to drain voltage overshoot in this utility model. Figure 2 .

[0025] Figure 4 This is a cross-sectional view of the process of a silicon carbide VDMOS with high tolerance to drain voltage overshoot in this utility model. Figure 3 .

[0026] Figure 5 This is a cross-sectional view of the process of a silicon carbide VDMOS with high tolerance to drain voltage overshoot in this utility model. Figure 4 .

[0027] Figure 6 This is a cross-sectional view of the process of a silicon carbide VDMOS with high tolerance to drain voltage overshoot in this utility model. Figure 5 .

[0028] Figure 7 This is a cross-sectional view of the process of a silicon carbide VDMOS with high tolerance to drain voltage overshoot in this utility model. Figure 6 .

[0029] Figure 8 This is a cross-sectional view of the process of a silicon carbide VDMOS with high tolerance to drain voltage overshoot in this utility model. Figure 7 .

[0030] Figure 9 This is a cross-sectional view of the process of a silicon carbide VDMOS with high tolerance to drain voltage overshoot in this utility model. Figure 8 .

[0031] Figure 10 This is a cross-sectional view of the process of a silicon carbide VDMOS with high tolerance to drain voltage overshoot in this utility model. Figure 9 .

[0032] Figure 11 This is a cross-sectional view of the process of a silicon carbide VDMOS with high tolerance to drain voltage overshoot in this utility model. Figure 10 . DETAILED DESCRIPTION

[0033] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0035] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "in contact with," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0036] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of one element or feature to other elements or features depicted in the figures. It should be understood that, in addition to the orientations depicted in the figures, spatially relative terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped over, an element or feature described as "under" or "beneath" or "beneath" the other elements would be oriented "over" the other elements or features. Thus, the exemplary terms "under" and "under" may encompass both the upper and lower orientations. Additionally, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0037] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] like Figure 1 As shown, the embodiment of the present application provides a silicon carbide VDMOS with high tolerance to drain voltage overshoot, including:

[0039] silicon carbide substrate 101,

[0040] a first drift layer 102 , wherein the lower side of the first drift layer 102 is connected to the upper side of the silicon carbide substrate 101 ;

[0041] A first N-type region 103 , wherein a lower side of the first N-type region 103 is connected to an upper side of the first drift layer 102 ;

[0042] A second N-type region 104 , wherein the lower side of the second N-type region 104 is connected to the upper side of the first N-type region 103 ;

[0043] A P-type well region 105, wherein the lower side of the P-type well region 105 is connected to the first N-type region 104, the outer side of the P-type well region 105 is connected to the inner side of the second N-type region 104, and an N-type source region 1051 is provided on the P-type well region 105; a first through hole (not shown) is provided in the P-type well region 105;

[0044] A second drift layer 106 is disposed in the first through-hole, and a lower side of the second drift layer 106 is connected to an upper side of the first N-type region 103 . A second through-hole 1061 is defined in the second drift layer 106 .

[0045] an insulating layer 107 , wherein the lower side surfaces of the insulating layer 107 are respectively connected to the upper side surfaces of the first N-type region 103 , and the insulating layer 107 is disposed in the second through-hole 1061 ;

[0046] a gate dielectric layer 108 , wherein the lower side of the gate dielectric layer 108 is respectively connected to the upper side of the N-type source region 1051 , the upper side of the P-type well region 105 , the upper side of the second drift layer 106 , and the upper side of the insulating layer 107 ;

[0047] A source metal layer 109 , wherein the source metal layer 109 is respectively connected to the second N-type region 104 , the P-type well region 105 , and the N-type source region 1051 ;

[0048] a gate metal layer 110 , wherein the gate metal layer 110 is connected to the gate dielectric layer 108 ;

[0049] and a drain metal layer 111 , wherein the drain metal layer 111 is connected to the lower side of the silicon carbide substrate 101 .

[0050] like Figures 1 to 11 As shown, the method for preparing the above-mentioned silicon carbide VDMOS includes the following steps:

[0051] Step 1: Deposit metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 111; and epitaxially grow on the side of the silicon carbide substrate 101 to form a drift region 112;

[0052] Step 2: performing ion implantation on the drift region 112 to form the first N-type region 103, the first drift layer 102, and the second drift layer 106. The ion implantation energy is 170-270 keV.

[0053] Step 3: forming a barrier layer 113 on the second drift layer 106, etching the barrier layer 113 to form a through hole, and performing ion implantation on the second drift layer 106 to form a P-type well region 105, with an ion implantation energy of 10-170 keV;

[0054] Step 4: remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, and perform ion implantation on the P-type well region 105 to form an N-type source region 1051. The ion implantation energy is 10-70 keV.

[0055] Step 5: remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, and perform ion implantation on the second drift layer 106 to form a second N-type region 104. The ion implantation energy is 10-170 keV.

[0056] Step 6: remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, and etch the second drift layer 106 to form a second through hole 1061, and deposit to form the insulating layer 107;

[0057] Step 7: removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and depositing a gate dielectric layer 108;

[0058] Step 8: removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and depositing metal to form a gate metal layer 110;

[0059] Step 9: remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, deposit metal to form a source metal layer 109, remove the barrier layer 113, and complete the preparation.

[0060] In this embodiment, preferably, the doping concentration of the first N-type region 103 is greater than the doping concentration of the first drift layer 102; the doping concentration of the first drift layer 102 is equal to the doping concentration of the second drift layer 106; the thickness of the second N-type region 104, the thickness of the P-type well region 105, the thickness of the second drift layer 106, and the thickness of the insulating layer 107 are all equal; the thickness of the first N-type region 103 is less than the thickness of the second N-type region 104; and the doping concentration of the first N-type region 103 is greater than the doping concentration of the P-type well region 105.

[0061] The silicon carbide substrate 101 is N-type, and its doping concentration is 2-8e18cm -3 The first drift layer 102 and the second drift layer 106 are N-type, and the doping concentrations of the first drift layer 102 and the second drift layer 106 are both 1-5e17cm -3 The doping concentration of the second N-type region 104 is 6-8e17cm -3 The doping concentration of the first N-type region 103 is 0.6-1.2e18cm -3 The doping concentration of the P-type well region 105 is 1-3e17 cm-3, the insulating layer 107 is silicon dioxide, the gate dielectric layer 108 is silicon dioxide, and the doping concentration of the N-type source region 1051 is 2e18 cm-3. -3 ;

[0062] The doping concentration of the N-type silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 111, thereby reducing the overall on-resistance of the device. The doping concentrations of the first drift layer 102 and the second drift layer 106 are a compromise between the reverse withstand voltage and on-resistance of the device. The doping concentration of the second N-type region 104 is to form a Schottky contact rather than an ohmic contact with the source metal layer 109, thereby constructing a parasitic Schottky diode of the device, improving the reverse recovery speed of the device, and reducing the body diode conduction voltage drop of the device. The doping concentration of the N-type source region 1051 is to form an ohmic contact with the source metal layer 109 and reduce the contact resistance. The doping concentration of the P-type well region 105 is to reduce the conductive channel on the left and right sides of the device insulating layer 107.

[0063] The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm, and the thickness of the first drift layer 102 is 20-40 μm, which can be adjusted within the above range according to the different requirements for the device's withstand voltage characteristics. The thickness of the first N-type region 103 is 300 nm, the thickness of the second N-type region 104 is 500 nm, the thickness of the N-type source region 1051 is 200 nm, the thickness of the P-type well region 105 below the N-type source region 1051 is 300 nm, and the thickness in the contact area with the source metal layer 109 is 500 nm. The width of the second drift layer on both sides of the insulating layer 107 is 300 nm. This is to avoid the influence of the insulating layer 107 on the resistance of the device JFET region. The width of the contact area between the second N-type region 104 and the source metal layer 109 is 300-600 nm, which can be individually designed according to the freewheeling capability of the body diode. The thickness of the gate dielectric layer 108 is 50 nm.

[0064] An insulating layer 107 is constructed directly below the gate of the planar-gate silicon carbide VDMOS device. The thickness of this insulating layer 107 is consistent with that of the P-type well region 105. When the drain is subjected to a large voltage, the insulating layer 107, together with the space charge region formed by the P-type well region 105 and the second drift layer 106, withstands the drain voltage shock. This structure does not form a space charge region with the second drift layer 106, so it does not affect the conductive channel of the device during normal conduction and does not introduce additional on-resistance to the device.

[0065] A second N-type region 104 is constructed inside the device. The second N-type region 104 is used to form a Schottky contact with the source metal layer 109 to form a Schottky diode, thereby improving the reverse recovery speed of the device and reducing the body diode conduction voltage drop of the device. A first N-type region 103 is constructed inside the device. The first N-type region 103 is distributed under the P-type well region 105, the second N-type region 104 and the insulating layer 107 of the device. When the device is not turned on and the body diode needs to be freewheeling, the first N-type region 103 can redistribute electrons from the second N-type region 104, so that the electrons are more evenly distributed laterally in the device body. When the device is normally turned on, the electrons from the left and right sides of the insulating layer can be redistributed. The redistribution of electrons can reduce the on-resistance of the device and avoid heat concentration.

[0066] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A silicon carbide VDMOS with high tolerance to drain voltage overshoot, characterized in that: include: Silicon carbide substrate, a first drift layer, wherein a lower side of the first drift layer is connected to an upper side of the silicon carbide substrate; a first N-type region, wherein a lower side surface of the first N-type region is connected to an upper side surface of the first drift layer; a second N-type region, wherein a lower side surface of the second N-type region is connected to an upper side surface of the first N-type region; A P-type well region, wherein the lower side of the P-type well region is connected to the first N-type region, the outer side of the P-type well region is connected to the inner side of the second N-type region, an N-type source region is provided on the P-type well region; and a first through hole is provided in the P-type well region; a second drift layer, wherein the second drift layer is disposed in the first through-hole, a lower side of the second drift layer is connected to an upper side of the first N-type region, and a second through-hole is disposed in the second drift layer; an insulating layer, wherein a lower side of the insulating layer is connected to an upper side of the first N-type region, and the insulating layer is disposed in the second through-hole; a gate dielectric layer, wherein the lower side of the gate dielectric layer is respectively connected to the upper side of the N-type source region, the upper side of the P-type well region, the upper side of the second drift layer, and the upper side of the insulating layer; a source metal layer, the source metal layer being connected to the second N-type region, the P-type well region, and the N-type source region respectively; a gate metal layer connected to the gate dielectric layer; and a drain metal layer connected to the lower side of the silicon carbide substrate.

2. The silicon carbide VDMOS with high drain voltage overshoot tolerance according to claim 1, wherein: The doping concentration of the first N-type region is greater than the doping concentration of the first drift layer; the doping concentration of the first drift layer is equal to the doping concentration of the second drift layer.

3. The silicon carbide VDMOS with high drain voltage overshoot tolerance according to claim 1, wherein: The thickness of the second N-type region, the thickness of the P-type well region, the thickness of the second drift layer, and the thickness of the insulating layer are all equal.

4. The silicon carbide VDMOS with high drain voltage overshoot tolerance according to claim 1, wherein: The thickness of the first N-type region is smaller than that of the second N-type region.

5. The silicon carbide VDMOS with high drain voltage overshoot tolerance according to claim 1, wherein: The doping concentration of the first N-type region is greater than the doping concentration of the P-type well region.

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