Semiconductor device structure

Abstract

The embodiment of the utility model provides a semiconductor device structure. The semiconductor device structure comprises a first S / D region, a first well part, a second S / D region, a second well part and an insulating structure, the first S / D region is disposed over the substrate, the first well portion is disposed under the first S / D region, the second S / D region is disposed over the substrate, the second well portion is disposed under the second S / D region, and the insulating structure is disposed between the first well portion and the second well portion. The insulating structure includes an insulating material, a first compliant layer, a second compliant layer, and a third compliant layer. The insulating material has a first height, the first compliant layer is in contact with the insulating material, and the first compliant layer has a second height different from the first height, the second compliant layer is in contact with the first compliant layer, and the second compliant layer has a third height different from the second height, the third compliant layer is in contact with the second compliant layer, the third compliant layer has a fourth height different from the third height.

Description

Technical Field

[0001] The embodiments of the utility model relate to the field of semiconductor technology, and in particular to a semiconductor device structure with a compliance layer. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have resulted in generations of ICs, each smaller and more complex than the previous. During IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be produced using a process) has decreased. This process of miniaturization generally benefits by increasing production efficiency and reducing associated costs. This miniaturization is also accompanied by more complex designs and processes for incorporating ICs into devices.

[0003] Therefore, there is a need to improve the process and manufacture of integrated circuits. Utility Model Content

[0004] One embodiment of the present invention provides a semiconductor device structure comprising a first source / drain region, a first well, a second source / drain region, a second well, and an insulating structure. The first source / drain region is disposed above a substrate, the first well is disposed below the first source / drain region, the second source / drain region is disposed above the substrate, the second well is disposed below the second source / drain region, and the insulating structure is disposed between the first well and the second well. The insulating structure comprises an insulating material, a first compliant layer, a second compliant layer, and a third compliant layer. The insulating material has a first height, the first compliant layer contacts the insulating material, and the first compliant layer has a second height different from the first height. The second compliant layer contacts the first compliant layer, and the second compliant layer has a third height different from the second height. The third compliant layer contacts the second compliant layer, and the third compliant layer has a fourth height different from the third height. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The following describes various embodiments of the present invention in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard industry practice, various components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the components may be arbitrarily enlarged or reduced to clearly illustrate the components of the present invention.

[0006] Figure 1 as well as Figure 2 FIG2 is a perspective view illustrating a semiconductor device structure at various fabrication stages according to some embodiments.

[0007] Figures 3 to 7According to some embodiments, Figure 2 Cross-sectional side views of a semiconductor device structure at various manufacturing stages.

[0008] Figure 8 to Figure 17 FIG2 is a perspective view illustrating a semiconductor device structure at various fabrication stages according to some embodiments.

[0009] Figure 12A According to some embodiments, Figure 12 A cross-sectional side view of a portion of a semiconductor device structure.

[0010] The following are the descriptions of the reference numerals:

[0011] 100:Semiconductor device structure

[0012] 101: Base

[0013] 103: first compliance layer

[0014] 104:Semiconductor layer stack

[0015] 105: Second compliance layer

[0016] 106: first semiconductor layer

[0017] 107: Third compliance layer

[0018] 108: Second semiconductor layer

[0019] 109: Fourth compliance layer

[0020] 110: oxide layer

[0021] 113: Nitride layer

[0022] 111: Insulation structure

[0023] 111t: Top surface

[0024] 112: Fin structure

[0025] 114: Groove

[0026] 116:Ibe

[0027] 116t / 116t1: Top surface

[0028] 118: first insulating material

[0029] 118t: Top surface

[0030] 119: Second insulating material

[0031] 130: Sacrificial gate structure

[0032] 132: Sacrificial gate dielectric layer

[0033] 134: Sacrificial gate electrode layer

[0034] 135: oxide layer

[0035] 136: Mask layer

[0036] 137: Nitride layer

[0037] 138: Gate spacer layer

[0038] 140: Gate spacer

[0039] 140a: Part 1

[0040] 140b: Part 2

[0041] 144: Dielectric spacer

[0042] 146: Source / drain region

[0043] 162: contact etch stop layer

[0044] 163: Interlayer dielectric layer

[0045] 168: Interface layer

[0046] 170: Gate dielectric layer

[0047] 172: Gate electrode layer

[0048] 174: Gate structure

[0049] 200: Part

[0050] 202: semiconductor layer

[0051] 204: oxide layer

[0052] T1 / T2 / T3:Thickness DETAILED DESCRIPTION

[0053] The following disclosure provides many embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description refers to a first element formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, and it may also include an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact. In addition, the embodiments of the present invention may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and is not intended to indicate the relationship between the different embodiments and / or configurations discussed.

[0054] Furthermore, spatially relative terms such as "below," "beneath," "lower," "above," "upper," "top," "upper," and the like may be used to facilitate describing the relationship between one component or parts and another component or parts in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is rotated 90 degrees or otherwise, the spatially relative adjectives used therein will also be interpreted based on the orientation after the rotation.

[0055] The present invention provides a semiconductor device structure and a method for forming the same. In some embodiments, the insulating structure includes a plurality of compliant layers to prevent epitaxial components from being formed on the sidewalls of the fin structure.

[0056] Although some of the embodiments described herein are described in the context of nanosheet channel field-effect transistors (FETs), some embodiments of the present invention may be used in other processes and / or other devices, such as fin-like field effect transistors (FinFETs), horizontal gate all around (HGAA) FETs, vertical gate all around (VGAA) FETs, and other suitable devices. A person skilled in the art will readily understand other modifications that may be made within the scope of the embodiments of the present invention. In the case of a gate-all-around (GAA) transistor structure, the GAA transistor structure may be patterned by any suitable method. For example, one or more photolithography processes may be used to pattern the structure, including double patterning or multiple patterning processes. Generally speaking, double patterning or multiple patterning processes combine photolithography processes with self-alignment processes to create, for example, a pattern with a smaller pitch than that obtained using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the GAA structure.

[0057] Figures 1 to 17 FIG. 1 is an exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of the present invention. It should be understood that additional embodiments of the method may be Figures 1 to 17 Additional operations are provided before, during, and after the steps shown, and some of the steps described below may be replaced or deleted in additional embodiments of the method. The order of the steps / processes is not limited and may be interchanged.

[0058] Figure 1 as well as Figure 2 FIG. 1 is a perspective view illustrating a semiconductor device structure 100 at various manufacturing stages according to some embodiments. Figure 1As shown, semiconductor device structure 100 includes a semiconductor layer stack 104 formed over a front side of substrate 101. Substrate 101 may be a semiconductor substrate. Substrate 101 may include crystalline semiconductor materials such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenide antimony (GaAsSb), and indium phosphide (InP). In some embodiments, substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one embodiment, the insulating layer is an oxygen-containing layer.

[0059] The substrate 101 may include various regions doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopant may be, for example, phosphorus for an n-type field effect transistor (NFET) and boron for a p-type field effect transistor (PFET).

[0060] The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructured channels in multi-gate devices, such as nanostructured channel FETs. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first and second semiconductor layers 106, 108. The first and second semiconductor layers 106, 108 are made of semiconductor materials having different etch selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be made of silicon (Si), and the second semiconductor layer 108 may be made of silicon germanium (SiGe). In some examples, the first semiconductor layer 106 may be made of silicon germanium (SiGe), and the second semiconductor layer 108 may be made of silicon (Si). Alternatively, in some embodiments, either of the semiconductor layers 106, 108 may be or may include other materials, such as germanium (Ge), silicon carbon (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), or any combination of the foregoing.

[0061] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the film layers of the semiconductor layer stack 104 can be performed by molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0062] The first semiconductor layer 106 or a portion of the first semiconductor layer 106 may form the nanosheet channel(s) of the semiconductor device structure 100 in a subsequent manufacturing stage. The term nanostructure is used herein to refer to any material portion having nanoscale or even microscale dimensions and having an elongated shape, regardless of the cross-sectional shape of such portion. Thus, this term refers to elongated material portions having circular and substantially circular cross-sections, as well as bundle or strip-shaped material portions, including, for example, cylindrical or substantially rectangular cross-sections. The nanosheet channel(s) of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanostructure transistor. A nanostructure transistor may be referred to as a nanosheet transistor, a nanowire transistor, a gate-all-around (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding a channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is discussed further below.

[0063] Each first semiconductor layer 106 may have a thickness ranging from about 5 nanometers (nm) to about 30 nm. Each second semiconductor layer 108 may have a thickness equal to, less than, or greater than that of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness ranging from about 2 nm to about 50 nm. The three first semiconductor layers 106 and the three second semiconductor layers 108 are alternately arranged, as shown in FIG. Figure 1 , which is for illustrative purposes and is not intended to be limiting beyond what is specifically set forth in the claims. It should be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the semiconductor layer stack 104, and the number of film layers depends on the desired number of channels of the semiconductor device structure 100. Figure 1As shown, an oxide layer 110 is formed on the topmost first semiconductor layer 106, and a nitride layer 113 is formed on the oxide layer 110. The oxide layer 110 may be silicon oxide and may have a different etching selectivity than the nitride layer 113. The nitride layer 113 may include any suitable nitride material, such as silicon nitride. In some embodiments, the oxide layer 110 and the nitride layer 113 may be a mask structure.

[0064] exist Figure 2 In the embodiment of the present invention, fin structures 112 are formed by semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106 and 108, and a well portion 116 formed by substrate 101. Fin structures 112 can be formed by patterning a hard mask layer (such as oxide layer 110 and nitride layer 113) formed on semiconductor layer stack 104 using multiple patterning operations including photolithography and etching processes. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process may include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure bake process, and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, patterning the photoresist layer to form the mask element may be performed using an electron beam (e-beam) lithography process. The etching process forms trenches 114 in the unprotected area through the hard mask layer, the semiconductor layer stack 104, and into the substrate 101, leaving a plurality of extended fin structures 112. The trenches 114 extend along the X-direction. The trenches 114 can be etched using dry etching (e.g., RIE), wet etching, and / or a combination thereof.

[0065] Figures 3 to 7 According to some embodiments, Figure 2 The cross-sectional side view of the semiconductor device structure 100 at various manufacturing stages is shown in FIG. Figure 3As shown, after forming the fin structure 112, a first compliant layer 103 is deposited on the exposed surface of the semiconductor device structure 100, a second compliant layer 105 is deposited on the first compliant layer 103, a third compliant layer 107 is deposited on the second compliant layer 105, and a fourth compliant layer 109 is deposited on the third compliant layer 107. In some embodiments, a semiconductor layer (not shown) may be first formed on the sidewalls of the semiconductor layer stack 104 and the sidewalls of the well 116, and the first compliant layer 103 is deposited on the semiconductor layer. In some embodiments, the semiconductor layer is a silicon layer, such as a crystalline silicon layer. The semiconductor layer may have a thickness ranging from approximately 0.1 nm to approximately 5 nm. The first compliant layer 103 may include a dielectric material, such as an oxide, for example, silicon oxide. In some embodiments, the first compliant layer 103 is formed by an oxidation process. The oxidation process oxidizes the semiconductor material of the semiconductor device structure 100 to form the first compliant layer 103 including silicon oxide. In some embodiments, the first compliant layer 103 is formed by a compliant process such as atomic layer deposition (ALD). The first compliant layer 103 may have a thickness ranging from approximately 0.1 nm to approximately 10 nm. The first compliant layer 103 may serve as an adhesion layer for the second compliant layer 105 or the third compliant layer 107. In other words, the second compliant layer 105 or the third compliant layer 107 may not adhere to the semiconductor material of the substrate 101, but may adhere to the first compliant layer 103.

[0066] The second compliant layer 105 may include a dielectric material, such as a low-k dielectric material, such as a nitrogen-containing low-k dielectric material. In some embodiments, the dielectric material includes silicon, oxygen, and nitrogen. For example, the dielectric material may be silicon oxynitride (SiON) having 31 atomic percent silicon, 52 atomic percent oxygen, and 17 atomic percent nitrogen. The second compliant layer 105 may be formed by any suitable process. In some embodiments, the second compliant layer 105 is formed by a compliant process such as ALD. The second compliant layer 105 may have a thickness ranging from approximately 0.1 nm to approximately 5 nm.

[0067] The third compliant layer 107 may include a dielectric material, such as a carbon-containing dielectric material. In some embodiments, the dielectric material includes silicon, carbon, oxygen, and nitrogen. For example, the dielectric material may be silicon oxycarbon nitride (SiOCN) having 26 atomic percent silicon, 3 atomic percent carbon, 62 atomic percent oxygen, and 9 atomic percent nitrogen. The third compliant layer 107 may be formed by any suitable process. In some embodiments, the third compliant layer 107 is formed by a compliant process such as ALD. The third compliant layer 107 may have a thickness ranging from approximately 0.1 nm to approximately 5 nm. In some embodiments, the third compliant layer 107 is deposited on the first compliant layer 103, and the second compliant layer 105 is deposited on the third compliant layer 107.

[0068] The fourth compliant layer 109 may include a semiconductor material, such as amorphous silicon. The fourth compliant layer 109 may be formed by any suitable process. In some embodiments, the fourth compliant layer 109 is formed by a compliant process such as ALD. The fourth compliant layer 109 may have a thickness ranging from approximately 0.1 nm to approximately 5 nm.

[0069] like Figure 4 As shown, the first insulating material 118 is deposited in the trenches 114 between adjacent fin structures 112. The first insulating material 118 is deposited on the fourth conformal layer 109. The first insulating material 118 can be deposited from bottom to top, as shown in FIG. Figure 4 In some embodiments, the first insulating material 118 is deposited by a flowable chemical vapor deposition (FCVD) process. The first insulating material 118 includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0070] (SiON), silicon oxycarbon nitride (SiOCN), silicon carbon nitride (SiCN), fluorine-dopedsilicate glass (FSG), low-K dielectric material, or any suitable dielectric material. In some embodiments, the first insulating material 118 includes a dielectric material having a lower K value than the first, second, and third compliant layers. Figure 4 As shown, the top surface 118t of the first insulating material 118 may be located substantially below the top surface 116t of the well portion 116. The first insulating material 118 has a thickness T1, as shown in FIG. Figure 4 The thickness T1 may be in the range of about 200 nm to about 300 nm.

[0071] After depositing the first insulating material 118, a first annealing process is performed to solidify or harden the first insulating material 118. The first annealing process can be performed at a temperature of approximately 500 degrees Celsius to approximately 800 degrees Celsius. In some embodiments, an oxygen-containing gas can be used in the first annealing process, and the fourth compliant layer 109 can be exposed to and oxidized by the oxygen-containing gas. In addition, oxygen in the first insulating material 118 can diffuse into the portion of the fourth compliant layer 109 that contacts the first insulating material 118, thereby oxidizing the portion of the fourth compliant layer 109. In this way, the first annealing process converts the fourth compliant layer 109 into an oxide, such as silicon oxide. The oxidation of the fourth compliant layer 109 causes the fourth compliant layer 109 to expand, which pushes away the third compliant layer 107, the second compliant layer 105, and the first compliant layer 103. As a result, the density of the third compliant layer 107, the second compliant layer 105, and the first compliant layer 103 is increased, and after the first annealing process, the third compliant layer 107, the second compliant layer 105, and the first compliant layer 103 have improved film quality, such as an improved wet etch rate (WER). In addition, during the first annealing process, carbon and nitrogen in the second compliant layer 105 and the third compliant layer 107 can diffuse through the fourth compliant layer 109 into the first insulating material 118. The first insulating material 118 with the carbon and nitrogen diffused therein has improved film quality, such as an improved WER.

[0072] like Figure 5 As shown, the second insulating material 119 is deposited on the first insulating material 118 and above the fin structure 112. The second insulating material 119 is also deposited on the fourth compliant layer 109. The second insulating material 119 comprises a different material than the first insulating material 118. In some embodiments, the second insulating material 119 is a dielectric material such as plasma enhanced oxide (PEOX). Compared to the first insulating material 118, the second insulating material 119 is Figure 11 The recessing of the portion of the fin structure 112 shown may have a slower etching rate. In other words, the second insulating material 119 protects the first insulating material 118. In some embodiments, the second insulating material 119 comprising PEOX is formed at a slower rate than the first insulating material 118 formed by FCVD. Figure 5 As shown, a second insulating material 119 is deposited over the fin structure 112 to embed the fin structure 112 .

[0073] like Figure 6As shown, the second insulating material 119, the first compliant layer 103, the second compliant layer 105, the third compliant layer 107, and the fourth compliant layer 109 are recessed. In some embodiments, a planarization operation such as a chemical mechanical polishing (CMP) method is performed so that the top of the fin structure 112 is exposed. The planarization process removes a portion of the second insulating material 119, a portion of the first compliant layer 103, a portion of the second compliant layer 105, a portion of the third compliant layer 107, and a portion of the fourth compliant layer 109 formed above the fin structure 112. After the planarization process, a second annealing process is performed to harden the second insulating material 119. The second annealing process may be the same as or different from the first annealing process. The second annealing process may cause carbon and nitrogen to further diffuse from the second compliant layer 105 and the third compliant layer 107 to the first insulating material 118 and the second insulating material 119. As a result, the film quality of the first insulating material 118 and the second insulating material 119 , such as WER, can be improved.

[0074] Next, if Figure 7 As shown, one or more etching processes are performed to recess portions of the second insulating material 119, the first compliant layer 103, the second compliant layer 105, the third compliant layer 107, and the fourth compliant layer 107 formed between adjacent fin structures 112. The resulting insulating structure 111 disposed between adjacent fin structures 112 may be shallow trench isolation (STI). The insulating structure 111 includes a first insulating material 118, a second insulating material 119 disposed on the first insulating material 118, a fourth compliant layer 109 in contact with at least three sides of the first insulating material 118 and the second insulating material 119, the third compliant layer 107 in contact with the fourth compliant layer 109, the second compliant layer 105 in contact with the third compliant layer 107, and the first compliant layer 103 in contact with the second compliant layer 105.

[0075] In some embodiments, due to the different materials of the second insulating material 119, the first compliant layer 103, the second compliant layer 105, the third compliant layer 107, and the fourth compliant layer 109, the top surface of the resulting insulating structure 111 may not be substantially flat. In some embodiments, the top surface of the insulating structure 111 may be curved, such as a concave top surface. The top surfaces of the first, second, third, and fourth compliant layers 103, 105, 107, 109 may be located higher than the top surface of the second insulating material 119. In some embodiments, the highest point of the top surface of the insulating structure 111 may be flush with or lower than the top surface 116t of the well 116. In some embodiments, during the recessing of the second insulating material 119 , the first compliant layer 103 , the second compliant layer 105 , the third compliant layer 107 , and the fourth compliant layer 109 , the oxide layer 110 and the nitride layer 113 are also removed.

[0076] like Figure 7 As shown, after recessing second insulating material 119, first compliant layer 103, second compliant layer 105, third compliant layer 107, and fourth compliant layer 109, second insulating material 119 has a thickness T2. In some embodiments, thickness T2 ranges from approximately 50 nm to approximately 150 nm. Thickness T2 may be substantially less than thickness T1. The total thickness T3 of first insulating material 118 and second insulating material 119 may range from approximately 250 nm to approximately 450 nm. In some embodiments, thickness T2 ranges from approximately 15% to approximately 45% of total thickness T3. As described above, second insulating material 119 protects first insulating material 118 and is deposited at a slower rate than first insulating material 118. Therefore, if thickness T2 is less than approximately 15% of total thickness T3, second insulating material 119 may not adequately protect first insulating material 118. On the other hand, if the thickness T3 is greater than about 45% of the total thickness T3 , the process of forming the insulating structure 111 may take too long because the process of depositing the second insulating material 119 is slow.

[0077] Figure 8 to Figure 17 FIG. 1 is a perspective view illustrating a semiconductor device structure 100 at various fabrication stages according to some embodiments. Figure 8 yes Figure 7 FIG. 1 is a perspective view of a semiconductor device structure 100 shown in FIG. 1 . For clarity, details of the insulating structure 111 are omitted. Figure 9As shown, one or more sacrificial gate structures 130 are formed over the semiconductor device structure 100. The sacrificial gate structures 130 are formed over a first portion of the fin structure 112 and a first portion of the insulating structure 111, while exposing a second portion of the fin structure 112 and a second portion of the insulating structure 111. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. In some embodiments, the mask layer 136 is a multi-layer structure. For example, the mask layer 136 includes an oxide layer 135 and a nitride layer 137 formed on the oxide layer 135. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning these layers into the sacrificial gate structure 130. The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as a material primarily composed of silicon oxide. The sacrificial gate electrode layer 134 may include silicon, such as polysilicon or amorphous silicon. The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region for the semiconductor device structure 100.

[0078] like Figure 10 As shown, a gate spacer layer 138 is formed to cover the sacrificial gate structure 130, the second portion of the fin structure 112, and the second portion of the insulating structure 111. The gate spacer layer 138 may include one or more layers of dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbon nitride (SiCN), silicon oxycarbide, silicon oxycarbon nitride (SiOCN), and / or combinations thereof. In some embodiments, the gate spacer layer 138 includes two dielectric layers. In some embodiments, the gate spacer layer 138 is formed by a compliant process, such as an atomic layer deposition (ALD) process. In some embodiments, the gate spacer layer 138 has a thickness ranging from approximately 2 nm to approximately 10 nm.

[0079] like Figure 11 As shown, an anisotropic etching process is performed to remove the horizontal portion of the gate spacer layer 138. The anisotropic etching process may be a selective etching process that does not substantially affect the nitride layer 137, the first semiconductor layer 106, and the insulating structure 111. In this way, the second portion of the fin structure 112 is exposed.

[0080] like Figure 12As shown, one or more etching processes are performed to recess the exposed second portion of the fin structure 112 that is not covered by the sacrificial gate structure 130 (and the portion of the gate spacer layer 138 formed on the sidewalls of the sacrificial gate structure 130) and remove the portion of the gate spacer layer 138. The portion of the gate spacer layer 138 formed on the sidewalls of the mask layer 136 may also be recessed. The one or more etching processes may include dry etching (such as reactive ion etching (RIE), neutron beam etching (NBE), etc.) and / or wet etching (such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH)). The one or more etching processes form the gate spacer 140, which includes a first portion 140a formed on the sidewalls of the sacrificial gate electrode layer 134 and a second portion 140b formed on the second portion of the insulating structure 111. In some embodiments, as Figure 12 As shown, the one or more etching processes also remove a portion of the second portion of the insulating structure 111. As a result, after the one or more etching processes, the top surface 111t of the second portion of the insulating structure 111 is located at a level substantially lower than the top surface 116t1 of the well 116. Figure 12 As shown, top surface 116t1 may be below the level of top surface 116t.

[0081] Figure 12A According to some embodiments, Figure 12 A cross-sectional side view of a portion 200 of a semiconductor device structure 100 is shown. Figure 12A As shown, the first compliant layer 103, the second compliant layer 105, the third compliant layer 107, and the fourth compliant layer 109 are recessed by one or more etching processes to recess the exposed second portion of the fin structure 112. In some embodiments, the one or more etching processes also remove the second insulating material 119 and recess the first insulating material 118, as shown in FIG. Figure 12A As shown. In some embodiments, the semiconductor device structure 100 includes a semiconductor layer 202 and an oxide layer 204. The semiconductor layer 202 may include crystalline silicon, and the oxide layer 204 may include silicon oxide. In some embodiments, the semiconductor layer 202 is formed on the fin structure 112, and the first conformal layer 103 is formed on the semiconductor layer 202. The oxide layer 204 is formed by oxidizing the semiconductor layer 202 during the first annealing process. Figure 12AAs shown, the semiconductor layer 202 and the oxide layer 204 are recessed together with the fin structure 112, and a portion of the first compliant layer 103 adjacent to the oxide layer 204 is also removed. As described above, the oxidation of the fourth compliant layer 109 densifies the first, second, and third compliant layers 103, 105, 107 and improves the film quality of the first, second, and third compliant layers 103, 105, 107. In this way, the second compliant layer 105 and / or the first compliant layer 103 are not laterally etched through. In other words, after one or more etching processes, the sidewalls of the well 116 are not exposed. If the first, second, and third compliant layers 103, 105, 107 are not present, one or more etching processes can remove portions of the oxide layer 204 and the semiconductor layer 202 to expose the sidewalls of the well 116. In this way, the source / drain (S / D) region 146 ( Figure 15 ) may be formed on the sidewall of the well 116 and cause leakage current.

[0082] like Figure 12A As shown, in some embodiments, the first insulating material 118 has a first height in the Z direction, the fourth compliant layer 109 has a second height substantially higher than the first height, the third compliant layer 107 has a third height substantially higher than the second height, the second compliant layer 105 has a fourth height substantially higher than the third height, and the first compliant layer 103 has a fifth height substantially the same as or higher than the fourth height. In some embodiments, as a result of one or more etching processes, the thicknesses of the first, second, third, and fourth compliant layers 103, 105, 107, 109 may decrease in a direction away from the substrate 101 (upward in the Z direction).

[0083] like Figure 13 As shown, ends of each second semiconductor layer 108 of the semiconductor layer stack 104 are horizontally removed along the X-direction. Removing the ends of the second semiconductor layers 108 forms cavities. In some embodiments, portions of the second semiconductor layers 108 are removed by a selective wet etching process. When the second semiconductor layers 108 are made of silicon germanium (SiGe) and the first semiconductor layer 106 is made of silicon (Si), the second semiconductor layers 108 can be selectively etched using a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), and / or potassium hydroxide (KOH) solution.

[0084] Figure 14 As shown, after removing the end portion of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form dielectric spacers 144. Dielectric spacers 144 can be made of a low-K dielectric material such as silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN), or silicon nitride (SiN). Dielectric spacers 144 can be formed by first forming a compliant dielectric layer using a compliant deposition process such as ALD, followed by an anisotropic etching process to remove portions of the compliant dielectric layer except for the dielectric spacers 144. During the anisotropic etching process, dielectric spacers 144 are protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 is covered between the dielectric spacers 144 along the X direction.

[0085] like Figure 15 As shown, source / drain (S / D) regions 146 are formed by the well 116. The S / D regions 146 can be grown vertically and horizontally to form facets that can correspond to the crystalline planes of the material used for the well 116. In embodiments of the present invention, source and drain regions can be used interchangeably and their structures are substantially the same. In addition, the source / drain regions can refer to the source or drain individually or collectively depending on the context. The S / D regions 146 can be made of one or more layers of silicon (Si), silicon phosphide (SiP), silicon carbon (SiC), and silicon carbon phosphide (SiCP) for n-type channel FETs, or one or more layers of silicon (Si), silicon germanium (SiGe), and germanium (Ge) for p-type channel FETs. For p-type channel FETs, p-type dopants such as boron (B) can also be included in the S / D regions 146. The S / D regions 146 may be formed by epitaxial growth using chemical vapor deposition (CVD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE).

[0086] like Figure 15As shown, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. CESL 162 covers the sidewalls of the first portion 140a of the gate spacer 140 and is disposed on the second portion 140b of the gate spacer 140 and the S / D region 146. CESL 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, or a combination thereof, and may be formed by CVD, plasma-enhanced chemical vapor deposition (PECVD), ALD, or any other suitable deposition technique. Next, an interlayer dielectric (ILD) layer 163 is formed on CESL 162. The material of the ILD layer 163 may include a compound containing silicon (Si), oxygen (O), carbon (C), and / or hydrogen (H), such as silicon oxide, silicon carbon hydroxide (SiCOH), or silicon oxycarbide (SiOC). Organic materials such as polymers may also be used for the ILD layer 163. The ILD layer 163 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the ILD layer 163, the semiconductor device structure 100 may be subjected to a heat treatment to anneal the ILD layer 163.

[0087] A planarization process is performed to expose the sacrificial gate electrode layer 134, such as Figure 15 The planarization process may be any suitable process, such as a chemical mechanical polish (CMP) process. The planarization process removes a portion of the ILD layer 163 disposed on the sacrificial gate stack 130 and a portion of the CESL 162. The planarization process may also remove the mask structure 136.

[0088] like Figure 16As shown, the sacrificial gate electrode layer 134 and the sacrificial gate dielectric layer 132 are removed, exposing a portion of the top surface of the topmost first semiconductor layer 106. A first portion of the insulating structure 111 is also exposed. The sacrificial gate electrode layer 134 can be removed first by any suitable process, such as dry etching, wet etching, or a combination thereof, followed by the removal of the sacrificial gate dielectric layer 132, which can be performed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant, such as a tetramethylammonium hydroxide (TMAH) solution, can be used to selectively remove the sacrificial gate electrode layer 134 without removing the spacers 140, the insulating structure 111, the ILD layer 163, and the CESL 162.

[0089] After removing the sacrificial gate electrode layer 134 and the sacrificial gate dielectric layer 132, a selective wet etching process can be used to remove the second semiconductor layer 108. In the case where the second semiconductor layer 108 is made of silicon germanium (SiGe) and the first semiconductor layer 106 is made of silicon (Si), the chemistry used in the selective wet etching process removes the SiGe while substantially leaving the Si, the gate spacer 140, the insulating structure 111, and the dielectric material of the dielectric spacer 144 unaffected. In one embodiment, the second semiconductor layer 108 can be removed using a wet etchant, such as, but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4), a dry etchant, such as a fluorine-based gas (e.g., fluorine (F2)) or a chlorine-based gas (e.g., chlorine (Cl2)), or any suitable isotropic etchant.

[0090] like Figure 17As shown, after forming the nanostructured channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed to surround the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as a gate structure 174. In some embodiments, an interfacial layer (IL) 168 is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. The IL 168 may include an oxide, such as silicon oxide, and may be formed as a result of a cleaning process. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, or a high-K dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-K dielectric materials include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium oxysilicide nitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO), aluminum oxide (Al2O3), a hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-K dielectric materials, and / or combinations thereof. The gate dielectric layer 170 can be formed by CVD, ALD, or any other suitable deposition technique. The gate electrode layer 172 may include one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), metal alloys, other suitable materials, and / or any combination thereof. The gate electrode layer 172 may be formed by CVD, ALD, electroplating, or other suitable deposition techniques. A gate dielectric layer 170 and a gate electrode layer 172 may also be deposited over the ILD layer 163. The gate dielectric layer 170 and the gate electrode layer 172 formed over the ILD layer 163 are then removed by, for example, CMP until the top surface of the ILD layer 163 is exposed.

[0091] Embodiments of the present invention provide a semiconductor device structure and a method for forming the same. Semiconductor device structure 100 includes an insulating structure 111 having first, second, third, and fourth compliant layers 103, 105, 107, and 109. Some embodiments can achieve advantages. For example, compliant layers 103, 105, 107, and 109 protect the sidewalls of well 116 during the recessed portion of fin structure 112. As a result, epitaxial features are not formed on the sidewalls of fin structure 112.

[0092] An embodiment of the present invention provides a method for forming a semiconductor device structure, the method comprising: forming a first fin structure and a second fin structure from a substrate, depositing a first conformal layer above the first fin structure and the second fin structure and between the first fin structure and the second fin structure, depositing a second conformal layer on the first conformal layer, depositing a third conformal layer on the second conformal layer, depositing a fourth conformal layer on the third conformal layer, depositing a first insulating material on the fourth conformal layer between the first fin structure and the second fin structure, and depositing a second insulating material on the first insulating material. The first fin structure and the second fin structure are embedded by the second insulating material. The method further comprises: removing a portion of the second insulating material, the first conformal layer, the second conformal layer, the third conformal layer, and the fourth conformal layer to expose the first fin structure and the second fin structure.

[0093] In one embodiment, the first fin structure and the second fin structure each include alternating first and second semiconductor layers disposed on a well portion. In one embodiment, the well portion has a first top surface, and the top surfaces of the second insulating material, the first compliant layer, the second compliant layer, the third compliant layer, and the fourth compliant layer are flush with or below the first top surface. In one embodiment, the first insulating material and the second insulating material have a total thickness, and the second insulating material has a first thickness that is 15% to 45% of the total thickness. In one embodiment, the first insulating material has a second thickness that is greater than the first thickness. In one embodiment, the first thickness is in a range of approximately 50 nanometers to approximately 150 nanometers, and the second thickness is in a range of approximately 200 nanometers to approximately 300 nanometers. The method also includes: forming a sacrificial gate stack on the first portion of the first fin structure and the second fin structure, recessing the second portion of the first fin structure and the second fin structure, wherein the first compliant layer, the second compliant layer, the third compliant layer, the fourth compliant layer, and the first insulating material are recessed, and the second insulating material is removed during the recessing of the second portion of the first fin structure and the second fin structure.

[0094] An embodiment of the present invention further provides a method for forming a semiconductor device structure, the method comprising: forming a first fin structure and a second fin structure from a substrate; depositing a first compliant layer over the first fin structure and the second fin structure and between the first fin structure and the second fin structure; depositing a second compliant layer on the first compliant layer; depositing a third compliant layer on the second compliant layer; depositing a fourth compliant layer on the third compliant layer; depositing a first insulating material on the fourth compliant layer between the first fin structure and the second fin structure; and performing a first annealing process. The fourth compliant layer expands during the first annealing process and causes the density of the first compliant layer, the second compliant layer, and the third compliant layer to increase. The method further comprises: depositing a second insulating material on the first insulating material, with the first fin structure and the second fin structure being embedded by the second insulating material. The method also includes: removing portions of the second insulating material, the first compliant layer, the second compliant layer, the third compliant layer, and the fourth compliant layer to expose the tops of the first fin structure and the second fin structure, performing a second annealing process, and recessing the second insulating material, the first compliant layer, the second compliant layer, the third compliant layer, and the fourth compliant layer.

[0095] In one embodiment, the fourth compliant layer comprises a semiconductor. In one embodiment, the fourth compliant layer is oxidized by a first annealing process. In one embodiment, the third compliant layer comprises carbon, and during the first annealing process, the carbon diffuses into the first insulating material. In one embodiment, the second compliant layer comprises nitrogen, and during the first annealing process, the nitrogen diffuses into the first insulating material. The method further includes forming a sacrificial gate stack over a first portion of the first and second fin structures, forming a gate spacer, and recessing a second portion of the first and second fin structures, wherein the gate spacer, the first compliant layer, the second compliant layer, the third compliant layer, the fourth compliant layer, and the first insulating material are recessed, and the second insulating material is removed during the recessing of the second portion of the first and second fin structures. In one embodiment, the gate spacer is in contact with the first compliant layer. The method further includes depositing a semiconductor layer over the first and second fin structures and between the first and second fin structures, wherein the first compliant layer is deposited over the semiconductor layer. In one embodiment, the semiconductor layer is oxidized during the first annealing process.

[0096] An embodiment of the present invention further provides a semiconductor device structure, comprising: a first source / drain region disposed above a substrate, a first well portion disposed below the first source / drain region, a second source / drain region disposed above the substrate, a second well portion disposed below the second source / drain region, and an insulating structure disposed between the first well portion and the second well portion. The insulating structure comprises: an insulating material having a first height, a first compliant layer in contact with the insulating material, and the first compliant layer having a second height different from the first height. The insulating material further comprises: a second compliant layer in contact with the first compliant layer, and the second compliant layer having a third height different from the second height. The insulating material further comprises: a third compliant layer in contact with the second compliant layer, and the third compliant layer having a fourth height different from the third height.

[0097] The structure further includes a fourth compliant layer in contact with the third compliant layer, wherein the fourth compliant layer has a fifth height different from the third height. In one embodiment, the first compliant layer, the second compliant layer, the third compliant layer, and the fourth compliant layer each have a decreasing thickness as they move away from the substrate. In one embodiment, the first compliant layer comprises an oxide, the second compliant layer comprises carbon, and the third compliant layer comprises nitrogen.

[0098] The above summarizes the components of several embodiments so that those skilled in the art can more easily understand the concepts of the embodiments of the present invention. Those skilled in the art will understand that they can use the embodiments of the present invention as a basis to design or modify other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device structure, characterized in that: include: a first source / drain region disposed above a substrate; a first well portion, disposed below the first source / drain region; a second source / drain region disposed above the substrate; a second well portion, disposed below the second source / drain region; as well as an insulating structure disposed between the first well portion and the second well portion, the insulating structure comprising: an insulating material having a first height; a first compliant layer in contact with the insulating material, wherein the first compliant layer has a second height different from the first height; a second compliant layer in contact with the first compliant layer, wherein the second compliant layer has a third height different from the second height; and A third compliant layer contacts the second compliant layer, wherein the third compliant layer has a fourth height different from the third height.

2. The semiconductor device structure according to claim 1, wherein: The invention also includes a fourth compliance layer contacting the third compliance layer, wherein the fourth compliance layer has a fifth height different from the third height.

3. The semiconductor device structure according to claim 2, wherein: The first compliant layer, the second compliant layer, the third compliant layer, and the fourth compliant layer each have a decreasing thickness along a direction away from the substrate.

4. The semiconductor device structure according to claim 3, wherein: The thickness of the fourth compliant layer is in a range of 0.1 nm to 10 nm.

5. The semiconductor device structure according to claim 1 or 3, wherein: The thickness of the first compliant layer, the second compliant layer, and the third compliant layer is in a range of 0.1 nm to 5 nm.

6. The semiconductor device structure according to claim 1, wherein: The isolation structure is a shallow trench isolation.

7. The semiconductor device structure according to claim 1, wherein: The first well portion has a first top surface, and the top surface of the insulating structure is flush with the first top surface or is located below the first top surface.

8. The semiconductor device structure according to claim 1, wherein: The invention also includes a gate spacer contacting the insulating structure.

9. The semiconductor device structure according to claim 8, wherein: Also includes: a contact etch stop layer disposed over the first source / drain region, the second source / drain region, and the gate spacer; as well as An interlayer dielectric layer is disposed on the contact etch stop layer.

10. The semiconductor device structure according to claim 1, wherein: The device further comprises a semiconductor layer, which is disposed above the first well portion and the second well portion and located between the first well portion and the second well portion, wherein the insulating structure is disposed on the semiconductor layer.

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