Power distribution network single-phase earth fault detection and positioning device

Abstract

The utility model relates to a power distribution network single-phase earth fault detection and positioning device, which comprises a master station and at least two groups of detection units, each detection point is provided with one group of detection unit, each group of detection unit comprises a collection unit and three signal acquisition units, the signal acquisition units are used for collecting three-phase current signals, and the collection units are used for collecting the three-phase current signals. The collection units are used for collecting the three-phase current signals and performing data communication and data operation with the adjacent collection units; the main station is used for collecting data of each group of collection units; the signal acquisition unit comprises an acquisition seat, a semicircular buckle, a TMR magnetic sensitive chip and an acquisition unit circuit board. The collection unit comprises a second wireless radio frequency module, a processor module, a long-distance wireless communication module and a memory module. According to the utility model, the lead can be fixed in the measurement process, the installation is convenient, the measurement accuracy is further ensured, the risk of direct connection of the device on hardware can be avoided, the local fault section judgment is realized, and the communication and master station calculation pressure is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of single-phase grounding fault detection, and in particular to a single-phase grounding fault detection and positioning device for a distribution network. Background Art

[0002] Currently, the traditional method for locating single-phase ground faults involves adjusting loads or changing operating modes, shutting down each line one by one to find the faulty line. This method often results in power outages, causing significant inconvenience to people's daily lives and is prone to operational errors. Therefore, finding and locating ground faults promptly without interrupting power supply has become an urgent issue.

[0003] The principles of fault line selection technology are mainly categorized into harmonic methods, active component methods, methods based on perturbations, methods based on transient signals, and zero-sequence methods. The various devices developed based on these methods require measuring voltage, current, or power in the conductors, typically using current transformers, which presents numerous installation challenges. Existing segmented location technologies for single-phase grounding faults in distribution networks typically extract phase currents and synthesize zero-sequence currents in a concentrator. This zero-sequence current is then uploaded to a master station for centralized fault location determination. However, connecting three signal acquisition units in the same hardware circuit on overhead lines presents the risk of direct connection. Furthermore, after a fault occurs, all zero-sequence current fault waveforms must be uploaded to a master server for centralized analysis. This involves uploading sampled values from each terminal to the master server in real time for analysis. However, communication limitations often hinder efficiency. Due to communication system failures or delays and heavy load on the master server, single-phase grounding fault location remains inefficient. Summary of the Invention

[0004] The purpose of the utility model is to provide a single-phase grounding fault detection and positioning device for a distribution network, which can fix the conductor during the measurement process, facilitate installation while further ensuring the accuracy of the measurement, and at the same time avoid the risk of direct connection of the device on hardware, realize on-site fault section judgment, and reduce the communication and main station calculation pressure.

[0005] The technical solution adopted by the utility model is: a single-phase grounding fault detection and positioning device for a power distribution network, comprising a master station and at least two groups of detection units, wherein each detection point is provided with a group of detection units, and each group of detection units comprises a collection unit and three signal acquisition units, wherein the signal acquisition unit is used to collect three-phase current signals, and the collection unit is used to collect the current signals collected by the three signal acquisition units and perform data communication and data calculation with adjacent collection units; the master station is used to collect data from each group of collection units;

[0006] The signal acquisition unit includes an acquisition seat, a semicircular buckle, a TMR magnetic sensitive chip and an acquisition unit circuit board. The acquisition unit circuit board includes a high-speed acquisition module, a first wireless radio frequency module and a fault trigger module. The high-speed acquisition module includes a signal processing circuit, an A / D conversion module and an FPGA module. The signal processing circuit includes an amplification circuit and a filtering circuit. The semicircular buckle is detachably arranged at one end of the acquisition seat. A semicircular through hole is provided at the end where the acquisition seat is connected to the semicircular buckle. The semicircular through hole and the semicircular buckle constitute a wire accommodating cavity. A pair of clamping devices are provided in the wire accommodating cavity. The clamping device includes a support column and an elastic sheet, one end of the support column is connected to the elastic sheet, and the other end is connected to the acquisition seat or the semicircular buckle, and the two elastic sheets are arranged opposite each other; the TMR magnetic sensitive chip and the acquisition unit circuit board are arranged on the acquisition seat, and the signal output by the TMR magnetic sensitive chip is transmitted in two ways, one way is transmitted to the fault trigger module, and the other way is transmitted to the high-speed acquisition module; within the high-speed acquisition module, an amplification circuit, a filtering circuit, an A / D conversion module and an FPGA module are arranged in sequence along the signal transmission direction, and the FPGA module is also connected to the first wireless radio frequency module and the fault trigger module;

[0007] The aggregation unit includes a second wireless radio frequency module, a processor module, a long-distance wireless communication module and a memory module. The second wireless radio frequency module is data-connected to the first wireless radio frequency module and is used to transmit the current signal collected by the signal acquisition unit to the processor module. The processor module is also connected to the long-distance wireless communication module and the memory module. Data connections are established between the processor modules and between the processor modules and the master station through the long-distance wireless communication module.

[0008] Furthermore, the amplifier circuit includes a two-stage signal amplifier circuit and a voltage follower circuit. The input end of the first-stage signal amplifier circuit is connected to the TMR magnetic sensitive chip, and the output end is connected to the input end of the second-stage amplifier circuit. The output end of the second-stage amplifier circuit is connected to the input end of the filter circuit. The voltage follower circuit is connected to the first-stage signal amplifier circuit. The voltage follower circuit is used to eliminate the bias current of the first-stage signal amplifier circuit.

[0009] Furthermore, the first-stage signal amplification circuit includes a high-speed instrumentation amplifier and a first variable resistor, the input end of the high-speed instrumentation amplifier is connected to the differential signal output by the TMR magnetic sensitive chip and the first variable resistor; the second-stage amplification circuit includes a first operational amplifier, a second resistor, a third resistor and a third adjustment resistor, one end of the second resistor is connected to the output end of the high-speed instrumentation amplifier, and the other end is connected to the input end of the first operational amplifier, one end of the third resistor is connected to the input end of the first operational amplifier, and the other end is grounded, one end of the third adjustment resistor is connected to the output end of the high-speed instrumentation amplifier, and the other end is connected to the output end of the first operational amplifier; the voltage follower circuit includes a second operational amplifier, a first resistor and a second adjustable resistor, one end of the first resistor is connected in series with the second adjustable resistor, the input end of the second operational amplifier is connected to the series connection point of the first resistor and the second adjustable resistor, and the output end is connected to the output end of the high-speed instrumentation amplifier.

[0010] Furthermore, the filtering circuit is a second-order low-pass filtering circuit, including a third operational amplifier, a fourth resistor, a fifth resistor, a sixth resistor, a fourth adjustable resistor, a first capacitor and a second capacitor; one end of the fourth resistor is connected to the input end of the third operational amplifier, and the other end is grounded; after the fifth resistor and the sixth resistor are connected in series, one end is connected to the output end of the second-stage amplifier circuit, and the other end is connected to the input end of the third operational amplifier; one end of the second capacitor is connected to the fifth resistor, and the other end is grounded; one end of the fourth adjustable resistor is connected to the fourth resistor, and the other end is connected to the first capacitor; the first capacitor is also connected to the series point of the fifth resistor and the sixth resistor; the third operational amplifier, the fourth resistor, the fifth resistor, the fourth adjustable resistor and the second capacitor constitute a first-order low-pass Butterworth filter, and the sixth resistor and the first capacitor constitute an additional RC circuit connected to the first-order low-pass Butterworth filter to form a second-order low-pass filtering device.

[0011] Furthermore, the fault triggering module is a single chip microcomputer.

[0012] Furthermore, the processor module is a DSP chip, and the DSP chip is also provided with an external clock circuit, which is used to provide a clock source for the DSP chip, including a crystal oscillator, an 85th capacitor and an 86th capacitor, one end of the 85th capacitor and the 86th capacitor is grounded, and the other end is respectively connected to the crystal oscillator, and the crystal oscillator is also connected to the DSP chip.

[0013] Furthermore, the first wireless radio frequency module and the second wireless radio frequency module are Bluetooth modules.

[0014] The beneficial effects of the present invention are:

[0015] (1) The utility model uses a TMR magnetic sensitive chip to measure three-phase current signals in a non-contact manner. The conductor is fixed by a semicircular buckle and a clamping device, which is convenient for disassembly and assembly and stabilizes the position of the conductor during the measurement process, reducing the measurement error caused by the deviation of the conductor position, ensuring that the magnetic field direction of the conductor to be measured is parallel to the magnetic sensitive direction of the chip, and ensuring the accuracy of the measurement data. Since the utility model uses a non-contact method to measure the current signal, there is no need to cut off the power during the installation and detection process, which not only reduces the probability of misoperation, but also avoids a major impact on residents' lives.

[0016] (2) The utility model adopts wireless radio frequency technology to transmit three-phase current, avoiding the risk of direct connection of the device in hardware. The correlation of zero-sequence current is calculated by DSP chip to realize local fault section judgment, thereby reducing the pressure of communication and main station calculation. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 This is a schematic structural diagram of an embodiment of the present utility model;

[0019] Figure 2 This is a principle block diagram of a detection unit in an embodiment of the present utility model;

[0020] Figure 3 This is a structural diagram of a signal acquisition unit in an embodiment of the present utility model;

[0021] Figure 4 This is a circuit diagram of an amplifier circuit in an embodiment of the present utility model;

[0022] Figure 5 1 is a circuit diagram of a filter circuit in an embodiment of the present utility model;

[0023] Figure 6 This is a schematic diagram of the connection relationship between the A / D conversion module, the FPGA module, the first wireless radio frequency module and the fault trigger module in an embodiment of the present utility model;

[0024] Figure 7 This is a pin diagram of the fault trigger module in the embodiment of the present utility model;

[0025] Figure 8 This is a pin diagram of the A / D conversion module in an embodiment of the present utility model;

[0026] Figure 9This is a pin diagram of the FPGA module in the embodiment of the present utility model;

[0027] Figure 10 This is a pin diagram of the first wireless radio frequency module and the second wireless radio frequency module in the embodiment of the present invention;

[0028] Figure 11 This is a pin diagram of the processor module in the embodiment of the present invention;

[0029] Figure 12 This is a circuit diagram of an external clock circuit in an embodiment of the present utility model;

[0030] Figure 13 This is a pin diagram of the long-distance wireless communication module in the embodiment of the present utility model;

[0031] Figure 14 1 is a pin diagram of the memory module in an embodiment of the present invention.

[0032] Explanation of the accompanying numbers: 1-main station, 2-collection unit, 3-signal acquisition unit, 301-acquisition seat, 302-semicircular buckle, 303-TMR magnetic sensitive chip, 304-acquisition unit circuit board, 305-wire accommodating cavity, 306-support column, 307-elastic sheet, 308-wire. DETAILED DESCRIPTION

[0033] In order to more clearly understand the above-mentioned purposes, features and advantages of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can also be implemented in other ways different from those described herein. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0034] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field described in this application. "First", "second" and similar words used in this patent application specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, "one" or "an" and similar words do not indicate a quantity limitation, but rather indicate the existence of at least one. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship also changes accordingly.

[0035] like Figures 1 to 3As shown, a single-phase ground fault detection and location device for a distribution network includes a master station 1 and at least two groups of detection units, with one detection unit set at each detection point. Each detection unit group includes a collection unit 2 and three signal acquisition units 3. The signal acquisition unit 3 is used to collect three-phase current signals. The collection unit 2 is used to collect the current signals collected by the three signal acquisition units 3 and perform data communication and data calculations with adjacent collection units 2. The master station 1 is used to collect data from each group of collection units 2.

[0036] The signal acquisition unit 3 comprises an acquisition base 301, a semicircular buckle 302, a TMR magnetic sensing chip 303, and an acquisition unit circuit board 304. The acquisition unit circuit board 304 includes a high-speed acquisition module, a first wireless radio frequency module, and a fault trigger module. The high-speed acquisition module includes a signal processing circuit, an A / D conversion module, and an FPGA module. The signal processing circuit includes an amplifier circuit and a filter circuit. The semicircular buckle 302 is detachably mounted on one end of the acquisition base 301. The end of the acquisition base 301 connected to the semicircular buckle 302 is provided with a semicircular through hole. The semicircular through hole and the semicircular buckle 302 form a wire accommodating cavity 305. Because the positional deviation of the wire 308 has a significant impact on the measurement accuracy of the TMR magnetic sensing chip 303, a pair of clamping devices are provided within the wire accommodating cavity 305. These clamping devices are used to clamp and secure the wire 308, reduce measurement errors caused by the positional deviation of the wire 308, ensure that the magnetic field direction of the wire 308 is parallel to the magnetic sensing direction of the chip, and ensure the accuracy of the measurement data. The clamping device includes a support column 306 and an elastic sheet 307. One end of the support column 306 is connected to the elastic sheet 307, and the other end is connected to the collection base 301 or the semicircular buckle 302. The two elastic sheets 307 are arranged opposite each other and can accommodate wires 308 of varying thicknesses, thereby enhancing the practicality of this embodiment of the utility model. The TMR magnetic sensing chip 303 and the collection unit circuit board 304 are disposed on the collection base 301. The signal output by the TMR magnetic sensing chip 303 is transmitted in two paths: one path is transmitted to the fault trigger module, and the other path is transmitted to the high-speed collection module. Within the high-speed collection module, an amplification circuit, a filtering circuit, an A / D conversion module, and an FPGA module are sequentially arranged along the signal transmission direction. The FPGA module is also connected to the first wireless RF module and the fault trigger module.

[0037] The aggregation unit 2 includes a second wireless radio frequency module, a processor module, a long-distance wireless communication module and a memory module. The second wireless radio frequency module is data-connected to the first wireless radio frequency module and is used to transmit the current signal collected by the signal acquisition unit 3 to the processor module. The processor module is also connected to the long-distance wireless communication module and the memory module. Data connections are established between the processor modules and between the processor modules and the master station 1 through the long-distance wireless communication module.

[0038] In an embodiment of the present utility model, the amplifier circuit includes a two-stage signal amplifier circuit and a voltage follower circuit. The input end of the first-stage signal amplifier circuit is connected to the TMR magnetic sensitive chip 303, and the output end is connected to the input end of the second-stage amplifier circuit. The output end of the second-stage amplifier circuit is connected to the input end of the filter circuit. The voltage follower circuit is connected to the first-stage signal amplifier circuit. The voltage follower circuit is used to eliminate the bias current of the first-stage signal amplifier circuit.

[0039] like Figure 4As shown, the first-stage signal amplification circuit includes a high-speed instrumentation amplifier U1 and a first variable resistor RP1. The high-speed instrumentation amplifier U1 is an AD8421 high-speed instrumentation amplifier capable of amplifying high-frequency signals. The -IN and +IN pins of the high-speed instrumentation amplifier U1 are respectively connected to the differential signals Port1 and Port2 output by the TMR magnetic sensor chip 303. The two RG pins are connected to the first variable resistor RP1, which is used to adjust the amplification gain. To ensure signal accuracy and reduce signal deviation, the amplification factor of the first-stage signal amplification circuit should not be set too high. The signal needs to be amplified in a second stage by a second-stage amplifier circuit. The second-stage amplifier circuit includes a first operational amplifier U3, a second resistor R2, a third resistor R3, and a third adjustment resistor RP3. The first operational amplifier U3 is an AD847 operational amplifier. One end of the second resistor R2 is connected to the VOUT pin of the high-speed instrumentation amplifier U1, and the other end is connected to the -IN pin of the first operational amplifier U3. One end of the third resistor R3 is connected to the +IN pin of the first operational amplifier U1, and the other end is grounded. One end of the third adjustment resistor RP3 is connected to the VOUT pin of the high-speed instrumentation amplifier U1, and the other end is connected to the OUT pin of the first operational amplifier U3. The second resistor R2 is used to buffer the input signal, the third adjustment resistor RP3 serves as a feedback resistor for adjusting the gain, and the third resistor R3 serves as a balancing resistor for suppressing the offset voltage. To eliminate the bias current of the high-speed instrumentation amplifier U1, the embodiment of the utility model provides a voltage follower circuit, which includes the second operational amplifier U2, the first resistor R1, and the second adjustable resistor RP2. The second operational amplifier U2 also uses an AD847 operational amplifier. One end of the first resistor R1 is connected in series with the second adjustable resistor RP2. The +IN pin of the second operational amplifier U2 is connected to the series connection point of the first resistor R1 and the second adjustable resistor RP2. The -IN pin and the OUT pin are connected, and then connected to the REF pin of the high-speed instrumentation amplifier U1. The first resistor R1 and the second adjustable resistor RP2 are used for voltage regulation. The OUT pin of the first operational amplifier U3 outputs the amplified current signal Port3. The +VS pins of the high-speed instrumentation amplifier U1, the first operational amplifier U3, and the second operational amplifier U2, as well as the second adjustable resistor RP2, are connected to the positive electrode of the external power supply. The -VS pins of the high-speed instrumentation amplifier U1, the first operational amplifier U3, and the second operational amplifier U2, as well as the first resistor R1, are connected to the negative electrode of the external power supply. In an embodiment of the present invention, the output voltage of the external power supply is 9V.

[0040] like Figure 5As shown, the filter circuit is a second-order low-pass filter circuit, including a third operational amplifier U4, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a fourth adjustable resistor RP4, a first capacitor C1, and a second capacitor C2. The third operational amplifier U4 uses an AD847 operational amplifier. One end of the fourth resistor R4 is connected to the -IN pin of the third operational amplifier U4, and the other end is grounded. The fifth resistor R5 and the sixth resistor R6 are connected in series, and one end is connected to the amplified current signal Port3 output by the first operational amplifier U3, and the other end is connected to the +IN pin of the third operational amplifier U4. One end of the second capacitor C2 is connected to the fifth resistor R5 and the other end is grounded. One end of the fourth adjustable resistor RP4 is connected to the fourth resistor R4, and the other end is connected to the first capacitor C1. The first capacitor C1 is also connected to the series connection point of the fifth resistor R5 and the sixth resistor R6. The +VS pin of the third operational amplifier U4 is connected to the positive terminal of the external power supply, and the -VS pin is connected to the negative terminal of the external power supply. The third operational amplifier U4, the fourth resistor R4, the fifth resistor R5, the fourth adjustable resistor RP4 and the second capacitor C2 constitute a first-order low-pass Butterworth filter, the sixth resistor R6 and the first capacitor C1 constitute an additional RC circuit connected to the first-order low-pass Butterworth filter, forming a second-order low-pass filter. The OUT pin of the third operational amplifier U4 outputs the filtered current signal Port4.

[0041] like Figures 6 to 10As shown. In the embodiment of the utility model, the A / D conversion module adopts the AD9268 chip, the FPGA module adopts the EP4CE10E22C8N chip, the fault trigger module is a single-chip microcomputer, specifically the STM32F103C8T6 single-chip microcomputer, and the first wireless radio frequency module and the second wireless radio frequency module are both Bluetooth modules, specifically the JDY34 chip. The STM32F103C8T6 chip has two 12-bit A / D conversion modules and four 16-bit timers / counters. When no fault occurs, the filtered current signal Port4 output by the third operational amplifier U4 is transmitted to pin 33 of the single-chip microcomputer. Through programming and signal analysis of the single-chip microcomputer, when it is detected that the current signal Port4 is greater than 1.1 times the normal signal and lasts for a period of time, it is determined that a fault has occurred. The single-chip microcomputer is connected to pin 6 of the EP4CE10E22C8N chip via pin 22, and a pulse is sent to trigger the high-speed acquisition module. The analog input terminal of the AD9268 chip, pin 51, is connected to the filtered current signal Port 4 output by the third operational amplifier U4. When a fault occurs, the FPGA module triggers the A / D conversion module to digitize the filtered current signal Port 4. After processing by the FPGA module, it is converted into serial data and transmitted to the first wireless RF module via serial communication. Pin 1 of the EP4CE10E22C8N chip is connected to pin 43 of the AD9268 chip, and pins 10 and 13 of the EP4CE10E22C8N chip are connected to pins 2 and 1 of the first wireless RF module, respectively. The first and second wireless RF modules are paired to transmit the current signal from signal acquisition unit 3 to aggregation unit 2. Aggregation unit 2 is installed near signal acquisition unit 3, such as on a nearby utility pole. Aggregation unit 2 receives the three-phase current data collected by signal acquisition unit 3 via the second wireless RF module, synthesizes the three-phase current data into zero-sequence current data through the processor module, and stores the data in the memory module. The zero-sequence current data is transmitted to the adjacent collection unit 2 through the long-distance wireless communication module and the Pearson correlation of the zero-sequence current is calculated to locate the single-phase ground fault and transmit the positioning result to the master station 1.

[0042] like Figures 11 to 14As shown, the processor module is a DSP chip, and in the embodiment of the present utility model, a TMS320F28335 chip is used. The DSP chip is a unique microprocessor that processes large amounts of information using digital signals. It has powerful computing power and a high operating speed. Compared with single-chip microcomputers, it has great advantages in terms of real-time performance, reliability, instruction cycle, and execution rate, and is more suitable for applications that require processing large amounts of signals. The DSP chip is also provided with an external clock circuit, which is used to provide a clock source for the DSP chip. The circuit includes a crystal oscillator Y1, an 85th capacitor C85, and an 86th capacitor C86. One end of the 85th capacitor C85 and the 86th capacitor C86 are grounded, and the other end is respectively connected to the crystal oscillator Y1. The crystal oscillator Y1 is also connected to pins 102 and 104 of the DSP chip, and pin 105 of the DSP chip is grounded. The crystal oscillator Y1 is used to provide a clock signal, and the 85th capacitor C85 and the 86th capacitor C86 are used to ensure the normal operation of the clock circuit. Pins 1 and 2 of the second wireless RF module are connected to pins 141 and 2 of the TMS320F28335 chip, respectively, for serial communication. The long-distance wireless communication module is implemented using the E22-400M22S chip. Pins 16 and 17 of the E22-400M22S chip serve as the device input and device output pins, respectively, and are connected to pins 96 and 97 of the TMS320F28335 chip for serial communication. Pins 18 and 19 of the E22-400M22S chip serve as the serial clock and chip select pins, respectively, and are connected to pins 98 and 99 of the TMS320F28335 chip. The memory module uses a 32GB Micro SD card and is connected to resistors R24, R25, R26, and R27. One end of resistors R24, R25, R26, and R27 is connected to pins 7, 5, 2, and 1 of the memory module, respectively. The other ends are connected to the positive terminals of the corresponding external power supplies. Pins 7 and 2 of the memory module are input and output pins, respectively, and are connected to pins 96 and 97 of the TMS320F28335 chip to implement serial communication. Pins 5 and 1 are connected to pins 98 and 145 of the TMS320F28335 chip, respectively, for serial clock and chip select.

[0043] The operating principle of the present embodiment is as follows: In a low-current grounding system, an appropriate number of detection points are selected at appropriate intervals based on actual conditions. At each detection point, three signal acquisition units 3 are installed on each phase conductor 308, and the corresponding aggregation unit 2 is installed near the signal acquisition unit 3. The TMR magnetic sensor chip 303 collects current data from the conductor 308 at a low speed. When the fault trigger module detects that the current value exceeds 1.1 times the normal current value, the timing module activates the timing module. When the timing module reaches the set time, a pulse is generated, activating the high-speed acquisition module. The FPGA module collects transient current at high speed and transmits the collected data to the aggregation unit 2 via the first and second wireless RF modules. The aggregation unit 2 receives the three-phase current data collected by the signal acquisition unit 3 via the second wireless RF module, and synthesizes the three-phase current data into zero-sequence current data using the processor module, storing the data in the memory module. The zero-sequence current data is obtained by adding the three-phase current data and dividing it by three. However, directly connecting the three signal acquisition units 3 on the transmission line through hardware poses a risk of direct connection, which can reduce the safety of the entire power system. Therefore, the present invention achieves current signal aggregation through wireless transmission. The adjacent aggregation unit 2 communicates data through the long-distance wireless communication module and performs data operations to calculate the Pearson correlation coefficient of the zero-sequence current at the two detection points. When the Pearson correlation coefficient is less than 0.4, it is determined that the fault point is located between the corresponding two detection points, thereby locating the single-phase grounding fault and transmitting the positioning result to the master station 1, reducing the pressure on communication and master station calculation.

[0044] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A single-phase ground fault detection and positioning device for a distribution network, characterized in that: It includes a master station and at least two groups of detection units. Each detection point is provided with a group of detection units. Each group of detection units includes a collection unit and three signal acquisition units. The signal acquisition unit is used to collect three-phase current signals. The collection unit is used to collect the current signals collected by the three signal acquisition units and perform data communication and data calculation with adjacent collection units. The master station is used to collect data from each group of collection units. The signal acquisition unit includes an acquisition seat, a semicircular buckle, a TMR magnetic sensitive chip and an acquisition unit circuit board. The acquisition unit circuit board includes a high-speed acquisition module, a first wireless radio frequency module and a fault trigger module. The high-speed acquisition module includes a signal processing circuit, an A / D conversion module and an FPGA module. The signal processing circuit includes an amplification circuit and a filtering circuit. The semicircular buckle is detachably arranged at one end of the acquisition seat. A semicircular through hole is provided at the end where the acquisition seat is connected to the semicircular buckle. The semicircular through hole and the semicircular buckle constitute a wire accommodating cavity. A pair of clamping devices are provided in the wire accommodating cavity. The clamping device includes a support column and an elastic sheet, one end of the support column is connected to the elastic sheet, and the other end is connected to the acquisition seat or the semicircular buckle, and the two elastic sheets are arranged opposite each other; the TMR magnetic sensitive chip and the acquisition unit circuit board are arranged on the acquisition seat, and the signal output by the TMR magnetic sensitive chip is transmitted in two ways, one way is transmitted to the fault trigger module, and the other way is transmitted to the high-speed acquisition module; within the high-speed acquisition module, an amplification circuit, a filtering circuit, an A / D conversion module and an FPGA module are arranged in sequence along the signal transmission direction, and the FPGA module is also connected to the first wireless radio frequency module and the fault trigger module; The aggregation unit includes a second wireless radio frequency module, a processor module, a long-distance wireless communication module and a memory module. The second wireless radio frequency module is data-connected to the first wireless radio frequency module and is used to transmit the current signal collected by the signal acquisition unit to the processor module. The processor module is also connected to the long-distance wireless communication module and the memory module. Data connections are established between the processor modules and between the processor modules and the master station through the long-distance wireless communication module.

2. A single-phase grounding fault detection and positioning device for a power distribution network according to claim 1, characterized in that: The amplifier circuit includes a two-stage signal amplifier circuit and a voltage follower circuit. The input end of the first-stage signal amplifier circuit is connected to the TMR magnetic sensitive chip, and the output end is connected to the input end of the second-stage amplifier circuit. The output end of the second-stage amplifier circuit is connected to the input end of the filter circuit. The voltage follower circuit is connected to the first-stage signal amplifier circuit. The voltage follower circuit is used to eliminate the bias current of the first-stage signal amplifier circuit.

3. A single-phase grounding fault detection and positioning device for a power distribution network according to claim 2, characterized in that: The first-stage signal amplification circuit includes a high-speed instrumentation amplifier and a first variable resistor, wherein the input end of the high-speed instrumentation amplifier is connected to the differential signal output by the TMR magnetic sensitive chip and the first variable resistor; the second-stage amplification circuit includes a first operational amplifier, a second resistor, a third resistor and a third adjustment resistor, wherein one end of the second resistor is connected to the output end of the high-speed instrumentation amplifier and the other end is connected to the input end of the first operational amplifier; one end of the third resistor is connected to the input end of the first operational amplifier and the other end is grounded; one end of the third adjustment resistor is connected to the output end of the high-speed instrumentation amplifier and the other end is connected to the output end of the first operational amplifier; the voltage follower circuit includes a second operational amplifier, a first resistor and a second adjustable resistor, one end of the first resistor is connected in series with the second adjustable resistor, the input end of the second operational amplifier is connected to the series connection point of the first resistor and the second adjustable resistor, and the output end is connected to the output end of the high-speed instrumentation amplifier.

4. A single-phase grounding fault detection and positioning device for a power distribution network according to claim 3, characterized in that: The filtering circuit is a second-order low-pass filtering circuit, including a third operational amplifier, a fourth resistor, a fifth resistor, a sixth resistor, a fourth adjustable resistor, a first capacitor, and a second capacitor; one end of the fourth resistor is connected to the input end of the third operational amplifier, and the other end is grounded; the fifth resistor and the sixth resistor are connected in series, and one end is connected to the output end of the second-stage amplifier circuit, and the other end is connected to the input end of the third operational amplifier; one end of the second capacitor is connected to the fifth resistor, and the other end is grounded; one end of the fourth adjustable resistor is connected to the fourth resistor, and the other end is connected to the first capacitor; the first capacitor is also connected to the series connection point of the fifth resistor and the sixth resistor; the third operational amplifier, the fourth resistor, the fifth resistor, the fourth adjustable resistor, the second capacitor constitute a first-order low-pass Butterworth filter; the sixth resistor and the first capacitor constitute an additional RC circuit connected to the first-order low-pass Butterworth filter, forming a second-order low-pass filtering device.

5. A single-phase grounding fault detection and positioning device for a power distribution network according to claim 4, characterized in that: The fault trigger module is a single chip microcomputer.

6. A single-phase grounding fault detection and positioning device for a power distribution network according to claim 5, characterized in that: The processor module is a DSP chip, which is also provided with an external clock circuit. The external clock circuit is used to provide a clock source for the DSP chip, including a crystal oscillator, an 85th capacitor and an 86th capacitor. One end of the 85th capacitor and the 86th capacitor are grounded, and the other end is respectively connected to the crystal oscillator, and the crystal oscillator is also connected to the DSP chip.

7. A single-phase grounding fault detection and positioning device for a power distribution network according to claim 6, characterized in that: The first wireless radio frequency module and the second wireless radio frequency module are Bluetooth modules.

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