Double-sided packaging hybrid chip structure of through hole substrate
By stacking multi-layer chips on the front and back of the substrate and using the double-sided packaging structure of the through-hole substrate, a high-performance, high-density, and miniaturized memory chip packaging is achieved, which solves the problems of packaging complexity and cost in the prior art and improves the packaging reliability.
Patent Information
- Application Number
- CN202422489687.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-15
- Publication Date
- 2025-08-12
- Estimated Expiration
- 2034-10-15
AI Technical Summary
The existing memory chip packaging technology is difficult to meet the needs of modern electronic products for high performance, high density and miniaturization. At the same time, the manufacturing process is complex and costly, which affects product reliability.
A double-sided packaged hybrid chip structure adopts a through-hole substrate. By stacking multi-layer chips on both sides of the substrate, and using the through-holes of the substrate to achieve simultaneous plastic sealing on both sides of the substrate during the plastic packaging process, combining conductive columns and re-wiring layers to achieve interconnection of multiple chips, simplifying the manufacturing process.
It realizes high integration and miniaturization of chip packaging, reduces manufacturing costs, improves packaging reliability, and meets the performance and density requirements of modern electronic products.
Smart Images
Figure CN223218304U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor packaging, and more particularly to a double-sided packaging hybrid chip structure of a through-hole substrate. Background Art
[0002] Memory chip packaging technology is a crucial component in semiconductor integrated circuit manufacturing. Traditional memory chip packaging relies on a stacked, wire-bonded structure. While simple and easy to implement, its limited design makes it unable to meet the high-performance, high-density, and miniaturized demands of modern electronic products.
[0003] To address this issue, new packaging technologies have been proposed and applied, such as increasing storage capacity by increasing the number of chip stacking layers or improving wire bonding structures to increase data transmission speeds. However, these methods often increase manufacturing costs and may also affect product reliability.
[0004] While existing packaging technologies have improved memory chip performance to some extent, their structural types remain relatively simple. Furthermore, the use of wire bonds in multi-layer chips limits wire density, which in turn restricts product communication speeds and fails to meet the demands of modern electronic products for high performance, high density, and miniaturization. Furthermore, existing packaging technologies often require complex manufacturing processes, which not only increases manufacturing costs but also potentially impacts product reliability.
[0005] Therefore, how to design a new memory chip packaging structure to meet the needs of modern electronic products is an urgent problem to be solved in the current semiconductor integrated circuit manufacturing field. Utility Model Content
[0006] In order to solve the above problems, the utility model provides a double-sided packaged hybrid chip structure of a through-hole substrate, which has higher integration and smaller volume. It can complete the double-sided plastic sealing of the substrate at one time, reduce manufacturing costs, improve packaging reliability, and meet the needs of modern electronic products for high performance, high density and miniaturization.
[0007] According to one aspect of the present invention, a double-sided package hybrid chip structure of a through-hole substrate is provided, comprising:
[0008] A substrate having a front side and a back side facing opposite directions, a metal post provided in the substrate for conducting electricity between the two sides of the substrate, and a through hole extending through the substrate, the through hole being used to provide a flow channel for melted molding compound during the molding process, thereby achieving simultaneous molding of both sides of the substrate;
[0009] A front chip, wherein the front chip is mounted on the front side of the substrate;
[0010] A back chip, the back chip being mounted on the back side of the substrate;
[0011] A first plastic encapsulation layer, located on the front side of the substrate and wrapping the front chip;
[0012] A second plastic sealing layer, located on the back side of the substrate and wrapping the back side chip;
[0013] A first redistribution layer, the first redistribution layer being located on a surface of the first plastic packaging layer;
[0014] A second redistribution layer, the second redistribution layer being located on the surface of the second plastic packaging layer;
[0015] Among them, the plastic encapsulation layer 1 and the plastic encapsulation layer 2 are formed simultaneously by filling the plastic encapsulation material on one side of the substrate and the plastic encapsulation material flows to the other side of the substrate through the through holes of the substrate. Conductive columns are provided in the plastic encapsulation layer 1 and the plastic encapsulation layer 2, and the conductive columns are interconnected with the metal columns of the substrate. The circuits of the substrate are led out to the surfaces of the plastic encapsulation layer 1 and the plastic encapsulation layer 2 through the conductive columns.
[0016] In some embodiments, the front chip includes chip one and chip two, chip one is mounted on the front of the substrate, chip two is mounted on the surface of chip one, the surface of chip one has a metal pad, a wire is bonded between the front of the substrate and the metal pad of chip one to form wire bond one, the surface of chip two has chip bumps, and the chip bumps of chip two are interconnected with the lines of redistribution layer one.
[0017] In some embodiments, the back chip includes chip three and chip four, chip three is mounted on the back of the substrate, chip four is mounted on the surface of chip three, the surface of chip three has a metal pad, a wire is bonded between the back of the substrate and the metal pad of chip three to form wire bond two, the surface of chip four has chip bumps, and the chip bumps of chip four are interconnected with the lines of the redistribution layer two.
[0018] In some embodiments, solder balls are implanted on the surface of the second redistribution layer, and the diameter of the solder balls is 120-300 μm.
[0019] In some embodiments, the metal pillar is vertically disposed through the substrate.
[0020] In some embodiments, the conductive pillars in the first plastic encapsulation layer and the second plastic encapsulation layer are copper pillars formed by electroplating copper or conductive glue pillars formed by injecting conductive glue.
[0021] In some embodiments, the conductive pillars have a diameter of 100-200 μm.
[0022] In some embodiments, the diameter of the chip bumps on the surfaces of chip two and chip four is 40-100 μm and the pitch is 80-200 μm.
[0023] In some embodiments, the number of circuit layers of the redistribution layer 1 and the redistribution layer 2 is 2 to 6, the line width is 2 to 20 μm, and the line spacing is 2 to 20 μm.
[0024] Compared with the prior art, the beneficial effects of the present invention are:
[0025] (1) The present invention proposes a novel chip packaging structure. By stacking multiple layers of chips on both the front and back sides of a substrate and fabricating an RDL (ReDistribution Layer) layer on the surface of the plastic package, the upper chip bumps are interconnected with the RDL, the lower chip is interconnected with the substrate, and the substrate and RDL are interconnected through conductive pillars. Ultimately, an overall interconnection structure is achieved between multiple chips on the front and back sides, thereby stabilizing chip reliability while also improving the I / O density of the memory chip. This structure not only meets the high performance, high density, and miniaturization requirements of modern electronic products, but also has a higher degree of integration and a smaller size than the traditional upright stacking + wire bonding structure.
[0026] (2) The manufacturing process is simplified. The packaging process of the utility model mainly includes the steps of stacking chips, plastic sealing, making conductive pillars, grinding and thinning, making RDL layers and planting solder balls. Among them, the plastic sealing can complete the plastic sealing material filling on both sides of the substrate in just one time. These steps are relatively simple and easy to perform, which greatly reduces the manufacturing cost.
[0027] (3) The chip packaging structure proposed in this utility model can be applied not only to memory chips but also to other types of semiconductor integrated circuits, thus possessing broad application prospects. In the future, as electronic products increasingly demand higher performance, density, and size, the packaging structure described in this utility model is expected to become a mainstream packaging method. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 It is a schematic diagram of the packaging process of attaching the front chip and the back chip to the substrate;
[0029] Figure 2 This is a schematic diagram of the packaging process of wiring on the front and back sides of the substrate and plastic sealing;
[0030] Figure 3 It is a schematic diagram of the packaging process of making and thinning the plastic sealing layer and the conductive pillars in the plastic sealing layer;
[0031] Figure 4 This is a schematic diagram of the production process of redistribution layer 1 and redistribution layer 2, as well as the packaging process of solder ball planting;
[0032] Figure 5 It is a structural schematic diagram of an embodiment of a double-sided packaged hybrid chip structure of a through-hole substrate of the present invention.
[0033] Explanation of the accompanying drawings: 1-substrate, 11-metal pillar, 12-through hole, 2-front chip, 21-chip one, 22-chip two, welding wire one 211, 212-metal welding pad of chip one, 221-chip bump of chip two, 3-back chip, 31-chip three, 32-chip four, 311 welding wire two, 312-metal welding pad of chip three, 321-chip bump of chip four, 4-plastic layer one, 5-plastic layer two, 6-conductive pillar, 60-laser hole, 7-rewiring layer one, 8-rewiring layer two, 81-tin ball. DETAILED DESCRIPTION
[0034] The present invention will be further described below in conjunction with specific implementation methods.
[0035] like Figure 5 As shown, a double-sided packaged hybrid chip structure of a through-hole substrate in one embodiment of the present invention includes a substrate 1, a front chip 2, a back chip 3, a redistribution layer 7 and a second redistribution layer 8. The substrate 1 has a front and a back facing opposite directions. The front and back of the substrate 1 are used to install electronic components such as chips. The front chip 2 and the back chip 3 are respectively mounted on the front and back of the substrate 1. There are metal circuits on the surface and inside of the substrate 1, and some areas have vertical metal columns 11 for conducting the two sides of the substrate 1. The substrate 1 is provided with a through hole 12 that passes through the substrate 1. The through hole 12 is used to provide a flow channel for the melted plastic encapsulation material during the plastic encapsulation process, so as to achieve simultaneous plastic encapsulation of both sides of the substrate 1. After mounting the front and back chips 3, the substrate 1 is plastic-encapsulated. Plastic encapsulation layer 1 4 and plastic encapsulation layer 2 5 are simultaneously formed by filling one side of the substrate 1 with plastic encapsulation material and allowing the plastic encapsulation material to flow through the through-holes 12 of the substrate 1 to the other side of the substrate 1. Plastic encapsulation layer 1 4 is located on the front side of the substrate 1 and wraps the front chip 2, while plastic encapsulation layer 2 5 is located on the back side of the substrate 1 and wraps the back chip 3. Both plastic encapsulation layer 1 4 and plastic encapsulation layer 2 5 contain conductive pillars 6, which are interconnected with the metal pillars 11 of the substrate 1. Through the conductive pillars 6, the circuits of the substrate 1 are led out to the surfaces of plastic encapsulation layer 1 4 and plastic encapsulation layer 2 5. A redistribution layer 1 7 is fabricated on the surface of plastic encapsulation layer 1 4, and a redistribution layer 2 8 is fabricated on the surface of plastic encapsulation layer 2 5. Redistribution layers 1 7 and 2 8 are interconnected with the conductive pillars 6, the front chip 2, and the back chip 3. Depending on product requirements, solder balls 81 may be implanted on the surface of redistribution layer 2 8.
[0036] The front chip 2 includes chip 1 21 and chip 2 22. Chip 1 21 is mounted on the front surface of substrate 1, while chip 2 22 is mounted on the surface of chip 1 21. Both chip 1 21 and substrate 1, and chip 2 22 and chip 1 21, can be soldered using DAF or silver glue. Chip 1 21 has metal pads 212 around its surface. Wire bonds 211 are formed between the front surface of substrate 1 and the metal pads 212 of chip 1 21. Chip 2 22 has bumps 221 on its surface, interconnecting these bumps 221 with the circuitry of redistribution layer 1 7.
[0037] Backside chip 3 includes chip 3 31 and chip 4 32. Chip 3 31 is mounted on the backside of substrate 1, while chip 4 32 is mounted on the topside of chip 3 31. Both chip 3 31 and substrate 1, and chip 4 32 and chip 3 31, can be soldered using DAF or silver glue. Chip 3 31 has metal pads 312 around its surface. Wire bonds 311 are formed between the backside of substrate 1 and the metal pads 312 of chip 3 31. Chip 4 32 has bumps 321 on its surface, interconnecting with the traces of redistribution layer 2 8.
[0038] The conductive pillars 6 in the first and second plastic encapsulation layers 4 and 5 are formed by first drilling holes and then electroplating copper to form copper pillars, or by injecting conductive adhesive. The diameter of the conductive pillars 6 is 100-200 μm.
[0039] Combine Figures 1 to 4 , specifically describing the packaging process of the double-sided packaged hybrid chip structure of the through-hole substrate described in this application, the steps are as follows:
[0040] Step 1: If Figure 1 As shown in Figure 1A, a substrate 1 with a thickness of 200 to 400 μm is prepared. Metal circuits are provided on the surface and inside of the substrate 1, and vertical metal columns 11 are provided in some areas. Through holes 12 are processed on the substrate 1, and the through holes 12 are reserved to provide a flow channel for the melted molding compound in the subsequent molding process.
[0041] Step 2: Mount the chip 21 on the front of the substrate 1. A metal pad 212 for wire bonding is provided around the chip 21. The chip 21 and the substrate 1 are bonded using DAF glue or silver glue. Figure 1 As shown in Figure 1B.
[0042] Step 3: If Figure 1 As shown in Figure 1C, chip 2 22 is mounted on the surface of chip 1 21, and the two are welded using DAF glue or silver glue. Chip bumps 221 are provided on the surface of chip 2 22, and the diameter of the chip bumps 221 is 40 to 100 μm and the spacing is 80 to 200 μm.
[0043] Step 4: Mount the chip 31 on the back of the substrate 1. A metal pad 312 for wire bonding is provided around the chip 31. The chip 31 and the substrate 1 are bonded with DAF glue or silver glue. Figure 1 As shown in Figure 1D.
[0044] Step 5: If Figure 1 As shown in Figure 1E, chip four 32 is mounted on the surface of chip three 31, and the two are welded using DAF glue or silver glue. Chip bumps 321 are provided on the surface of chip four 32, and the diameter of chip bumps 321 is 40 to 100 μm and the spacing is 80 to 200 μm.
[0045] Step 6: Bond wires between the front surface of the substrate 1 and the metal pad 212 of the chip 1 21, forming a bonding wire 1 211, so as to complete the electrical connection between the chip and the substrate 1. Figure 2 As shown in 1F.
[0046] Step 7: Bond wire 2 311 between the back of substrate 1 and the metal pad 312 of chip 31, so as to complete the electrical connection between chip and substrate 1. Figure 2 As shown in Figure 1G.
[0047] Step 8: Use epoxy resin to perform plastic encapsulation on the front side of substrate 1. At the same time, the melted plastic encapsulation material flows through the through hole 12 of substrate 1 to the back side of substrate 1, thereby achieving plastic encapsulation of both the front and back sides of substrate 1. The plastic encapsulation body needs to cover all the chips and bonding wires on the front and back sides respectively, that is, forming plastic encapsulation layer 1 4 and plastic encapsulation layer 2 5. Figure 2 As shown in 1H.
[0048] Step 9: If Figure 3 As shown in FIG1I , laser drilling is performed on the front and back plastic packaging bodies, namely the plastic packaging layer 1 4 and the plastic packaging layer 2 5 . The laser hole 60 is connected to the internal circuit of the substrate 1 and the hole diameter is 100 to 200 μm.
[0049] Step 10: Fill the laser hole 60 with metal (e.g. copper) through electroplating process to form a metal copper column (i.e. conductive column 6), and lead the circuit of substrate 1 to the surface of plastic package through the copper column. Alternatively, conductive glue or other materials can be injected into the laser hole 60 through filling process, such as Figure 3 As shown in Figure 1J.
[0050] Step 11: Grind and thin the front and back surfaces of the plastic package body, that is, the surface of the plastic package layer 1 4 and the plastic package layer 2 5, so that the chip bumps of the chip 2 22 and the chip 4 32 are exposed. Figure 3 As shown in 1K.
[0051] Step 12: Figure 4As shown in Figure 1L, an RDL layer (i.e., redistribution layer 7) is fabricated on the surface of the plastic layer 4, interconnecting the chip bumps 221 with the RDL layer. The redistribution layer 7 has 2 to 6 circuit layers, a line width of 2 to 20 μm, and a line spacing of 2 to 20 μm.
[0052] Step 13: If Figure 4 As shown in FIG1M , an RDL layer (i.e., redistribution layer 8) is fabricated on the surface of the second plastic layer 5, interconnecting the chip bumps 321 with the RDL layer. The second redistribution layer 8 has 2 to 6 circuit layers, a line width of 2 to 20 μm, and a line spacing of 2 to 20 μm.
[0053] Step 14: Plant solder balls 81 on the surface of the second redistribution layer 8. The diameter of the solder balls 81 is 120 to 300 μm. Figure 4 As shown in 1N.
[0054] The chip packaging structure described in the present invention realizes the interconnection between the chip bumps on the upper layer and the RDL, and the interconnection between the chip on the lower layer and the substrate 1, and then the substrate 1 and the RDL are interconnected through the conductive pillars 6, finally realizing the overall interconnection structure between the multiple chips on the front and back sides, thereby stabilizing the chip reliability while also improving the I / O density of the memory chip.
[0055] The manufacturing process is relatively simplified, mainly including the steps of chip stacking, plastic encapsulation, making conductive pillars 6, thinning the wafer, making RDL layers and planting solder balls 81. Among them, the plastic encapsulation can complete the plastic encapsulation material filling on both sides of the substrate 1 in just one time, which greatly reduces the manufacturing cost and increases the reliability of the package.
[0056] The chip packaging structure proposed in this utility model can be applied not only to memory chips but also to other types of semiconductor integrated circuits. This packaging structure not only meets the high-performance, high-density, and miniaturized demands of modern electronic products, but also offers higher integration and a smaller footprint than the traditional upright stacking and wire bonding structure, thus offering broad application prospects.
[0057] The above are only some embodiments of the present invention. It should be pointed out that for ordinary technicians in this field, other variations and improvements can be made without departing from the creative concept of the present invention, and these all fall within the scope of protection of the present invention.
Claims
1. A double-sided package hybrid chip structure of a through-hole substrate, characterized in that: include: A substrate (1), the substrate (1) having a front side and a back side facing opposite directions, a metal column (11) provided in the substrate (1) for conducting the two sides of the substrate (1), the substrate (1) being provided with a through hole (12) penetrating the substrate (1), the through hole (12) being used to provide a flow channel for melted molding compound during the molding process, so as to achieve simultaneous molding of both sides of the substrate (1); A front chip (2), wherein the front chip (2) is mounted on the front side of the substrate (1); A back chip (3), the back chip (3) being mounted on the back side of the substrate (1); A plastic encapsulation layer (4), the plastic encapsulation layer (4) being located on the front surface of the substrate (1) and wrapping the front chip (2); A second plastic sealing layer (5), the second plastic sealing layer (5) being located on the back side of the substrate (1) and wrapping the back side chip (3); A redistribution layer (7), wherein the redistribution layer (7) is located on the surface of the plastic packaging layer (4); A second redistribution layer (8), the second redistribution layer (8) being located on the surface of the second plastic packaging layer (5); The first plastic encapsulation layer (4) and the second plastic encapsulation layer (5) are formed simultaneously by filling a plastic encapsulation material on one side of the substrate (1) and the plastic encapsulation material flows to the other side of the substrate (1) through the through hole (12) of the substrate (1); the first plastic encapsulation layer (4) and the second plastic encapsulation layer (5) are both provided with conductive columns (6); the conductive columns (6) are interconnected with the metal columns (11) of the substrate (1); and the circuits of the substrate (1) are led out to the surfaces of the first plastic encapsulation layer (4) and the second plastic encapsulation layer (5) through the conductive columns (6).
2. The double-sided package hybrid chip structure of the through-hole substrate according to claim 1, characterized in that: The front chip (2) includes chip one (21) and chip two (22), wherein chip one (21) is mounted on the front of the substrate (1), and chip two (22) is mounted on the surface of chip one (21), wherein the surface of chip one (21) has a metal pad, and wire bonding is formed between the front of the substrate (1) and the metal pad of chip one (21), and the surface of chip two (22) has chip bumps, and the chip bumps of chip two (22) are interconnected with the circuits of the redistribution layer one (7).
3. The double-sided package hybrid chip structure of the through-hole substrate according to claim 2, characterized in that: The back chip (3) includes a chip three (31) and a chip four (32), wherein the chip three (31) is mounted on the back of the substrate (1), and the chip four (32) is mounted on the surface of the chip three (31), wherein the surface of the chip three (31) has a metal pad, and a wire is bonded between the back of the substrate (1) and the metal pad of the chip three (31) to form a wire bond two (311), and the surface of the chip four (32) has a chip bump, and the chip bump of the chip four (32) is interconnected with the circuit of the redistribution layer two (8).
4. The double-sided packaged hybrid chip structure of the through-hole substrate according to claim 1 or 3, characterized in that: The surface of the second redistribution layer (8) is planted with solder balls (81), and the diameter of the solder balls (81) is 120 to 300 μm.
5. The double-sided package hybrid chip structure of the through-hole substrate according to claim 1, characterized in that: The metal column (11) is vertically penetrated in the substrate (1).
6. The double-sided package hybrid chip structure of the through-hole substrate according to claim 1, characterized in that: The conductive pillars (6) in the first plastic sealing layer (4) and the second plastic sealing layer (5) are copper pillars formed by electroplating copper or conductive glue pillars formed by injecting conductive glue.
7. The double-sided package hybrid chip structure of the through-hole substrate according to claim 6, characterized in that: The diameter of the conductive column (6) is 100-200 μm.
8. The double-sided package hybrid chip structure of the through-hole substrate according to claim 3, characterized in that: The diameter of the chip bumps on the surface of the chip 2 (22) and the chip 4 (32) is 40 to 100 μm, and the spacing is 80 to 200 μm.
9. The double-sided package hybrid chip structure of the through-hole substrate according to claim 1, characterized in that: The number of circuit layers of the redistribution layer 1 (7) and the redistribution layer 2 (8) is 2 to 6, the line width is 2 to 20 μm, and the line spacing is 2 to 20 μm.