Low-capacitance ESD chip with good protection effect

Abstract

The utility model relates to the technical field of electronic science, in particular to a low-capacitance ESD (Electro-Static Discharge) chip with a good protection effect, which comprises a first branch, a second branch and a third branch, the first branch is arranged between the second branch and the third branch, and the second branch and the third branch are provided with deep isolation grooves relative to the first branch; the first branch sequentially comprises an SN layer, an N-epi layer and a P-sub layer from top to bottom, the N-epi layer wraps the periphery of the SN layer, and the end face, away from the SN layer, of the N-epi layer is connected to the P-sub layer; the second branch and the third branch are the same in structure, the second branch sequentially comprises an SP layer, an N-epi layer, a BN layer and a P-sub layer from top to bottom, and the deep isolation groove wraps the second branch and the third branch. The utility model aims to improve the protection effect of the ESD chip.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic science, in particular to a low-capacitance ESD chip with good protection effect. Background Art

[0002] Electrostatic discharge (ESD) is a widespread phenomenon in everyday life. It poses a fatal threat to precision integrated circuits. Integrated circuits are highly susceptible to ESD during production, manufacturing, assembly, and operation, causing internal damage and reduced reliability. Therefore, research into high-performance, high-reliability ESD protection devices is crucial to improving the yield and reliability of integrated circuits.

[0003] In related technologies, the lateral structure of low-capacitance SCR devices often requires a larger ESD protection device while maintaining the same line width. However, reducing the device size by reducing the lateral structure would reduce the SCR device's area-related current carrying capacity. This means that currently, low-capacitance SCR-structured high-flyback ESD protection devices are difficult to implement in smaller device packages. Utility Model Content

[0004] The main purpose of the utility model is to provide a low-capacitance ESD chip with good protection effect, aiming to improve the protection effect of the ESD chip.

[0005] To achieve the above objectives, the present invention provides a low-capacitance ESD chip with excellent protection, characterized in that it includes a first branch, a second branch, and a third branch, wherein the first branch is located between the second branch and the third branch, and the second branch and the third branch are provided with a deep isolation trench relative to the first branch;

[0006] The first branch includes, from top to bottom, an SN layer, an N-epi layer, and a P-sub layer, wherein the N-epi layer surrounds the periphery of the SN layer, and an end surface of the N-epi layer away from the SN layer is connected to the P-sub layer;

[0007] The second branch and the third branch have the same structure. The second branch includes an SP layer, an N-epi layer, a BN layer and a P-sub layer from top to bottom. The deep isolation trench surrounds the second branch and the third branch.

[0008] In one embodiment of the present application, the N-epi layer is wrapped around the SP layer. The SP layer and the SN layer are connected to the same side end surface of the N-epi layer and are evenly spaced. The end surface of the N-epi layer away from the SP layer is connected to the BN layer, and the end surface of the BN layer away from the N-epi layer is connected to the P-sub layer.

[0009] In one embodiment of the present application, one end of the deep isolation trench is connected to the outer edge of the N-epi layer and passes through the N-epi layer, and one end of the deep isolation trench away from the N-epi layer passes through the P-sub layer.

[0010] In one embodiment of the present application, the bottom edge of the deep isolation trench is covered with the bottom edge of the BN layer, the BN layer is penetrated by the P-sub layer, the inner wall of the deep isolation trench is connected to the P-sub layer, and the bottom edge of the BN layer is connected to the P-sub layer.

[0011] In one embodiment of the present application, there are multiple groups of deep isolation grooves, and the multiple groups of deep isolation grooves are surrounded by the second branch and the third branch. The multiple groups of deep isolation grooves adopt a wall structure design, and the deep isolation grooves in adjacent gaps are staggered.

[0012] In one embodiment of the present application, the operating currents of the first branch, the second branch, and the third branch all flow vertically.

[0013] The technical solution of the utility model decomposes the low-capacitance ESD chip into the first branch, the second branch and the third branch through a deep isolation groove in terms of structure and function. The first branch is the main branch, and its structure includes the SN layer, the N-epi layer and the P-sub layer. Functionally, the structure composed of the SN layer, the N-epi layer and the P-sub layer can be equivalent to a low-capacitance diode, which can be named D3. The second branch and the third branch structurally include the SP layer, the N-epi layer, the BN layer and the P-sub layer, and can be functionally equivalent to a low-capacitance diode and a TVS tube with ordinary capacitance. The two groups of diodes are named D1 and D2 respectively, and the two groups of TVS tubes are named D4 and D5 respectively. The deep isolation groove forms multiple A barrier separates the three branches. The distance between the SN and SP layers can change the capacitance and clamping voltage, while the BN layer design helps suppress autodoping during epitaxial growth. Similarly, the capacitance of the first branch, D3, is Cap_D3. D3 itself is a low-capacitance diode, so the capacitance of this branch is low. The capacitance of the second branch, D1 + D4, is Cap_D1*Cap_D4 / (Cap_D1+Cap_D4). Because D1 has a low capacitance, the capacitance of this branch is also low. The capacitance of the third branch, D2 + D5, is Cap_D2*Cap_D5 / (Cap_D2+Cap_D5). Because D2 has a low capacitance, the capacitance of this branch is also low. The total capacitance of the chip structure is the sum of the capacitances of the three branches, also low. This structure ensures low overall chip capacitance and fast response time, which improves chip protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0015] Figure 1 This is a schematic diagram of the structure of the low-capacitance ESD chip with good protection effect of the utility model;

[0016] Figure 2 for Figure 1 A partial enlarged view of point A in the middle;

[0017] Figure 3 This is a cross-sectional view of a low-capacitance ESD chip with good protection effect according to the present invention.

[0018] Description of Figure Numbers:

[0019] 1. First branch; 11. SN layer; 12. N-epi layer; 13. P-sub layer; 2. Second branch; 21. SP layer; 22. BN layer; 3. Third branch; 4. Deep isolation trench.

[0020] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0022] Reference Figures 1 to 3 In one embodiment of the present invention, a low-capacitance ESD chip with excellent protection is proposed, characterized by including a first branch 1, a second branch 2, and a third branch 3. The first branch 1 is located between the second branch 2 and the third branch 3, and the second branch 2 and the third branch 3 are provided with a deep isolation trench 4 relative to the first branch 1. The first branch 1 includes, from top to bottom, an SN layer 11, an N-epi layer 12, and a P-sub layer 13. The N-epi layer 12 wraps around the periphery of the SN layer 11, and the end surface of the N-epi layer 12 away from the SN layer 11 is connected to the P-sub. The second branch 2 and the third branch 3 have the same structure. The second branch 2 includes, from top to bottom, an SP layer 21, an N-epi layer 12, a BN layer 22, and a P-sub layer 13. The deep isolation trench 4 wraps around the second branch 2 and the third branch 3.

[0023] In a low-capacitance ESD chip with good protection effect in the present application, the low-capacitance ESD chip is decomposed into the first branch 1, the second branch 2 and the third branch 3 through the deep isolation groove 4 in terms of structure and function. The first branch 1 is the main branch, and its structure includes the SN layer 11, the N-epi layer 12 and the P-sub layer 13. Functionally, the structure composed of the SN layer 11, the N-epi layer 12 and the P-sub layer 13 can be equivalent to a low-capacitance diode, which can be named D3. The second branch 2 and the third branch 3 structurally include the SP layer 21, the N-epi layer 12, the BN layer 22 and the P-sub layer 13, which can be functionally equivalent to a low-capacitance diode and a TVS tube with ordinary capacitance. The two groups of diodes are named D1 and D2 respectively, and the two groups of TVS tubes are named D 4 and D5, the deep isolation trench 4 forms multiple partitions, isolating the three branches. The distance between the SN layer 11 and the SP layer 21 can change the capacitance and clamping voltage, and the design of the BN layer 22 can help suppress self-doping during the epitaxial growth process. Similarly, the capacitance value of the first branch 1, D3, is Cap_D3. D3 itself is a low-capacitance diode, so the capacitance of this branch is low. The capacitance value of the second branch 2, D1+D4, is Cap_D1*Cap_D4 / (Cap_D1+Cap_D4). Because D1 is a low capacitance, the capacitance of this branch is also low. The capacitance value of the third branch 3, D2+D5, is Cap_D2*Cap_D5 / (Cap_D2+Cap_D5). Because D2 is a low capacitance, the capacitance of this branch is also low. The capacitance of the chip structure is the sum of the capacitances of the three branches, which is also low capacitance. With this structure, the overall capacitance of the chip is low and the response time is short, which is beneficial to improving the protection effect of the chip.

[0024] See also Figures 1 to 3 In one embodiment of the present application, the N-epi layer 12 is wrapped around the SP layer 21. The SP layer 21 and the SN layer 11 are connected to the same side end surface of the N-epi layer 12 and are evenly spaced. The end surface of the N-epi layer 12 away from the SP layer 21 is connected to the BN layer 22, and the end surface of the BN layer 22 away from the N-epi layer 12 is connected to the P-sub layer 13.

[0025] In a low-capacitance ESD chip with good protection effect in the present application, the N-epi layer 12 is used as the N-type epitaxial layer to wrap the SP layer 21, so that the SP layer 21 and the SN layer 11 are on the same side end surface of the N-epi layer 12. The change in the distance between SN and SP can adjust the capacitance and clamping voltage, making the chip easy to design. The BN layer 22 can protect the branch. Through its appropriate area design, it can suppress self-doping during the epitaxial growth process, which can effectively improve the performance of the chip.

[0026] See also Figure 3 In one embodiment of the present application, one end of the deep isolation trench 4 is connected to the outer edge of the N-epi layer 12 and passes through the N-epi layer 12 , and one end of the deep isolation trench 4 away from the N-epi layer 12 passes through the P-sub layer 13 .

[0027] In a low-capacitance ESD chip with good protection effect in the present application, the deep isolation trench 4 runs from the N-epi layer 12 to the P-sub layer 13, so that the second branch 2 and the third branch 3 can be completely isolated from the first branch 1, thereby improving the safety of the chip and avoiding mutual influence between different branches.

[0028] See also Figure 3 In one embodiment of the present application, the bottom edge of the deep isolation trench 4 is covered with the bottom edge of the BN layer 22, the BN layer 22 is penetrated by the P-sub layer 13, the inner wall of the deep isolation trench 4 is connected to the P-sub layer 13, and the bottom edge of the BN layer 22 is connected to the P-sub layer 13.

[0029] In a low-capacitance ESD chip with good protection effect in the present application, the bottom edge of the deep isolation groove 4 is covered with the bottom edge of the BN layer 22, so that the branch isolation effect of the chip is better, thereby ensuring the stability of the chip operation and improving the chip performance.

[0030] See also Figures 1 to 3 In one embodiment of the present application, multiple groups of deep isolation grooves 4 are provided, and the multiple groups of deep isolation grooves 4 are surrounded by the second branch 2 and the third branch 3. The multiple groups of deep isolation grooves 4 adopt a wall structure design, and the deep isolation grooves 4 in adjacent gaps are staggered.

[0031] In a low-capacitance ESD chip with good protection effect in the present application, multiple groups of deep isolation grooves 4 are provided, and multiple groups of deep isolation grooves 4 are wrapped around the second branch 2 and the third branch 3. In the present application, from the cross-section, there are 4 groups of deep isolation grooves 4, and each group includes multiple deep isolation grooves 4. The multiple isolation grooves are designed in a wall structure to ensure the isolation effect and improve the ability to resist process fluctuations. Even if the depth of one groove or the filling does not meet the standard, it will not affect the isolation effect. Adjacent deep isolation grooves 4 are staggered, and the gap spacing is controlled at 10um. The corners of the deep isolation grooves 4 are provided with arcs, and good flatness can be guaranteed when filling the corners.

[0032] See also Figures 1 to 3 In one embodiment of the present application, the working currents of the first branch 1 , the second branch 2 , and the third branch 3 all flow vertically.

[0033] In a low-capacitance ESD chip with good protection effect in the present application, the working currents of the first branch 1, the second branch 2 and the third branch 3 all flow vertically, making the entire chip structure a vertical structure. Combined with the three-branch structure, it can effectively improve the chip performance and improve its protection effect.

[0034] The same or similar numbers in the drawings of this embodiment correspond to the same or similar parts; in the description of this application, it should be understood that if the terms "upper", "lower", "left", "right", etc. indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the drawings. This is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as a limitation on this patent. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0035] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A low capacitance ESD chip with good protection effect, characterized in that: The circuit comprises a first branch, a second branch and a third branch, wherein the first branch is located between the second branch and the third branch, and the second branch and the third branch are provided with a deep isolation groove relative to the first branch; The first branch includes, from top to bottom, an SN layer, an N-epi layer, and a P-sub layer, wherein the N-epi layer surrounds the periphery of the SN layer, and an end surface of the N-epi layer away from the SN layer is connected to the P-sub layer; The second branch and the third branch have the same structure. The second branch includes an SP layer, an N-epi layer, a BN layer and a P-sub layer from top to bottom. The deep isolation trench surrounds the second branch and the third branch.

2. A low capacitance ESD chip with good protection effect according to claim 1, characterized in that: The N-epi layer is wrapped around the SP layer. The SP layer and the SN layer are connected to the same side end surface of the N-epi layer and are evenly spaced. The end surface of the N-epi layer away from the SP layer is connected to the BN layer, and the end surface of the BN layer away from the N-epi layer is connected to the P-sub layer.

3. The low capacitance ESD chip with good protection effect according to claim 1, characterized in that: One end of the deep isolation trench is connected to the outer edge of the N-epi layer and penetrates the N-epi layer. One end of the deep isolation trench away from the N-epi layer penetrates the P-sub layer.

4. A low capacitance ESD chip with good protection effect according to claim 3, characterized in that: The bottom edge of the deep isolation trench covers the bottom edge of the BN layer, the BN layer penetrates the P-sub layer, the inner wall of the deep isolation trench is connected to the P-sub layer, and the bottom edge of the BN layer is connected to the P-sub layer.

5. A low capacitance ESD chip with good protection effect according to claim 4, characterized in that: There are multiple groups of deep isolation grooves, and the multiple groups of deep isolation grooves surround the second branch and the third branch. The multiple groups of deep isolation grooves adopt a wall structure design, and the deep isolation grooves in adjacent gaps are staggered.

6. The low capacitance ESD chip with good protection effect according to claim 1, characterized in that: The working currents of the first branch, the second branch and the third branch all flow vertically.

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