Pull-down circuit suitable for NMOS path tube

Abstract

The utility model discloses a pull-down circuit suitable for an NMOS path tube, which comprises a trigger circuit, a reverse circuit, a current source I0, a first resistor, a first capacitor and an MOS tube M1, the input end of the current source I0 and the input end of the trigger circuit are respectively connected with a voltage VCC, the voltage VCC is obtained by voltage stabilization of an input voltage VIN, and the first resistor is connected with the first capacitor. The output end of the current source I0 is electrically connected with one end of the first capacitor and the reset end of the trigger circuit, the output end of the trigger circuit is electrically connected with the input end of the reverse circuit through the first resistor, the output end of the reverse circuit is electrically connected with the grid electrode of the MOS tube M1, the drain electrode of the MOS tube is electrically connected with the grid electrode of the NMOS path tube M0, and the output end of the NMOS path tube M0 is electrically connected with the output end of the reverse circuit. And the source electrode of the MOS tube and the other end of the first capacitor are respectively grounded.

Description

Technical Field

[0001] The utility model relates to the technical field of pull-down circuits, in particular to a pull-down circuit suitable for an NMOS path tube. Background Art

[0002] Among the currently popular path transistor chips with input overvoltage protection, there are two types: NMOS path transistors and PMOS path transistors. Generally speaking, the mobility of NMOS is higher than that of PMOS, and using NMOS as a path transistor has a cost advantage. Figure 1 As shown, the connection scheme of the NMOS path transistor is that the input is connected to the drain terminal and the output is connected to the source terminal. The control and drive circuit controls the on and off of the NMOS by controlling the gate voltage. When VGS>threshold voltage, the NMOS is turned on. The conventional input overvoltage protection triggering environment is that the chip's initial input voltage is normal. At this time, the path transistor is normally turned on and the internal control circuit of the chip is in normal working state. When the input voltage rises above the set protection voltage, the control circuit turns off the path transistor to protect other circuits connected to the output. As the market demand for overvoltage protection chips increases, the chip's input voltage is required to be powered on quickly, and the chip's overvoltage protection still exists. When the input voltage is quickly powered on from 0V, the internal power supply of the chip rises rapidly, and this process may be within 1us. Since the control circuits such as the reference circuit and the detection circuit require a certain startup time to work normally, the gate terminal of the path transistor cannot be effectively controlled during the fast power-on time. For the NMOS path transistor, due to the NMOS's own parasitic capacitance C GD Due to the existence of , the gate voltage will increase along with the input voltage during the rapid power-on process, causing VGS to be greater than the threshold voltage. At this time, the NMOS is turned on, causing the output voltage to increase along with the input voltage. If the input voltage jumps to an excessively high voltage, causing the output voltage to be higher than the required protection voltage, the circuit behind the output end will be burned. Utility Model Content

[0003] The purpose of the present invention is to solve at least one of the technical problems existing in the prior art and to provide a pull-down circuit suitable for NMOS path tubes that maintains a low output voltage and improves reliability when the input voltage is quickly powered up from 0V.

[0004] According to an embodiment of the present invention, a pull-down circuit suitable for an NMOS path transistor includes a trigger circuit, an inverting circuit, a current source I0, a first resistor, a first capacitor, and a MOS transistor M1. The input end of the current source I0 and the input end of the trigger circuit are respectively connected to a voltage VCC, which is obtained by stabilizing the input voltage VIN. The output end of the current source I0 is respectively electrically connected to one end of the first capacitor and a reset end of the trigger circuit. The output end of the trigger circuit is electrically connected to the input end of the inverting circuit via the first resistor. The output end of the inverting circuit is electrically connected to the gate of the MOS transistor M1, the drain of the MOS transistor is electrically connected to the gate of the NMOS path transistor M0, and the source of the MOS transistor and the other end of the first capacitor are respectively grounded.

[0005] According to some embodiments of the present invention, a second capacitor is included, one end of the second capacitor is electrically connected to the input end of the reverse circuit, and the other end of the second capacitor is grounded.

[0006] According to some embodiments of the present invention, the first capacitor includes a capacitor C1, the first resistor includes a resistor R1, and the second capacitor includes a capacitor C0.

[0007] According to some embodiments of the present invention, the trigger circuit adopts a trigger.

[0008] According to some embodiments of the present invention, the trigger is a D flip-flop DFF.

[0009] According to some embodiments of the present invention, the inverting circuit uses an inverter INV.

[0010] According to some embodiments of the present invention, the MOS transistor M1 is an NMOS transistor.

[0011] The pull-down circuit for an NMOS transistor according to an embodiment of the present invention has at least the following beneficial effects: when the input voltage VIN is rapidly powered up from 0V, the voltage VCC rapidly increases, and the current source I0 outputs a low level. At this time, the first capacitor acts as a delay, causing the reset terminal of the trigger circuit to remain low for a certain period of time, thereby causing the trigger circuit to output a low level. The output terminal of the reverse circuit is pulled up to a high level, turning on the MOS transistor M1 and discharging the gate terminal of the NMOS transistor M0. As a result, during the rapid power-up of the input voltage VIN from 0V, the NMOS transistor M0 is in a closed state, and the output voltage does not exceed the set protection voltage. When the input voltage VIN is fully powered up and the internal reference voltage and clock of the chip are stable, the current source I0 charges the first capacitor, the reset terminal of the trigger circuit becomes high, and the reset state is released. When a trigger signal arrives, the trigger circuit outputs a high level, and the reverse circuit outputs a low level, causing the MOS transistor M1 to turn off, thereby not affecting the control and driving of the NMOS transistor M0 by the internal control circuit and the drive circuit.

[0012] Additional aspects and advantages of the present invention will be given in part in the following description and will become apparent from the following description or learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The following is a further description of the specific embodiments of the present invention in conjunction with the accompanying drawings;

[0014] Figure 1 This is the connection diagram of the NMOS path tube;

[0015] Figure 2 This is a schematic diagram of a pull-down circuit suitable for NMOS path tubes. DETAILED DESCRIPTION

[0016] This section will describe in detail the specific embodiments of the present invention. The preferred embodiments of the present invention are shown in the accompanying drawings. The purpose of the accompanying drawings is to supplement the description of the text part of the specification with graphics, so that people can intuitively and vividly understand each technical feature and overall technical solution of the present invention, but it cannot be understood as a limitation on the scope of protection of the present invention.

[0017] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.

[0018] In the description of this utility model, "several" means one or more, "many" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" in the description is solely for the purpose of distinguishing technical features and is not to be construed as indicating or implying relative importance, implicitly specifying the number of the indicated technical features, or implicitly specifying the order of the indicated technical features.

[0019] Reference Figures 1 to 2The utility model discloses a pull-down circuit suitable for an NMOS path transistor, comprising a trigger circuit, an inverting circuit, a current source I0, a first resistor, a first capacitor, and a MOS transistor M1. The input end of the current source I0 and the input end of the trigger circuit are respectively connected to a voltage VCC, which is obtained by stabilizing the input voltage VIN. The output end of the current source I0 is respectively electrically connected to one end of the first capacitor and a reset end of the trigger circuit. The output end of the trigger circuit is electrically connected to the input end of the inverting circuit via the first resistor. The output end of the inverting circuit is electrically connected to the gate of the MOS transistor M1. The drain of the MOS transistor is electrically connected to the gate of the NMOS path transistor M0. The source of the MOS transistor and the other end of the first capacitor are respectively grounded. When the input voltage VIN is rapidly powered up from 0V, the voltage VCC rises rapidly, and the current source I0 outputs a low level. At this point, the first capacitor acts as a delay, keeping the reset terminal of the trigger circuit low for a certain period of time, causing the trigger circuit to output a low level. The output terminal of the reverse circuit is pulled high, turning on MOS transistor M1 and discharging the gate terminal of NMOS path transistor M0. As a result, during the rapid power-up of the input voltage VIN from 0V, NMOS path transistor M0 is off, and the output voltage does not exceed the set protection voltage. When the input voltage VIN is fully powered up and the internal reference voltage and clock of the chip stabilize, current source I0 charges the first capacitor, and the reset terminal of the trigger circuit goes high, releasing the reset state. When a trigger signal arrives, the trigger circuit outputs a high level, and the reverse circuit outputs a low level, turning off MOS transistor M1. This does not affect the control and drive of NMOS path transistor M0 by the internal control and drive circuits. This simple structure makes it easy to control and effectively improves reliability.

[0020] Furthermore, a second capacitor is included, one end of the second capacitor is electrically connected to the input end of the reverse circuit, and the other end of the second capacitor is grounded. Before the input voltage VIN is powered on, the input end of the reverse circuit is at a low level, ensuring that the reverse circuit outputs a high level to turn on the MOS tube M1, so that when the input voltage VIN is quickly powered on from 0V, the NMOS path tube M0 can be in a closed state, and the output voltage will not exceed the set protection voltage, further improving reliability and control accuracy.

[0021] like Figure 2 As shown, in some embodiments, the first capacitor includes capacitor C1, the first resistor includes resistor R1, the second capacitor includes capacitor C0, and the trigger circuit uses a flip-flop, preferably a D flip-flop DFF. The reverse circuit uses an inverter INV, and the MOS transistor M1 uses a more efficient NMOS transistor, resulting in a simple structure and easy implementation.

[0022] It is easy for those skilled in the art to understand that, under the premise of no conflict, the above preferred embodiments can be freely combined and superimposed.

[0023] The above are only preferred embodiments of the present invention and do not limit the patent scope of the present invention. All equivalent structural transformations made by using the contents of the present invention specification and drawings under the utility model concept, or directly or indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A pull-down circuit suitable for an NMOS path tube, characterized in that: include: A trigger circuit, an inverting circuit, a current source I0, a first resistor, a first capacitor, and a MOS transistor M1. The input end of the current source I0 and the input end of the trigger circuit are respectively connected to a voltage VCC, which is obtained by stabilizing the input voltage VIN. The output end of the current source I0 is respectively electrically connected to one end of the first capacitor and a reset end of the trigger circuit. The output end of the trigger circuit is electrically connected to the input end of the inverting circuit via the first resistor. The output end of the inverting circuit is electrically connected to the gate of the MOS transistor M1. The drain of the MOS transistor is electrically connected to the gate of the NMOS path transistor M0. The source of the MOS transistor and the other end of the first capacitor are respectively grounded.

2. The pull-down circuit for an NMOS path transistor according to claim 1, wherein: It includes a second capacitor, one end of the second capacitor is electrically connected to the input end of the reverse circuit, and the other end of the second capacitor is grounded.

3. The pull-down circuit for an NMOS path transistor according to claim 2, wherein: The first capacitor includes a capacitor C1 , the first resistor includes a resistor R1 , and the second capacitor includes a capacitor C0 .

4. The pull-down circuit for an NMOS path transistor according to claim 1, wherein: The trigger circuit uses a trigger.

5. The pull-down circuit for an NMOS path transistor according to claim 4, wherein: The trigger is a D flip-flop DFF.

6. The pull-down circuit for an NMOS path transistor according to claim 1, wherein: The reverse circuit uses an inverter INV.

7. The pull-down circuit for an NMOS path transistor according to claim 1, wherein: The MOS tube M1 is an NMOS tube.

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