Semiconductor device

Abstract

The utility model provides a semiconductor device, which is applied to the technical field of semiconductors. According to the utility model, the plurality of bit line structures in the semiconductor device are arranged alternately along the horizontal direction, and the top surfaces of the first bit line structures and the second bit line structures are located at different horizontal heights; the problems of top adhesion, electric leakage and the like of adjacent bit line structures of the bit line structures with the top surfaces at the same horizontal height along with the size reduction of the semiconductor device in the prior art are solved, and the purpose of improving the reliability and the performance of the semiconductor device is further achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a semiconductor device. Background Art

[0002] As various electronic products develop towards miniaturization, semiconductor device designs must also meet the requirements of high integration and density. Dynamic random access memory (DRAM) with a recessed gate structure has gradually replaced DRAM with only a planar gate structure in the current mainstream development trend because it can achieve a longer carrier channel length within the same semiconductor substrate, thereby reducing leakage in the capacitor structure. Generally speaking, a DRAM with a recessed gate structure is composed of a large number of memory cells clustered together to form an array area for storing information. Each memory cell is composed of a transistor element and a capacitor element connected in series to receive voltage information from a word line (WL) and a bit line (BL). To meet product requirements, the density of memory cells in the array area must continue to increase, resulting in an increasing risk of adhesion between the tops of adjacent bit line structures. Therefore, existing technologies or structures need further improvement to effectively enhance the performance and reliability of related memory devices. Utility Model Content

[0003] The purpose of the present invention is to provide a semiconductor device that effectively avoids the problems of top adhesion, leakage, etc. in the conventional bit line structure caused by the miniaturization of the semiconductor device size, thereby improving the reliability and performance of the semiconductor device.

[0004] In order to achieve the above object, the present invention provides a semiconductor device, which may at least include:

[0005] substrate;

[0006] a plurality of bit line structures disposed on the substrate, comprising a conductive layer and an insulating cap layer stacked sequentially from bottom to top, the bit line structures comprising a first bit line structure and a second bit line structure spaced apart from each other and alternately arranged in a horizontal direction, and a top surface of the first bit line structure being higher than a top surface of the second bit line structure;

[0007] a plurality of connection pad structures, disposed between adjacent bit line structures and extending in a horizontal direction to cover a portion of the top surface of the bit line structure;

[0008] A plurality of isolation structures are arranged between adjacent connection pad structures, including a first isolation structure located above the first bit line structure and a second isolation structure located above the second bit line structure.

[0009] In some optional examples, top surfaces of the conductive layer of the first bit line structure and the conductive layer of the second bit line structure are located at the same level.

[0010] In some optional examples, the first isolation structure directly contacts the first bit line structure, and the second isolation structure and the second bit line structure are isolated from each other.

[0011] In some optional examples, the first isolation structure directly contacts the first bit line structure, and the second isolation structure directly contacts the second bit line structure.

[0012] In some optional examples, the first isolation structure and the second isolation structure extend to different depths of the first bit line structure and the second bit line structure.

[0013] In some optional examples, a bottom surface of the first isolation structure is lower than a bottom surface of the second isolation structure.

[0014] In some optional examples, a distance between a top surface of the first bit line structure and a top surface of the connection pad structure may be smaller than a distance between a top surface of the second bit line structure and a top surface of the connection pad structure.

[0015] In some optional examples, the semiconductor device in the present invention may further include:

[0016] A dielectric layer is disposed on the substrate and covers a top surface of the second bit line structure.

[0017] In some optional examples, top surfaces of the dielectric layer and the first bit line structure may be located at the same level.

[0018] In some optional examples, the semiconductor device in the present invention may further include:

[0019] A plurality of contact structures are disposed under the connection pad structure and electrically connected to the substrate.

[0020] In the present invention, by arranging multiple bit line structures in a semiconductor device into a first bit line structure and a second bit line structure with top surfaces at different horizontal heights in an alternating arrangement along the horizontal direction, the problems of top adhesion and leakage of adjacent bit line structures derived from the bit line structures with top surfaces at the same horizontal height as the size of the semiconductor device is reduced in the prior art are avoided, thereby improving the reliability and performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following detailed description, they are used to explain the present application but do not constitute a limitation of the present application. In the accompanying drawings:

[0022] Figures 1 to 8 Schematic diagram of the structure of a method for manufacturing a semiconductor device in an embodiment of the present invention during the preparation process; wherein,

[0023] Figure 7 Schematic cross-sectional view of a semiconductor device in a first embodiment of the present invention;

[0024] Figure 8 It is a cross-sectional schematic diagram of a semiconductor device in the second embodiment of the present invention.

[0025] Wherein, the accompanying drawings are marked as follows:

[0026] 100 - substrate, 101 - shallow trench isolation, 110 - isolation layer, 120 - bit line material layer, 121 - semiconductor layer; 122 - barrier layer; 123 - conductive layer; 124 - insulating cap layer, BL - bit line structure, BL1 - first bit line structure, BL2 - second bit line structure, 130 - sidewall structure, 131 - first sidewall, 132 - second sidewall, 140 - insulating material layer, 150 - photoresist layer, 160 - dielectric layer, SNC - contact structure, 170-silicide layer, 180-connection pad structure, 181-first connection pad layer, 182-second connection pad layer, 190-isolation structure, 191-first isolation structure, 192-second isolation structure, X-horizontal direction, Y-vertical direction, D1~D3-extension depth of the isolation structure on the bit line structure, H1-distance between the top surface of the first bit line structure and the top surface of the connection pad structure, H2-distance between the top surface of the second bit line structure and the top surface of the connection pad structure.

[0027] In the drawings, like components are given like reference numerals, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0028] The semiconductor device proposed by the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to conveniently and clearly assist in illustrating the purpose of the embodiments of the present invention. Many specific details are set forth in the following description to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein, and therefore the present invention is not limited to the specific embodiments disclosed below.

[0029] For ease of understanding, the horizontal direction and the vertical direction are defined below, wherein the horizontal direction is a direction parallel to the surface of the substrate 100; the vertical direction is a direction perpendicular to the surface of the substrate 100; and Figures 1 to 8 The X direction and the Y direction are defined in , wherein the X direction corresponds to the horizontal direction, and the Y direction corresponds to the vertical direction, and the X direction and the Y direction, the horizontal direction and the vertical direction are perpendicular to each other.

[0030] Please refer to Figure 7 As shown, Figure 7 FIG is a cross-sectional view of a semiconductor device in the first embodiment of the present invention. Figure 7 As shown, the semiconductor device may include a substrate 100, a plurality of bit line structures BL, a dielectric layer 160, a connection pad structure 180, and an isolation structure 190. The substrate 100 may be any suitable substrate material known in the art, such as, but not limited to, a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe), a silicon-on-insulator substrate, or a substrate composed of other suitable materials. A plurality of shallow trench isolations (STIs) 101 are further provided within the substrate 100 to define a plurality of active areas (AA, not shown) within the substrate 100. Specifically, the shallow trench isolation 101 may include a single layer or multiple layers of dielectric material. Suitable dielectric materials may include, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorinated silica glass (FSG), silicon carbon oxide (SiCOH), spin-on silica glass (spin-on glass), porous low-k dielectric materials, organic polymer dielectric materials, or combinations thereof, but are not limited thereto. For example, the shallow trench isolation 101 in this embodiment may be in the form of an elongated strip with its major axis extending along the Y direction. Furthermore, an isolation layer 110 is provided on the substrate 100. Specifically, the isolation layer 110 may be a single layer structure, such as a silicon oxide layer or a silicon nitride layer, or a composite layer, such as an ONO composite layer composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, but is not limited thereto.

[0031] In this embodiment, the bit line structure BL may include a plurality of first bit line structures BL1 and a plurality of second bit line structures BL2 whose top surfaces are located at different horizontal heights. That is, the top surfaces of the plurality of first bit line structures BL1 or the plurality of second bit line structures BL2 are coplanar, but the top surfaces of the plurality of first bit line structures BL1 and the plurality of second bit line structures BL2 are not coplanar, that is, the plurality of first bit line structures BL1 and the plurality of second bit line structures BL2 have a height difference along the vertical direction (hereinafter referred to as the Y direction). This avoids the problem of the bit line structures having top surfaces at the same horizontal height in the prior art (that is, the top surfaces of all bit line structures are coplanar), and improves the reliability and performance of the semiconductor device as the size of the semiconductor device is reduced, thereby avoiding the problems of top adhesion and leakage of adjacent bit line structures.

[0032] Specifically, a plurality of first bitline structures BL1 and a plurality of second bitline structures BL2 may be spaced apart from each other along a horizontal direction (hereinafter referred to as the X-direction) and alternately disposed on the substrate 100. The first bitline structures BL1 and the second bitline structures BL2 include multiple bitline material layers, such as a bitline material layer 120 composed of a semiconductor layer 121, a barrier layer 122, a conductive layer 123, and an insulating cap layer 124 stacked in ascending order. The semiconductor layer 121 may be made of, but is not limited to, single crystal silicon (crystalline silicon), polycrystalline silicon (poly silicon), amorphous silicon (amorphous silicon), doped silicon, silicon germanium (SiGe), or other suitable semiconductor materials. The barrier layer 122 may be made of, but is not limited to, a metal, metal silicide, or metal nitride, such as, but not limited to, titanium (Ti), titanium nitride (TiN), tungsten silicide (WSi), cobalt silicide (CoSi), or tungsten nitride (WN). The material of the conductive layer 123 may include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but is not limited thereto. The insulating cap layer 124 may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but is not limited thereto. Exemplarily, the material of the semiconductor layer 121 is polysilicon, the material of the barrier layer 122 is cobalt silicide (CoSi), the material of the conductive layer 123 is tungsten (W), and the material of the insulating cap layer 124 is silicon nitride (SiN).

[0033] In this embodiment, the top surface of the first bit line structure BL1 is higher than the top surface of the second bit line structure BL2. Specifically, the top surface of the insulating cap layer 124 in the first bit line structure BL1 is higher than the top surface of the insulating cap layer 124 in the second bit line structure BL2. However, the conductive layer 123, the barrier layer 122, and the semiconductor layer 121 in the first bit line structure BL1 are all located at the same level as the top surfaces of the conductive layer 123, the barrier layer 122, and the semiconductor layer 121 in the second bit line structure BL2. In addition, the sidewalls of the first bit line structure BL1 and the second bit line structure BL2 in the embodiment of the present invention may also be provided with sidewall structures 130 located on both sides thereof. The sidewall structure 130 may also have a multi-layer structure, for example Figure 7 The first sidewall 131 and the second sidewall 132 are stacked sequentially along the X-direction, and the first sidewall 131 is in direct contact with the sidewalls of the first bitline structure BL1 or the second bitline structure BL2. Specifically, the first sidewall 131 and the second sidewall 132 may each comprise a dielectric material, such as, but not limited to, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), or a combination thereof. Exemplarily, the material of the first sidewall 131 is silicon oxide (SiO2), and the material of the second sidewall 132 is silicon nitride (SiN). It should be noted that since the bitline structure BL in this embodiment of the present invention includes the first bitline structure BL1 and the second bitline structure BL2 having different heights along the Y-direction, the heights of the sidewall structures 130 located on the sidewalls of the first bitline structure BL1 and the second bitline structure BL2 may also include first and second sidewall structures having different heights along the Y-direction. To simplify the drawing, the first and second sidewall structures are labeled with the same reference numerals in this embodiment.

[0034] Continue to refer to Figure 7 As shown, the dielectric layer 160 in this embodiment is specifically disposed on the substrate 100, and the dielectric layer 160 can at least cover the top surface of the second bitline structure BL2, which has a lower top surface, among the bitline structures BL. Specifically, the top surface of the dielectric layer 160 can be flush with the top surface of the second bitline structure BL2 among the bitline structures BL, or the top surface of the dielectric layer 160 can be flush with the top surface of the first bitline structure BL1 among the bitline structures BL, or the top surface of the dielectric layer 160 can be between the top surfaces of the first bitline structure BL1 and the second bitline structure BL2 among the bitline structures BL, but the present invention is not limited thereto. For example, in this embodiment, the top surface of the dielectric layer 160 is configured to be flush with the top surface of the first bitline structure BL1 among the bitline structures BL, so that it covers the top surface of the second bitline structure BL2. The material of the dielectric layer 160 may include, but is not limited to, silicon oxide, polysilazane, or other suitable materials.

[0035] Furthermore, the connection pad structure 180 in this embodiment is specifically disposed between adjacent bit line structures BL and extends along the X direction to cover a part of the top surface of the bit line structure BL. The isolation structure 190 including the first isolation structure 191 and the second isolation structure 192 that are separated from each other and alternately arranged along the X direction is specifically disposed between adjacent connection pad structures 180. Specifically, the connection pad structure 180 may include a first connection pad layer 181 and a second connection pad layer 182 that are stacked in sequence along the Y direction. Since a dielectric layer 160 with a top surface flush with the top surface of the first bit line structure BL1 is provided between adjacent bit line structures BL in this embodiment, the first connection pad layer 181 in the connection pad structure 180 directly covers the top surface of the dielectric layer 160 and is in direct contact with the first bit line structure BL1. The top surfaces of the first isolation structure 191 and the second isolation structure 192 in the isolation structure 190 are flush, and are at the same horizontal height (i.e., coplanar) as the top surface of the second connection pad 182 in the connection pad structure 180. All the first isolation structures 191 pass through the connection pad structure 180, the dielectric layer 160 and are in direct contact with the first bit line structure BL1. A part of the second isolation structures 192 in the isolation structure 190 pass through the connection pad structure 180, the dielectric layer 160 and are in direct contact with the second bit line structure BL2, and the other part of the second isolation structures 192 pass through the connection pad structure 180, the dielectric layer 160 and are isolated from the second bit line structure BL2 through the dielectric layer 160.

[0036] In this embodiment, the first isolation structure 191 and the second isolation structure 192 in the isolation structure 190 may extend along the Y direction to different depths of the first bit line structure BL1 and the second bit line structure BL2, that is, the bottom surfaces of some of the first isolation structures 191 and some of the second isolation structures 192 are not coplanar. For example, the bottom surface of the first isolation structure 191 may be lower than the bottom surface of the second isolation structure 192. That is, the distances (along the Y direction) between the top surface and the bottom surface of multiple first isolation structures 191 in the isolation structure 190 may be different, the distances between the top surface and the bottom surface of multiple second isolation structures 192 may be different, and the distances between the top surface and the bottom surface of multiple first isolation structures 191 and the distances between the top surface and the bottom surface of multiple second isolation structures 192 may also be different. Exemplarily, as Figure 7 shown, if the extension depth of the isolation structure 190 on the bit line structure BL is D, that is, the extension depth of one of the first isolation structures 191 on the first bit line structure BL1 is D2, and the extension depths of the two second isolation structures 192 on the second bit line structure BL2 are D1 and D3 respectively, then D1 < D2 < D3, but not limited thereto.

[0037] In this embodiment, the material of the first connection pad layer 181 may include conductive barrier materials such as titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN), but is not limited thereto. The material of the second connection pad layer 182 may include metals such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), nitrides, silicides, alloys, and / or composite layers of the aforementioned materials, but is not limited thereto. The material of the isolation structure 190 may include nitrides such as silicon nitride, and may also include oxides such as silicon oxide, but is not limited thereto. Exemplarily, the material of the first connection pad layer 181 is titanium nitride (TiN), the material of the second connection pad layer 182 is tungsten (W), and the material of the isolation structure 190 (including the first isolation structure 191 and the second isolation structure 192) is silicon nitride.

[0038] It is understood that, when viewed from the Y direction, the distance between the connection pad structure 180 and the bitline structure BL is less than the distance between the top surface of the first bitline structure BL1 and the top surface of the connection pad structure 180 (i.e., the top surface of the second connection pad 182) in the bitline structure BL of this embodiment, but the present invention is not limited thereto. In this configuration, the first bitline structure BL1 and the second bitline structure BL2, whose top surfaces are located at different heights, achieve the purpose of the present invention of avoiding the problems of top adhesion and leakage of adjacent bitline structures that arise from the scaling of semiconductor device sizes in the prior art where the top surfaces of the bitline structures are located at the same height, thereby improving the reliability and performance of the semiconductor device.

[0039] A person skilled in the art will readily appreciate that, to meet actual product requirements, the semiconductor device of the present invention may have other aspects and is not limited to the aforementioned aspects. The following further describes other embodiments or variations of the semiconductor device of the present invention. For simplicity, the following description will primarily detail the differences between the various embodiments, without reiterating the similarities. Furthermore, identical components in the various embodiments of the present invention are designated with the same reference numerals to facilitate cross-reference between the various embodiments.

[0040] Please refer to Figure 8 As shown, Figure 8FIG2 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention. The structure of the semiconductor device of this embodiment is substantially the same as that of the semiconductor device of the first embodiment. For example, the semiconductor device also includes multiple bitline structures BL, and the bitline structures BL include multiple first bitline structures BL1 and multiple second bitline structures BL2, which are spaced apart from each other along the X-direction and alternately disposed on a substrate 100, and whose top surfaces are not coplanar. The similarities are not further described here. The semiconductor device of this embodiment differs from the first embodiment primarily in that the semiconductor device lacks a dielectric layer 160. Instead, the semiconductor device includes multiple contact structures SNC disposed beneath connection pad structures 180, and a silicide layer 170 disposed between the connection pad structures 180 and the contact structures SNC. The contact structures SNC extend vertically along the Y-direction within the substrate 100 between adjacent bitline structures BL to electrically connect to the substrate 100. Because the contact structures SNC are provided in this embodiment and the dielectric layer 160 is absent, the cross-sectional shape of the connection pad structures 180 in this embodiment also differs from that of the first embodiment.

[0041] Specifically, if Figure 8As shown, in this embodiment, a contact structure SNC is formed respectively within the interval between adjacent first bit line structure BL1 and second bit line structure BL2. Its two sides are separated from the bit line structure 120 by sidewall structures 130 and do not directly contact, while its bottom directly contacts the end of the active region (substrate 100). Herein, the material of the contact structure SNC may include crystalline silicon, poly silicon, amorphous silicon, doped silicon, SiGe, or other suitable silicon-containing semiconductor materials, but is not limited thereto. Exemplarily, the material of the contact structure SNC is phosphorus-doped silicon (SiP). A silicide layer 170 is located above the contact structure SNC, and a connection pad structure 180 conformally covers the top surface of the contact structure SNC, the top surface of the sidewall structure 130, and the top surface of the bit line structure BL (including the first bit line structure BL1 and the second bit line structure BL2). Moreover, the connection pad structure 180 in this embodiment also includes a first connection pad 181 and a second connection pad 182 stacked in sequence from bottom to top. Therefore, the conformal coverage of the connection pad structure 180 may specifically be that its first connection pad 181 wraps around the outer surfaces of the first bit line structure BL1 and the second bit line structure BL2, and its second connection pad 182 covers the first connection pad 181 and fills the gap between the adjacent first bit line structure BL1 and second bit line structure BL2, and its top surface is higher than the top surface of the first bit line structure BL1. Exemplarily, when observing the relationship between the top surface of the connection pad structure 180 and the top surface of the bit line structure BL from the top surface of the connection pad structure 180 to the top surface of the bit line structure BL, if the distance between the top surface of the connection pad structure 180 and the top surface of the first bit line structure BL1 is H1, and the distance between the top surface of the connection pad structure 180 and the top surface of the second bit line structure BL2 is H2, then the distance H1 < H2, but is not limited thereto.

[0042] It should be particularly noted that the isolation structure 190 in this embodiment is still divided into a first isolation structure 191 and a second isolation structure 192. However, at this time, the first isolation structure 191 directly contacts the first bit line structure BL1, and the second isolation structure 192 also directly contacts the second bit line structure BL2. Of course, the first isolation structure 191 and the second isolation structure 192 in the isolation structure 190 in this embodiment can still extend along the Y direction to different depths of the first bit line structure BL1 and the second bit line structure BL2 in the bit line structure BL. Exemplarily, as Figure 8 shown, if the extension depth of the isolation structure 190 on the bit line structure BL is D, that is, the extension depth of one of the first isolation structures 191 on the first bit line structure BL1 is D2, and the extension depths of the two second isolation structures 192 on the second bit line structure BL2 are D1 and D3 respectively, then D2 < D1 < D3, but is not limited thereto.

[0043] Under this setting, the first bit line structure BL1 and the second bit line structure BL2 in this embodiment, whose top surfaces are located at different horizontal heights, can also achieve the purpose of the present invention to avoid the problems of top adhesion and leakage of adjacent bit line structures derived from the bit line structures with top surfaces located at the same horizontal height in the prior art as the size of semiconductor devices is reduced, thereby improving the reliability and performance of semiconductor devices.

[0044] It should be understood that the “common shape” in the embodiments of the present invention refers to constructing a continuous structural shape by utilizing the morphological similarities and correlations between two or more shapes.

[0045] In order to enable a person skilled in the art to which the present invention relates to easily understand the semiconductor device in the embodiment of the present invention, the semiconductor device proposed in the present invention will be further described below in conjunction with various structural schematic diagrams of the semiconductor device manufacturing method during the preparation process.

[0046] Please refer to Figures 1 to 8 As shown, Figures 1 to 8 It is a structural schematic diagram of the manufacturing method of a semiconductor device during the preparation process in an embodiment of the present utility model.

[0047] like Figure 1As shown, a substrate 100 is first provided, and a plurality of shallow trenches are formed in the substrate 100 by an etching process. Then, an insulating material (such as silicon oxide, silicon nitride, etc.) is filled in the plurality of shallow trenches by a deposition process, such as at least one of a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process, to form a plurality of shallow trench isolations 101. The plurality of shallow trench isolations 101 define a plurality of active areas in the substrate 100. Then, an isolation layer 110 (such as a silicon oxide layer or a silicon nitride layer) and a bit line material layer 120 located on the isolation layer 110 are formed on the substrate 100. Specifically, forming the bit line material layer 120 may include sequentially forming a semiconductor layer 121, a barrier layer 122, a conductive layer 123, and an insulating cap layer 124 on the substrate 100 from bottom to top. Exemplarily, the semiconductor layer 121 is made of polysilicon, the barrier layer 122 is made of cobalt silicide (CoSi), the conductive layer 123 is made of tungsten (W), and the insulating cap layer 124 is made of silicon nitride (SiN). Subsequently, the multilayer structure of the bit line material layer 120 is sequentially etched along the Y direction using an etching process, thereby forming a plurality of mutually separated bit line structures BL therein. At this time, the top surfaces of the plurality of bit line structures BL are all located on the same horizontal line (i.e., coplanar), and the heights of the plurality of bit line structures BL along the Y direction are consistent with the height of the first bit line structure BL1 along the Y direction, but this is not limited to this. Next, sidewall structures 130 are formed on both sides of the bitline structure 120, aligned with the sidewalls of the bitline structure 120. Since the multiple bitline structures BL have the same height along the Y direction, the sidewall structures 130 formed in this step also have the same height along the Y direction. The sidewall structures 130 may have a multi-layer structure, such as a first sidewall 131 (e.g., silicon oxide) and a second sidewall 132 (e.g., silicon nitride) stacked in sequence along the X direction.

[0048] like Figure 2 As shown, an insulating material layer 140 (e.g., silicon oxide, silicon nitride, etc.) is then filled between adjacent bitline structures BL using at least one of the above deposition processes, or further subjected to a chemical mechanical polishing (CMP) process, to ensure that the top surface of the insulating material layer 140 is flush with the top surface of the bitline structures BL. A photoresist layer 150 is then formed on the top surfaces of the insulating material layer 140 and the bitline structures BL. The photoresist layer 150 has an opening pattern therein, which is used to form a second bitline structure BL2 with a lower top surface among the multiple bitline structures BL.

[0049] like Figure 3 and Figure 4As shown, an etching process, such as at least one of a dry etching process and a wet etching process, is then used with the photoresist layer 150 as a mask to remove a portion of the height of the bitline structure BL below the opening pattern and portions of the insulating material layer 140 on both sides thereof. This allows the plurality of bitline structures BL with flush top surfaces to be formed into a plurality of first bitline structures BL1 and a plurality of second bitline structures BL2, each with top surfaces at different levels. The plurality of first bitline structures BL1 and the plurality of second bitline structures BL2 can be spaced apart from each other and alternately arranged along the X-direction. The insulating material layer 140 and the photoresist layer 150 are then further removed.

[0050] Afterwards, if you want to form Figure 7 The semiconductor device shown includes a plurality of bit line structures BL, a dielectric layer 160, a connection pad structure 180 and an isolation structure 190, and can be further referred to. Figure 5 , if you want to form Figure 8 The structure comprising a plurality of bit line structures BL, a plurality of contact structures SNC, a silicide layer 170, a connection pad structure 180 and an isolation structure 190 may be further referred to. Figure 6 The following will introduce the subsequent multiple figures in the order of first forming the semiconductor device in the first embodiment and then forming the semiconductor device in the second embodiment.

[0051] like Figure 5 As shown, a dielectric layer 160 (such as silicon oxide) can be further formed in the gap between the adjacent first bit line structure BL1 and the second bit line structure BL2 by using a deposition process, and the top surface of the dielectric layer 160 is set to be flush with the top surface of the first bit line structure BL1 in the bit line structure BL, so that it covers the top surfaces of the first bit line structure BL1 and the second bit line structure BL2. It should be understood that the top surface of the dielectric layer 160 in the embodiment of the present invention can be flush with the top surface of the second bit line structure BL2 in the bit line structure BL, or the top surface of the dielectric layer 160 can be flush with the top surface of the first bit line structure BL1 in the bit line structure BL, or the top surface of the dielectric layer 160 can also be between the top surface of the first bit line structure BL1 and the top surface of the second bit line structure BL2 in the bit line structure BL, but is not limited thereto. Figure 5 The figure is merely an example of the positional relationship between the top surface of the dielectric layer 160 and the top surface of the first bit line structure BL1 in the bit line structure BL in the embodiment of the present invention.

[0052] like Figure 7As shown, after the dielectric layer 160 is formed, a first connection pad layer 181 (e.g., titanium nitride) and a second connection pad layer 182 (e.g., metal tungsten) of the connection pad structure 180 can be further formed along at least the Y direction using the above deposition process. Specifically, the first connection pad layer 181 of the connection pad structure 180 is located on the dielectric layer 160 and the bitline structures BL. Thus, the first connection pad layer 181 is in direct contact with the first bitline structures BL1 that are exposed through the dielectric layer 160. The second connection pad layer 182 is located on the first connection pad layer 181, and its bottom surface is higher than the top surfaces of the multiple first bitline structures BL1. Next, a mask layer (not shown) is formed on the connection pad structure 180, wherein the mask layer has an isolation structure pattern therein. Using the mask layer as a mask, an etching process, such as a dry etching process or a wet etching process, is used to form grooves (i.e., the area corresponding to the isolation structure 190) along the Y direction in the mask layer, the connection pad structure 180, and a portion of the bit line structure BL on one side of the bit line structure BL, thereby exposing a portion of the sidewall structure 130. At this time, the multiple grooves separate the mask layer and the connection pad structure 180 along the X direction. Thereafter, an isolation material layer (e.g., silicon oxide or silicon nitride) is formed on the substrate 100, and the isolation material layer at least fills the multiple grooves, thereby forming the isolation structure 190 between adjacent connection pad structures 180. In which, the isolation structure 190 includes a first isolation structure 191 and a second isolation structure 192 separated from each other and alternately arranged along the X direction, and the bottom surface of the first isolation structure 191 extends to the first bit line structure BL1 to directly contact the corresponding first bit line structure BL1, and the bottom surface of a portion of the second isolation structure 192 extends to the second bit line structure BL2 and directly contacts the corresponding second bit line structure BL1, while the top surface of the remaining portion is isolated from the second bit line structure BL2, that is, there is a dielectric layer 160 between the bottom surface of a portion of the second isolation structure 192 and the top surface of the second bit line structure BL2, thereby forming the semiconductor device in the aforementioned first embodiment.

[0053] It should be understood that if the semiconductor device in the second embodiment is to be formed, Figure 4 After forming a plurality of first bit line structures BL1 and a plurality of second bit line structures BL2 separated from each other and alternately arranged along the X direction on the substrate 100, the Figure 6As shown, first, on the substrate 100 between the adjacent first bit line structure BL1 and the second bit line structure BL2, an etching process is used to etch downward along the Y direction to form a storage node contact groove (not shown) on the outside of the sidewall structure 130 after removing the isolation layer 110 and part of the substrate 100, and then a contact material layer (not shown) is formed to fully cover the substrate 100 and fill the storage node contact groove, and then an etching or flattening process is used to remove the contact material layer outside the storage node contact groove until the top surface of the bit line structure BL and the sidewall structure 130 are exposed, thereby obtaining contact structures SNC respectively located in the storage node contact groove. Among them, the contact material layer can be a silicon-containing semiconductor material, such as phosphorus-doped silicon. Then, a metal material layer (not shown) is deposited on the substrate 100, and the metal material layer and the substrate 100 and other structures are silicided to allow the top of the contact structure SNC, which is a silicon-containing semiconductor material, such as phosphorus-doped silicon, to react with the metal material layer to form a silicide layer 170, and obtain Figure 6 The structure shown.

[0054] Then, if Figure 8 As shown, a first connection pad material layer (e.g., titanium nitride) and a second connection pad material layer (e.g., metal tungsten) for the connection pad structure 180 are deposited on the substrate 100 using a deposition process and then etched to form a first connection pad layer 181 that wraps around the silicide layer 170, the first bitline structure BL1, and the second bitline structure BL2, and a second connection pad layer 182 that fills the gap between the adjacent first and second bitline structures BL1 and BL2 and has a top surface higher than the top surface of the first bitline structure BL1. This forms the connection pad structure 180 comprising the first and second connection pad layers 181 and 182 sequentially arranged from bottom to top. Subsequently, a mask layer (not shown) is formed on the connection pad structure 180, wherein the mask layer has an isolation structure pattern therein. Using the mask layer as a mask, an etching process is performed to form an isolation structure 190, whose bottom surface is in direct contact with the bitline structure BL, on the connection pad structure 180 and a portion of the bitline structure BL on one side of the bitline structure BL along the Y direction. Specifically, the isolation structure 190 includes a first isolation structure 191 and a second isolation structure 192 that are separated from each other and alternately arranged along the X direction, wherein the bottom surface of the first isolation structure 191 extends to the first bit line structure BL1 to directly contact the corresponding first bit line structure BL1, and the bottom surface of the second isolation structure 192 also extends to the second bit line structure BL2 to directly contact the corresponding second bit line structure BL2, thereby forming the semiconductor device in the aforementioned second embodiment.

[0055] To sum up, in the semiconductor device provided in the embodiment of the present invention, it may specifically include: a substrate, a plurality of bit line structures, which are arranged on the substrate and include a conductive layer and an insulating cover layer stacked in sequence from bottom to top, the bit line structure including a first bit line structure and a second bit line structure separated from each other and arranged alternately in the horizontal direction, and the top surface of the first bit line structure is higher than the top surface of the second bit line structure, a plurality of connection pad structures, which are arranged between adjacent bit line structures and extend in the horizontal direction to cover part of the top surface of the bit line structure, and a plurality of isolation structures, which are arranged between adjacent connection pad structures, including a first isolation structure located above the first bit line structure and a second isolation structure located above the second bit line structure.

[0056] In the present invention, by arranging multiple bit line structures in a semiconductor device into a first bit line structure and a second bit line structure with top surfaces at different horizontal heights in an alternating arrangement along the horizontal direction, the problems of top adhesion and leakage of adjacent bit line structures derived from the bit line structures with top surfaces at the same horizontal height as the size of the semiconductor device is reduced in the prior art are avoided, thereby improving the reliability and performance of the semiconductor device.

[0057] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0058] Each embodiment in this specification is described in a related manner. Similar portions between the various embodiments can be referenced to each other. Each embodiment focuses on the differences between the other embodiments. In particular, the device, electronic device, and computer-readable storage medium embodiments are generally similar to the method embodiments, so their descriptions are relatively simple. For related portions, reference can be made to the descriptions of the method embodiments.

[0059] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention are included in the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: substrate; a plurality of bit line structures disposed on the substrate, comprising a conductive layer and an insulating cap layer stacked sequentially from bottom to top, the bit line structures comprising a first bit line structure and a second bit line structure spaced apart from each other and alternately arranged in a horizontal direction, and a top surface of the first bit line structure being higher than a top surface of the second bit line structure; a plurality of connection pad structures, disposed between adjacent bit line structures and extending in a horizontal direction to cover a portion of the top surface of the bit line structure; A plurality of isolation structures are arranged between adjacent connection pad structures, including a first isolation structure located above the first bit line structure and a second isolation structure located above the second bit line structure.

2. The semiconductor device according to claim 1, wherein Top surfaces of the conductive layer of the first bit line structure and the conductive layer of the second bit line structure are located at the same level.

3. The semiconductor device according to claim 1, wherein The first isolation structure directly contacts the first bit line structure, and the second isolation structure and the second bit line structure are isolated from each other.

4. The semiconductor device according to claim 1, wherein The first isolation structure directly contacts the first bit line structure, and the second isolation structure directly contacts the second bit line structure.

5. The semiconductor device according to claim 4, wherein The first isolation structure and the second isolation structure extend to different depths of the first bit line structure and the second bit line structure.

6. The semiconductor device according to claim 1, wherein A bottom surface of the first isolation structure is lower than a bottom surface of the second isolation structure.

7. The semiconductor device according to claim 1, wherein A distance between a top surface of the first bit line structure and a top surface of the connection pad structure is smaller than a distance between a top surface of the second bit line structure and a top surface of the connection pad structure.

8. The semiconductor device according to claim 1, wherein Also includes: A dielectric layer is disposed on the substrate and covers a top surface of the second bit line structure.

9. The semiconductor device according to claim 8, wherein The dielectric layer and the top surface of the first bit line structure are located at the same level.

10. The semiconductor device according to claim 4, wherein Also includes: A plurality of contact structures are disposed under the connection pad structure and electrically connected to the substrate.

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