Semiconductor device
By introducing drain and source voltage divider structures into semiconductor devices, the problem of output power instability caused by temperature cycling in pulse working mode is solved, and more stable output power is achieved and the reliability of the device is improved.
Patent Information
- Application Number
- CN202422054739.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-22
- Publication Date
- 2025-08-12
- Estimated Expiration
- 2034-08-22
AI Technical Summary
In electronic detection applications, semiconductor devices are unstable in the output power due to temperature cycling in pulsed operation mode, affecting the detection range and effect.
The drain and source voltage divider structures are adopted to divide the channel area of the epitaxial layer through the drain and source voltage divider structures, adjust the temperature, reduce the temperature difference, and improve the output power stability.
Improves the output power stability of semiconductor devices and improves the reliability and operating performance of devices.
Smart Images
Figure CN223219404U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device. Background Art
[0002] In some electronic detection applications, pulsed operation is used to save power, reduce energy consumption, and extend system operation time. During this operation, the power amplifier chip experiences a cycle of "heating-freezing-heating-freezing," which directly causes the device temperature to constantly cycle between high and low temperatures. This, in turn, prevents the output power within the pulse from maintaining a constant state, severely impacting detection range and effectiveness. Utility Model Content
[0003] In view of this, the present application provides a semiconductor device, aiming to solve one of the technical problems in the prior art.
[0004] To achieve the above objectives, the technical solutions adopted in this application are as follows:
[0005] In a first aspect, an embodiment of the present application provides a semiconductor device, comprising:
[0006] substrate;
[0007] an epitaxial layer, disposed on the substrate;
[0008] An electrode layer is arranged on the epitaxial layer, the electrode layer includes a source, a drain and a gate arranged between the source and the drain, the epitaxial layer has a channel region electrically coupled to the source and the drain, the drain includes a drain interconnect layer and a drain voltage divider structure, the drain interconnect layer and the epitaxial layer are separated from each other and are respectively connected to the drain voltage divider structure, so that the drain interconnect layer is electrically coupled to the channel region of the epitaxial layer via the drain voltage divider structure.
[0009] In one embodiment of the first aspect, the drain voltage dividing structure is a positive temperature coefficient resistor film or a negative temperature coefficient resistor film.
[0010] In one of the embodiments of the first aspect, the semiconductor device further includes a passivation layer, the passivation layer is arranged on the epitaxial layer, a drain groove exposing the epitaxial layer is formed on the passivation layer, the drain voltage divider structure is arranged in the drain groove, and the drain interconnection layer is arranged at an end of the drain voltage divider structure away from the epitaxial layer to separate the drain interconnection layer and the passivation layer.
[0011] In one embodiment of the first aspect, an ion implantation region is formed on the surface of the epitaxial layer in the drain trench, and a side of the drain voltage divider structure away from the drain interconnect layer is electrically connected to the ion implantation region.
[0012] In one embodiment of the first aspect, a drain ohmic layer is formed on the surface of the epitaxial layer in the drain trench, and a side of the drain voltage divider structure away from the drain interconnect layer is electrically connected to the drain ohmic layer.
[0013] In one embodiment of the first aspect, there are an active area and a passive area, the passive area is arranged on the peripheral side of the active area, a grounding via is opened under the source of the active area, the grounding via passes through the epitaxial layer and the substrate, and the source is grounded through the grounding via.
[0014] In one embodiment of the first aspect, the source includes a source interconnect layer and a source voltage divider structure, the source interconnect layer and the epitaxial layer are separated from each other and are respectively connected to the source voltage divider structure, so that the source interconnect layer is electrically coupled to the channel region of the epitaxial layer via the source voltage divider structure.
[0015] In one embodiment of the first aspect, the source voltage dividing structure is a positive temperature coefficient temperature sensitive resistor film or a negative temperature coefficient temperature sensitive resistor film.
[0016] In one embodiment of the first aspect, there are an active area and a passive area, the passive area is arranged on the peripheral side of the active area, a grounding via is opened under the source electrode of the passive area, the grounding via penetrates the epitaxial layer and the substrate, and the source electrode is grounded through the grounding via.
[0017] In one embodiment of the first aspect, the source voltage divider structure and the drain voltage divider structure are both disposed in the active region of the epitaxial layer.
[0018] Compared with the prior art, the beneficial effects of the present application are as follows: the present application proposes a semiconductor device, comprising a substrate, an epitaxial layer and an electrode layer, the epitaxial layer being arranged on the substrate; the electrode layer being arranged on the epitaxial layer, the electrode layer comprising a source, a drain and a gate arranged between the source and the drain, the epitaxial layer having a channel region electrically coupled to the source and the drain, the drain comprising a drain interconnect layer and a drain voltage divider structure, the drain interconnect layer and the epitaxial layer being separated from each other and respectively connected to the drain voltage divider structure, so that the drain interconnect layer is electrically coupled to the channel region of the epitaxial layer via the drain voltage divider structure, the channel is voltage divided by the drain voltage divider structure, the temperature of the channel region of the epitaxial layer is adjusted, the temperature difference in the channel region is reduced, and the output power of the semiconductor device is more stable. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.
[0020] Figure 1 One of the structural schematic diagrams of semiconductor devices in some embodiments of the present application is shown;
[0021] Figure 2 Shown Figure 1 One of the cross-sectional structural diagrams at AA in the middle;
[0022] Figure 3 Shown Figure 1 The second schematic diagram of the cross-section structure at AA in the middle;
[0023] Figure 4 The second structural diagram of the semiconductor device in some embodiments of the present application is shown;
[0024] Figure 5 Shown Figure 4 Schematic diagram of the cross-sectional structure at the middle BB;
[0025] Figure 6 Shown Figure 1 One of the cross-sectional structural diagrams at CC in the middle;
[0026] Figure 7 Shown Figure 1 The second schematic diagram of the cross-section structure at CC in the middle;
[0027] Figure 8 Shown Figure 1 Schematic diagram of the cross-sectional structure at DD in the middle;
[0028] Figure 9 Shown Figure 4 Schematic diagram of the cross-sectional structure at EE;
[0029] Figure 10 One of the structural diagrams within the manufacturing process of a semiconductor device is shown;
[0030] Figure 11 The second structural diagram of the manufacturing process of the semiconductor device is shown;
[0031] Figure 12 The third structural diagram within the manufacturing process of a semiconductor device is shown;
[0032] Figure 13A fourth structural diagram showing a semiconductor device manufacturing process;
[0033] Figure 14 A fifth structural diagram showing a semiconductor device manufacturing process;
[0034] Figure 15 A sixth structural diagram showing a semiconductor device manufacturing process;
[0035] Figure 16 shows a schematic diagram of a chip structure with multiple channel regions;
[0036] Figure 17 A flowchart of the manufacturing process of a semiconductor device is shown.
[0037] Explanation of the main component symbols: 100-semiconductor device; 110-substrate; 120-epitaxial layer; 131-source; 132-drain; 133-gate; 121-channel region; 1321-drain interconnection layer; 1322-drain voltage divider structure; 140-passivation layer; 141-drain slot; 122-two-dimensional electron gas; 123-ion implantation region; 124-active region; 125-passive region; 126-ground via; 142-source slot; 1311-source interconnection layer; 1313-source ohmic layer; 1312-source voltage divider structure; 150-first photoresist layer; 151-first window; 161-second window; 160-second photoresist layer; 171-third window; 1323-drain ohmic layer; 200-chip. DETAILED DESCRIPTION
[0038] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.
[0039] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.
[0040] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.
[0041] In this application, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components or interactions between two components. Those skilled in the art will understand the specific meanings of these terms in this application based on specific circumstances.
[0042] In this application, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.
[0043] like Figure 1 and Figure 2 As shown, the embodiment of the present application provides a semiconductor device 100 that can reduce the temperature difference in the channel region 121, improve power droop, make the semiconductor output power constant, and improve the reliability of the semiconductor device 100.
[0044] The semiconductor device 100 includes a substrate 110 , an epitaxial layer 120 disposed on the substrate 110 , and an electrode layer disposed on the epitaxial layer 120 .
[0045] The substrate 110 is a base material for carrying semiconductor integrated circuit components, and the material may be sapphire, GaN, Si, SiC, etc.
[0046] An epitaxial layer 120 is epitaxially grown on the substrate 110. The epitaxial layer 120 may be formed by metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). This application does not limit this, and a reasonable selection may be made based on actual needs.
[0047] The epitaxial layer 120 can be one layer, two layers or multiple layers, and should be reasonably selected in combination with the device type when setting it. This application does not limit it.
[0048] The electrode layer includes a source electrode 131 , a drain electrode 132 , and a gate electrode 133 disposed between the source electrode 131 and the drain electrode 132 . The epitaxial layer 120 has a channel region 121 electrically coupled to the source electrode 131 and the drain electrode 132 .
[0049] like Figure 1 As shown, the source electrode 131 , the drain electrode 132 and the gate electrode 133 are spaced apart from each other, and the source electrode 131 , the gate electrode 133 and the drain electrode 132 are sequentially arranged in the length direction of the channel region 121 .
[0050] In some electronic detection applications, a pulsed operating mode is used. At the leading edge of the pulse, the device is still in a "cold" state, the temperature in the channel is still relatively low, and the channel current reaches its maximum value. At this point, the device begins to heat up, the channel temperature rises, and due to self-heating, the channel current slowly decreases until it reaches a stable state at thermal equilibrium. At the trailing edge of the pulse, the device is in a "hot" state, the channel temperature reaches its peak, and the channel current reaches its minimum value. After the pulse, no current flows through the device channel, and heat is dissipated to the outside world through the substrate, heat sink, etc., causing the channel temperature to continue to decrease, and the device slowly returns to a "cold" state.
[0051] During a pulse cycle, the temperature in the channel changes with the pulse phase, causing the semiconductor device to cycle through heat-off, heat-off, and heat-off. This causes the output power of the semiconductor device to be unstable during the pulse, affecting its performance.
[0052] In response to the above problems, Figure 2 and Figure 3 As shown, the drain 132 of the present application includes a drain interconnect layer 1321 and a drain voltage divider structure 1322. The drain interconnect layer 1321 and the epitaxial layer 120 are separated from each other and are respectively connected to the drain voltage divider structure 1322, so that the drain interconnect layer 1321 is electrically coupled to the channel region 121 via the drain voltage divider structure 1322, so that the drain interconnect layer 1321, the drain voltage divider structure 1322 and the channel region 121 of the epitaxial layer 120 are connected in series.
[0053] The drain interconnect layer 1321 and the epitaxial layer 120 are separated from each other, which means that the drain interconnect layer 1321 and the channel region 121 of the epitaxial layer 120 are spatially separated. The drain interconnect layer 1321 and the epitaxial layer 120 are not directly connected, but can only be connected to the epitaxial layer 120 through the drain voltage divider structure 1322, so that the drain voltage divider structure 1322 divides the voltage of the channel region 121 of the epitaxial layer 120.
[0054] Power droop refers to the difference between the transient output power at the leading edge of the pulse and the steady-state output power after the pulse.
[0055] In the early stage of the pulse, the drain voltage divider structure 1322 can reduce the voltage of the channel region 121, suppress the channel current spike, and delay the temperature rise of the channel region 121; in the late stage of the pulse, the drain voltage divider structure 1322 can compensate the channel current relative to the pulse front, so that the temperature curve fluctuation of the channel region 121 within the pulse period becomes smaller, and the difference between the transient output power of the semiconductor at the pulse front and the output power at the pulse trailing edge is reduced, thereby improving the power droop of the semiconductor device 100 and improving the reliability of the semiconductor device 100.
[0056] In some embodiments, the drain voltage dividing structure 1322 is a resistive film with a variable resistance value.
[0057] It should be understood that a variable resistance film is a resistor element that can change its resistance value. It is typically used to provide voltage division, adjust current, or change impedance. The resistance value of a variable resistance film can be adjusted manually (such as by turning a knob on a potentiometer) or in response to external signals (such as changes in temperature, pressure, or humidity).
[0058] In some embodiments, the drain voltage dividing structure 1322 is a temperature sensitive resistor film.
[0059] By setting the drain voltage-dividing structure 1322 as a temperature-sensitive resistor film and electrically connecting the temperature-sensitive resistor film to the channel region 121, the temperature-sensitive resistor can not only divide the voltage of the channel region 121, but also the voltage-dividing capability of the temperature-sensitive resistor film can be adaptively adjusted as the temperature of the channel region 121 changes, thereby adjusting the output power of the semiconductor device 100.
[0060] The drain voltage dividing structure 1322 is a positive temperature coefficient resistor film or a negative temperature coefficient resistor film.
[0061] like Figure 16 As shown, in a device having multiple channel regions 121, the chip 200 has a larger area, the channel region 121 located in the middle of the chip 200 has poor heat dissipation, and the temperature rises more under the same power, while the channel region 121 located at the edge of the chip 200 has better heat dissipation and the temperature rises less under the same power.
[0062] At this time, the drain voltage divider structures 1322 in the middle and at the edges of the chip 200 both use positive temperature coefficient resistor films. As a result, the temperature of the channel region 121 in the middle of the chip 200 is high, and the drain voltage divider structure 1322 in the middle has a large resistance value, significantly dividing the voltage in the middle channel region 121. This reduces the current in the middle channel region 121 and slows down the temperature rise of the middle channel region 121 of the chip 200.
[0063] The channel region 121 at the edge of the chip 200 is not densely distributed. When the temperature of the channel region 121 at the edge of the chip 200 is low, the resistance value of the drain voltage divider structure 1322 at the edge is small, the voltage divided on the channel region 121 at the edge is small, and the current in the channel region 121 at the edge increases, causing the temperature of the channel region 121 at the edge of the chip 200 to rise more.
[0064] By setting positive temperature coefficient sensitive resistors, adaptive adjustment can be performed on various parts of the chip 200 having multiple channel regions 121 in the spatial dimension, reducing the temperature difference between the central channel region 121 and the edge channel region 121 of the chip 200, and improving the power droop of the chip 200.
[0065] When the pulse time of the chip 200 is short and the duty cycle is small, the working time of the chip 200 is short, and the heat generated by each channel area 121 during each pulse time can be dissipated. Therefore, there is no significant difference in the temperature of the channel area 121 in the middle and edge of the chip 200. The top drop is mainly reduced by reducing the power difference between the front and rear edges of the pulse.
[0066] In this way, at the leading edge of the pulse, the temperature of the channel region 121 is low, the resistance value of the drain voltage divider structure 1322 is large, the voltage divided on the channel region 121 is obvious, the current in the channel region 121 cannot reach saturation, and the temperature rise of the channel region 121 is small; at the trailing edge of the pulse, the temperature of the channel region 121 rises, the resistance value of the drain voltage divider structure 1322 decreases, the voltage divided on the channel region 121 is small, and the current in the channel region 121 increases compared to the leading edge, so as to offset the current drop caused by self-heating.
[0067] By setting a negative temperature coefficient sensitive resistor, the temperature of the channel region 121 can be adaptively adjusted in the time dimension, reducing the temperature difference between the channel region 121 at the pulse front and the pulse trailing edge, thereby reducing the difference between the semiconductor's transient output power at the pulse front and the output power after the pulse, improving the power droop of the semiconductor device 100, and improving the reliability of the semiconductor device 100.
[0068] In some embodiments, as Figure 2 and Figure 3 As shown, the semiconductor device 100 further includes a passivation layer 140 , which is disposed on the epitaxial layer 120 .
[0069] The passivation layer 140 can be formed by plasma enhanced chemical vapor deposition (PECVD) or atomic layer epitaxy (ALD) to grow SiN on the surface of the epitaxial layer 120. The SiN forms dangling bonds with the surface of the epitaxial layer 120 to passivate the surface of the epitaxial layer 120.
[0070] A drain groove 141 exposing the epitaxial layer 120 is formed on the passivation layer 140 , a drain voltage divider structure 1322 is arranged in the drain groove 141 , and a drain interconnection layer 1321 is arranged at one end of the drain voltage divider structure 1322 away from the epitaxial layer 120 to separate the drain interconnection layer 1321 and the passivation layer 140 .
[0071] The separation of the drain interconnect layer 1321 and the passivation layer 140 means that the drain interconnect layer 1321 and the passivation layer 140 are spatially separated, and the drain interconnect layer 1321 and the passivation layer 140 are not directly connected. The drain interconnect layer 1321 and the passivation layer 140 can only be connected to the passivation layer 140 through the drain voltage divider structure 1322, so that the current flowing through the drain interconnect layer 1321 flows entirely to the drain voltage divider structure 1322.
[0072] like Figure 2 As shown, in the length direction of the channel region 121, the length of the drain voltage divider structure 1322 is not less than the length of the drain interconnection layer 1321. In this way, the drain interconnection layer 1321 is stacked on the drain voltage divider structure 1322, so that the surface of the drain interconnection layer 1321 is only in contact with the drain voltage divider structure 1322, so that all the current of the drain interconnection layer 1321 flows to the epitaxial layer 120 through the drain voltage divider structure 1322.
[0073] In some embodiments, Figure 2 and Figure 6 As shown, a two-dimensional electron gas 122 (2DEG) is provided on the surface of the active region 124 of the epitaxial layer 120, and ion implantation is performed on the surface of the epitaxial layer 120 exposed at the drain groove 141 to form an ion implantation region 123, so that the epitaxial layer 120 in the drain groove 141 has ohmic characteristics, and the drain voltage divider structure 1322 contacts the epitaxial layer 120 to form an electrical connection.
[0074] It should be understood that in semiconductor materials, two-dimensional electron gas 122 refers to the accumulation of electrons at the interface of the material due to band discontinuity at the interface of the heterostructure, which creates a potential barrier that restricts electron movement in the direction perpendicular to the interface. The term "two-dimensional" refers to the fact that the accumulated electrons can move freely, forming a current in the lateral direction, while the vertical current is suppressed.
[0075] Ion implantation is used to precisely control the electrical properties of semiconductor materials by accelerating charged impurity ions to the surface of semiconductor materials.
[0076] In some embodiments, as Figure 3 and Figure 7 As shown, a drain ohmic layer 1323 is disposed in the drain trench 141 .
[0077] The drain ohmic layer 1323 is electrically connected to the epitaxial layer 120 , the drain voltage divider structure 1322 is disposed on the drain ohmic layer 1323 , and the drain interconnect layer 1321 is disposed on the drain voltage divider structure 1322 , so that the drain interconnect layer 1321 is electrically coupled to the drain ohmic layer 1323 via the drain voltage divider structure 1322 .
[0078] It should be understood that the drain ohmic layer 1323 can be an ohmic metal evaporated on the drain groove 141, and the ohmic metal is subjected to a high-temperature heat treatment process, so that the epitaxial layer is alloyed to form the drain ohmic layer 1323, so that the drain ohmic layer 1323 is electrically connected to the epitaxial layer 120 and the drain voltage divider structure 1322 respectively.
[0079] In some embodiments, as Figure 1 and Figure 4 As shown, the semiconductor device 100 has an active area 124 and a passive area 125. The passive area 125 is arranged on the peripheral side of the active area 124. A grounding via 126 is opened under the source 131 of the active area 124. The grounding via 126 passes through the epitaxial layer 120 and the substrate 110. The source 131 is grounded through the grounding via 126.
[0080] The two-dimensional electron gas 122 exists in the active region 124, and the two-dimensional electron gas 122 does not exist in the passive region 125. The active region 124 is in a continuous state, and the passive region 125 is arranged around the active region 124.
[0081] like Figures 1 to 3 As shown, when the ground via 126 is set at the source 131 of the active area 124, a source groove 142 exposing the epitaxial layer 120 is provided on the passivation layer 140, and the source 131 includes a source interconnect layer 1311 and a source ohmic layer 1313, and the source interconnect layer 1311 and the source ohmic layer 1313 are in direct contact.
[0082] The method of forming the ion implantation region 123 by ion implantation in the source trench 142 or forming the source ohmic layer 1313 by high temperature sintering of the ohmic metal alloy is the same as that of the drain 132 and will not be described in detail here.
[0083] like Figure 1 and Figure 8 As shown, when the ISV (In-Source VIA) process is adopted, the ground via 126 is inside the active area 124, and the ground via 126 is directly connected to the source 131. The current does not pass through the source 131 interconnection metal. Therefore, the source 131 does not need to be provided with a source voltage divider structure 1312, and only a drain voltage divider structure 1322 is provided at the drain 132, thereby improving the top drop problem of the semiconductor device 100.
[0084] It should be understood that Figure 4 and Figure 9 As shown, when the OSV (Out-Source VIA) process is adopted, the current needs to flow through the source interconnection layer 1311. Therefore, a source voltage divider structure 1312 is set at the source 131 to further enhance the voltage dividing capability of the channel region 121, improve the power droop, stabilize the semiconductor output power, and improve the reliability of the semiconductor device 100.
[0085] In some embodiments, as Figure 5 As shown, the source 131 includes a source interconnect layer 1311 and a source voltage divider structure 1312. The source interconnect layer 1311 and the epitaxial layer 120 are separated from each other and are respectively connected to the source voltage divider structure 1312, so that the source interconnect layer 1311 is electrically coupled to the channel region 121 via the source voltage divider structure 1312, so that the source interconnect layer 1311, the source voltage divider structure 1312 and the channel region 121 of the epitaxial layer 120 are connected in series.
[0086] The source interconnect layer 1311 and the epitaxial layer 120 are separated from each other, which means that the source interconnect layer 1311 and the channel region 121 of the epitaxial layer 120 are spatially separated. The source interconnect layer 1311 and the epitaxial layer 120 are not directly connected, but can only be connected to the epitaxial layer 120 through the source voltage divider structure 1312, so that the source voltage divider structure 1312 divides the voltage of the channel region 121 of the epitaxial layer 120.
[0087] In some embodiments, the source voltage dividing structure 1312 is a resistive film with a variable resistance value.
[0088] In some embodiments, the source voltage divider structure 1312 is a temperature-sensitive resistor film, for example, a positive temperature coefficient temperature-sensitive resistor film or a negative temperature coefficient temperature-sensitive resistor film.
[0089] Among them, when the source voltage divider structure 1312 is a positive temperature coefficient resistor film, its function is the same as that of the drain voltage divider structure 1322. It can adaptively adjust the temperature of the channel region 121 from the spatial dimension, improve the power drop of the semiconductor device 100, and improve the reliability of the semiconductor device 100. It will not be repeated here.
[0090] Of course, when the source voltage divider structure 1312 is a negative temperature coefficient resistor film, its function is the same as that of the drain voltage divider structure 1322. It can adaptively adjust the temperature of the channel region 121 from the time dimension, improve the power drop of the semiconductor device 100, and improve the reliability of the semiconductor device 100. It will not be repeated here.
[0091] In some embodiments, as Figure 4 and Figure 9As shown, when the OSV process is adopted and the current needs to flow through the source interconnection layer 1311, a grounding via 126 is opened under the source 131 of the passive area 125. The grounding via 126 passes through the epitaxial layer 120 and the substrate 110. The grounding via 126 is connected to the source interconnection layer 1311, and the source 131 is grounded through the grounding via 126.
[0092] In some embodiments, as Figures 6 to 9 As shown, the source voltage divider structure 1312 and the drain voltage divider structure 1322 are both disposed in the active region 124 of the epitaxial layer 120 .
[0093] The active region 124 is the region of the device that directly participates in current transmission, while the passive region 125 does not directly participate in the device's current transmission process. Both the source voltage divider structure 1312 and the drain voltage divider structure 1322 are disposed in the active region 124 of the epitaxial layer 120 , enabling both the source voltage divider structure 1312 and the drain voltage divider structure 1322 to effectively divide the voltage in the channel region 121 of the epitaxial layer 120 .
[0094] like Figure 17 As shown, an embodiment of the present application provides a method for manufacturing a semiconductor device 100, comprising:
[0095] Step S10 , growing an epitaxial layer 120 on the substrate 110 .
[0096] like Figure 10 As shown, a substrate 110 is first provided. The substrate 110 may be sapphire or silicon carbide, etc., and then epitaxial growth is performed on the substrate 110 to form an epitaxial layer 120.
[0097] In step S20 , a first photoresist layer 150 is formed on the epitaxial layer 120 , and the first photoresist layer 150 is etched to define a first window 151 exposing the epitaxial layer 120 , and then the first photoresist layer 150 is removed.
[0098] The first window 151 is used to make the epitaxial layer 120 therein have ohmic characteristics.
[0099] Specifically, such as Figure 11 As shown, the ohmic characteristics can be formed by evaporating an ohmic metal layer covering the first window 151 on the entire surface of the first photoresist layer 150, and then stripping the ohmic metal layer on the first photoresist layer 150, while retaining the ohmic metal layer in the first window 151, thereby obtaining the drain ohmic layer 1323. It should be understood that after the stripping process, a high-temperature heat treatment process is required to allow the ohmic metal layer to react with the epitaxial layer, thereby alloying the epitaxial layer, and thus forming an ohmic contact between the ohmic metal of the drain 132 and the epitaxial layer 120.
[0100] Alternatively, the ohmic characteristic can be formed by performing ion implantation on the surface of the epitaxial layer 120 within the first window 151, so that the epitaxial layer 120 within the first window 151 has ohmic characteristics. It should be noted that when ion implantation is used, in step S10, a two-dimensional electron gas 122 is formed on the surface of the epitaxial layer 120.
[0101] In step S30 , the passivation layer 140 is continuously epitaxially grown on the epitaxial layer 120 , and the passivation layer 140 is etched to define a second window 161 exposing the epitaxial layer 120 having ohmic characteristics.
[0102] Among them, such as Figure 2 and Figure 12 As shown, in the length direction of the channel region 121, the length of the second window 161 is smaller than that of the first window 151, and the second window 161 and the first window 151 cooperate to form a stacked hole structure so that the drain voltage divider structure 1322 subsequently formed in the second window 161 only contacts the epitaxial layer 120 with ohmic characteristics, and does not contact other parts of the epitaxial layer 120.
[0103] It should be understood that in some embodiments, when etching the second window 161 , windows for forming the source 131 and the gate 133 may be simultaneously etched.
[0104] In step S40 , a second photoresist layer 160 is formed on the passivation layer 140 , and the second photoresist layer 160 is etched to define a third window 171 exposing the epitaxial layer 120 and the passivation layer 140 .
[0105] Among them, such as Figure 2 and Figure 13 As shown, in the length direction of the channel region 121 , the length of the third window 171 is greater than that of the second window 161 , and the third window 171 and the second window 161 cooperate to form a stacked hole structure, and the edge of the third window 171 does not overlap with the edge of the second window 161 .
[0106] In step S50 , the drain voltage divider structure 1322 is grown in the third window 171 and the second window 161 , and then the second photoresist layer 160 is removed.
[0107] Among them, such as Figure 14 As shown, the drain voltage divider structure 1322 is deposited by chemical vapor deposition to form a resistive film on the surface of the drain ohmic layer 1323 , the surface of the second window 161 of the passivation layer 140 , and the surface of the third window 171 of the second photoresist layer 160 .
[0108] It should be understood that in steps S30 to S50 , when the source voltage dividing structure 1312 needs to be provided, the manufacturing process of the source voltage dividing structure 1312 is synchronized with the manufacturing process of the drain voltage dividing structure 1322 .
[0109] In step S60, a third photoresist layer (not shown) is formed on the passivation layer 140, and the third photoresist layer is etched to define a fourth window (not shown) exposing the drain voltage divider structure 1322 to form a drain interconnect layer 1321, and then the third photoresist layer is removed.
[0110] Among them, such as Figure 15 As shown, the length of the fourth window is no greater than that of the third window 171 , a drain interconnection layer 1321 is formed in the fourth window, and then the third photoresist layer is removed.
[0111] It should be noted that the source interconnect layer 1311 and the drain interconnect layer 1321 can be formed in a single step. That is, the source interconnect layer 1311 and the drain interconnect layer 1321 can be obtained by vapor-depositing an interconnect metal covering the third window 171 and the fourth window on the entire surface of the third photoresist layer, and then stripping the third photoresist layer while retaining the interconnect metal located in the third window 171 and the fourth window.
[0112] The gate electrode 133 may be formed in one step with the source interconnection layer 1311 and the drain interconnection layer 1321 , or may be formed separately, and there is no particular limitation.
[0113] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.
[0114] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.
Claims
1. A semiconductor device, characterized in that: include: substrate; an epitaxial layer, disposed on the substrate; An electrode layer is arranged on the epitaxial layer, the electrode layer includes a source, a drain and a gate arranged between the source and the drain, the epitaxial layer has a channel region electrically coupled to the source and the drain, the drain includes a drain interconnect layer and a drain voltage divider structure, the drain interconnect layer and the epitaxial layer are separated from each other and are respectively connected to the drain voltage divider structure, so that the drain interconnect layer is electrically coupled to the channel region of the epitaxial layer via the drain voltage divider structure.
2. The semiconductor device according to claim 1, wherein The drain voltage dividing structure is a positive temperature coefficient resistor film or a negative temperature coefficient resistor film.
3. The semiconductor device according to claim 1 or 2, wherein: The semiconductor device also includes a passivation layer, which is arranged on the epitaxial layer. A drain groove exposing the epitaxial layer is formed on the passivation layer. The drain voltage divider structure is arranged in the drain groove. The drain interconnect layer is arranged at an end of the drain voltage divider structure away from the epitaxial layer to separate the drain interconnect layer and the passivation layer.
4. The semiconductor device according to claim 3, wherein An ion implantation region is formed on the surface of the epitaxial layer in the drain groove, and a side of the drain voltage divider structure away from the drain interconnection layer is electrically connected to the ion implantation region.
5. The semiconductor device according to claim 3, wherein A drain ohmic layer is formed on the surface of the epitaxial layer in the drain groove, and a side of the drain voltage divider structure away from the drain interconnection layer is electrically connected to the drain ohmic layer.
6. The semiconductor device according to claim 3, wherein The device comprises an active region and a passive region, wherein the passive region is arranged around the active region, a grounding via is provided below the source of the active region, the grounding via penetrates the epitaxial layer and the substrate, and the source is grounded through the grounding via.
7. The semiconductor device according to claim 3, wherein The source includes a source interconnect layer and a source voltage divider structure. The source interconnect layer and the epitaxial layer are separated from each other and are respectively connected to the source voltage divider structure so that the source interconnect layer is electrically coupled to the channel region of the epitaxial layer via the source voltage divider structure.
8. The semiconductor device according to claim 7, wherein: The source voltage dividing structure is a positive temperature coefficient temperature sensitive resistor film or a negative temperature coefficient temperature sensitive resistor film.
9. The semiconductor device according to claim 7, wherein: The invention has an active area and a passive area, wherein the passive area is arranged around the active area, a grounding via is opened under the source of the passive area, the grounding via passes through the epitaxial layer and the substrate, and the source is grounded through the grounding via.
10. The semiconductor device according to claim 9, wherein The source voltage-dividing structure and the drain voltage-dividing structure are both arranged in the active region of the epitaxial layer.