V-shaped gate silicon carbide VDMOS with low gate charge
By adopting V-type gate structure and P-type well region design in silicon carbide VDMOS devices, the problem of high gate charge is solved, and a low gate charge device is realized, and switching speed and reliability are improved.
Patent Information
- Application Number
- CN202421685753.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-16
- Publication Date
- 2025-08-12
- Estimated Expiration
- 2034-07-16
AI Technical Summary
The existing silicon carbide VDMOS devices have high gate charge, resulting in large switching losses, making it difficult to meet the requirements of high frequency, high efficiency and high power density.
Using the V-type gate device structure, the P-type well region is constructed at the gate, and the gate inversion thickness is reduced, combined with the N-type homogeneous layer design, the gate charge is reduced, and the electric field concentration area is formed at the sharp gate to construct protection to optimize the current distribution.
It effectively reduces the gate charge of the device, increases the switching speed, reduces switching losses, and improves the reliability and current sharing ability of the device.
Smart Images
Figure CN223219405U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a V-type gate silicon carbide VDMOS with low gate charge. Background Art
[0002] Silicon carbide (VDMOS) is a typical example of a silicon carbide power device, widely used in electric vehicles, aerospace, power conversion, and other fields. As power systems demand ever-increasing power density, the operating frequency of silicon carbide VDMOS is also increasing. This requires the device's gate charge to be as low as possible to reduce switching losses, increase switching speed, and achieve high frequency, high efficiency, and high power density. However, the gate charge of existing devices is still relatively high, necessitating an urgent need to reduce this. Utility Model Content
[0003] The technical problem to be solved by the present invention is to provide a V-gate silicon carbide VDMOS with low gate charge. It adopts a V-gate device structure, requires less inversion thickness for gate control, has small gate charge, and can effectively improve the switching speed of the device.
[0004] The utility model is implemented as follows: a V-type gate silicon carbide VDMOS with low gate charge, comprising:
[0005] Silicon carbide substrate,
[0006] a drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate, and a current balancing layer is provided in the drift layer;
[0007] A P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the drift layer;
[0008] A P-type well region, wherein the lower side of the P-type well region is connected to the upper side of the drift layer;
[0009] An N-type source region, wherein the lower side of the N-type source region is connected to the P-type well region;
[0010] an insulating dielectric layer, the insulating dielectric layer being V-shaped and connected to the P-type well region and the N-type source region respectively; and a V-shaped groove being provided in the insulating dielectric layer;
[0011] a source metal layer, the source metal layer being connected to the P-type source region and the N-type source region respectively;
[0012] a gate metal layer, the gate metal layer being disposed in the V-shaped groove;
[0013] and a drain metal layer connected to the lower side of the silicon carbide substrate.
[0014] The advantages of the present invention are:
[0015] 1. The device adopts a V-type gate device structure. The gate control requires less inversion thickness and smaller gate charge, which can effectively improve the switching speed of the device.
[0016] Second, the V-type gate is prone to form electric field concentration at the sharp part of the gate of the device, which in turn affects the gate reliability. However, the present invention constructs a P-type well region at the sharp part of the gate, which can effectively suppress the electric field concentration in this area.
[0017] 3. The source metal layer of the device is in direct contact with the P-type source region, and the P-type source region is in direct contact with the N-type drift layer without passing through the P-type well region, which can reduce the conduction loss of the body diode;
[0018] Fourth, the N-type current-sharing layer of the device is distributed in the N-type drift layer, close to the P-type well region, but there is a 300nm thick N-type drift layer between the P-type well region. This can avoid the N-type current-sharing protecting the sharp part of the P-type well region on the gate while balancing the current from the gate. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0020] Figure 1 This is a schematic diagram of a V-type gate silicon carbide VDMOS with low gate charge according to the present invention.
[0021] Figure 2 The present invention is a flow chart of a method for preparing a V-type gate silicon carbide VDMOS with low gate charge.
[0022] Figure 3 This is a cross-sectional view of the process of a low gate charge V-gate silicon carbide VDMOS in this utility model. Figure 1 .
[0023] Figure 4 This is a cross-sectional view of the process of a low gate charge V-gate silicon carbide VDMOS in this utility model. Figure 2 .
[0024] Figure 5 This is a cross-sectional view of the process of a low gate charge V-gate silicon carbide VDMOS in this utility model. Figure 3 .
[0025] Figure 6 This is a cross-sectional view of the process of a low gate charge V-gate silicon carbide VDMOS in this utility model. Figure 4 .
[0026] Figure 7 This is a cross-sectional view of the process of a low gate charge V-gate silicon carbide VDMOS in this utility model. Figure 5 .
[0027] Figure 8This is a cross-sectional view of the process of a low gate charge V-gate silicon carbide VDMOS in this utility model. Figure 6 .
[0028] Figure 9 This is a cross-sectional view of the process of a low gate charge V-gate silicon carbide VDMOS in this utility model. Figure 7 .
[0029] Figure 10 This is a cross-sectional view of the process of a low gate charge V-gate silicon carbide VDMOS in this utility model. Figure 8 .
[0030] Figure 11 This is a cross-sectional view of the process of a low gate charge V-gate silicon carbide VDMOS in this utility model. Figure 9 .
[0031] Figure 12 This is a cross-sectional view of the process of a low gate charge V-gate silicon carbide VDMOS in this utility model. Figure 10 . DETAILED DESCRIPTION
[0032] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.
[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.
[0034] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "in contact with," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.
[0035] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of one element or feature to other elements or features depicted in the figures. It should be understood that, in addition to the orientations depicted in the figures, spatially relative terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped over, an element or feature described as "under" or "beneath" or "beneath" the other elements would be oriented "over" the other elements or features. Thus, the exemplary terms "under" and "under" may encompass both the upper and lower orientations. Additionally, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.
[0036] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0037] like Figure 1 As shown, the embodiment of the present application provides a low gate charge V-gate silicon carbide VDMOS, including:
[0038] Silicon carbide substrate 1,
[0039] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1, and a current balancing layer 21 is provided in the drift layer 2;
[0040] A P-type source region 3, wherein the lower side of the P-type source region 3 is connected to the upper side of the drift layer 2;
[0041] A P-type well region 4, wherein the lower side of the P-type well region 4 is connected to the upper side of the drift layer 2;
[0042] An N-type source region 5 , wherein the lower side of the N-type source region 5 is connected to the P-type well region 4 ;
[0043] an insulating dielectric layer 6 , wherein the insulating dielectric layer 6 is V-shaped and connects the P-type well region 4 and the N-type source region 5 ; a V-shaped groove 61 is provided in the insulating dielectric layer 6 ;
[0044] a source metal layer 7, the source metal layer 7 being connected to the P-type source region 3 and the N-type source region 5 respectively;
[0045] a gate metal layer 8 disposed in the V-shaped groove 61;
[0046] and a drain metal layer 9, wherein the drain metal layer 9 is connected to the lower side of the silicon carbide substrate 1;
[0047] A V-shaped groove 41 is defined in the N-type source region 5 and the P-type well region 4 , and the insulating dielectric layer 6 is disposed in the V-shaped groove 41 .
[0048] like Figures 2 to 12 As shown, the method for preparing the above-mentioned VDMOS includes the following steps:
[0049] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 9; epitaxially growing on the silicon carbide substrate 1 to form a drift layer 2;
[0050] Step 2: forming a current-balancing layer 21 in the drift layer 2 by ion implantation, with an ion implantation energy of 300-400 keV;
[0051] Step 3: forming a barrier layer a on the drift layer 2, etching the barrier layer a to form a through hole, and forming a P-type well region 4 in the drift layer 2 by ion implantation, with an ion implantation energy of 200-300 keV;
[0052] Step 4: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and form a P-type source region 3 in the drift layer 2 by ion implantation, with an ion implantation energy of 200-300 keV;
[0053] Step 5: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and form an N-type source region 5 in the drift layer 2 by ion implantation, with an ion implantation energy of 10-200 keV;
[0054] Step 6: Remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and then wet-etch the N-type source region 5 and the P-type well region 4 to form a V-shaped groove 41; then, dry oxygen oxidation is performed in the V-shaped groove 41 to form an insulating dielectric layer 6, and the insulating dielectric layer 6 has a V-shaped groove 61.
[0055] Step 7: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, deposit metal, and form a gate metal layer 8;
[0056] Step 8: Remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and etch the drift layer 2 until the upper side of the P-type source region 3, deposit metal to form a source metal layer 7, and then remove the barrier layer a to complete the preparation.
[0057] The silicon carbide substrate 1 is N-type, and its doping concentration is 2e18cm -3 The drift layer 2 is N-type, and its doping concentration is 2e16cm -3 The current-distributing layer 21 is of N-type with a doping concentration of 6e17cm -3 The doping concentration of the P-type source region 3 is 8e18cm -3 The doping concentration of the P-type well region 4 is 1e17cm -3 The doping concentration of the N-type source region 5 is 2e18cm -3 The insulating dielectric layer 6 is made of silicon dioxide, and the gate metal layer 8, the source metal layer 7, and the drain metal layer 9 are all made of Al. The thickness of the N-type silicon carbide substrate 1 of the device is 1 μm, the thickness of the N-type drift layer 2 is 10-20 μm, the thickness of the N-type current-balancing layer 21 is 300 nm, the distance from the upper side of the N-type current-balancing layer 21 to the upper side of the N-type drift layer 2 is 300 nm, the thickness of the P-type source region 3 is 300 nm, the thickness of the P-type well region 4 is 300 nm, the distance from the bottom of the P-type well region 4 to the bottom of the insulating dielectric layer is 50 nm, the thickness of the N-type source region 5 is 600 nm, the thickness of the source metal layer 7 is 600 nm, the sidewall thickness of the insulating dielectric layer 6 is 20 nm, and the device withstand voltage is 800-1200 V.
[0058] The concentration of the N-type silicon carbide substrate 1 is to form a low-resistance ohmic contact with the drain metal layer 9, thereby reducing the on-resistance of the device. Its thickness is based on the design conditions of the device epitaxial thickness (N-type drift layer 2) to ensure support and improve process stability. The thickness and doping concentration of the N-type drift layer 2 are a compromise between on-resistance and withstand voltage. The P-type source region 3 is designed to reduce the on-resistance of the device body diode and improve the freewheeling capability of the body diode. The N-type current balancing layer 21 is to reduce the on-resistance of the device and realize the equalization of the current inside the device. Its concentration, thickness and position relationship are to realize the electrons from the N-type source region 5 through the inverted P-type well region 4 into the N-type drift layer 2 above the N-type current balancing layer 21. When entering the position of the N-type current balancing layer 21, the lateral resistance value is smaller and the lateral diffusion of the current is greater, thereby avoiding the current concentration in the middle area of the device and improving the reliability of the device.
[0059] When the device is turned off, the gate is at zero voltage, the drain is subjected to high voltage, and the space charge region constructed by the N-type drift layer 2, the P-type well region 4, and the P-type source region 3 is subjected to high voltage; when a positive voltage is applied to the device gate, the P-type well region 4 is inverted near the gate insulating dielectric layer 6, forming a conductive channel along the insulating dielectric layer 6 to achieve conduction. Since the inversion is only in the P-type well region 4, and the N-type current-sharing layer 21 completes the electric field shielding of the gate to the drain, the gate-drain capacitance and the gate-source capacitance are reduced, and the gate charge of the device is reduced;
[0060] The utility model constructs a P-type well region at the sharp corner of the gate, thereby protecting the sharp corner of the gate and improving the reliability of the device on the basis of ensuring that the gate charge of the device is reduced.
[0061] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.
Claims
1. A low gate charge V-gate silicon carbide VDMOS, characterized by: include: Silicon carbide substrate, a drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate, and a current balancing layer is provided in the drift layer; A P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the drift layer; A P-type well region, wherein the lower side of the P-type well region is connected to the upper side of the drift layer; An N-type source region, wherein the lower side of the N-type source region is connected to the P-type well region; an insulating dielectric layer, the insulating dielectric layer being V-shaped and connected to the P-type well region and the N-type source region respectively; and a V-shaped groove being provided in the insulating dielectric layer; a source metal layer, the source metal layer being connected to the P-type source region and the N-type source region respectively; a gate metal layer, the gate metal layer being disposed in the V-shaped groove; and a drain metal layer connected to the lower side of the silicon carbide substrate.
2. The low gate charge V-gate silicon carbide VDMOS according to claim 1, wherein: The distance between the upper side of the current balancing layer and the upper side of the drift layer is 300 nm.
3. The low gate charge V-gate silicon carbide VDMOS according to claim 1, wherein: A V-shaped groove is provided in the N-type source region and the P-type well region, and the insulating dielectric layer is provided in the V-shaped groove.
4. The low gate charge V-gate silicon carbide VDMOS according to claim 1, wherein: The sidewall thickness of the insulating dielectric layer is 20 nm.
5. The low gate charge V-gate silicon carbide VDMOS according to claim 1, wherein: The thickness of the flow-balancing layer is 300 nm.