Symmetrical multi-chip parallel silicon carbide power module packaging structure
Through the symmetric multi-chip parallel silicon carbide power module packaging structure, the problem of high parasitic inductance of silicon carbide power chip circuit is solved, the module is high reliability and low-cost production are achieved, and the application range is expanded.
Patent Information
- Application Number
- CN202422254955.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-13
- Publication Date
- 2025-08-15
- Estimated Expiration
- 2034-09-13
AI Technical Summary
The existing silicon carbide power chips have higher overall loop parasitic inductance and lower overall module reliability.
The symmetrical multi-chip parallel silicon carbide power module packaging structure is adopted, including the connection between the upper ceramic substrate and the lower ceramic substrate, the silicon carbide power chip is connected through copper blocks and solder layers, the copper blocks and terminals are connected using bonding wires, and nano-silver sintered material and epoxy resin are used to reduce heat accumulation.
It reduces the overall loop parasitic inductance, improves the reliability and flexibility of the module, reduces manufacturing costs, and can use multiple silicon carbide power chips at the same time, enhancing the scope of application of the module.
Smart Images

Figure CN223230345U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of power electronic devices, in particular to a symmetrical multi-chip parallel silicon carbide power module packaging structure. Background Art
[0002] Power semiconductor devices, as core components for controlling and converting electrical energy, are widely used in power management, automotive electronics, industrial control, wastewater treatment, renewable energy and other fields, playing an indispensable role in various occasions and working conditions.
[0003] Silicon carbide, a representative of third-generation semiconductor materials, boasts advantages such as high temperature, high speed, high efficiency, and high reliability, earning it the nickname "the rising star of future power electronics." Compared to first- and second-generation semiconductor materials, third-generation semiconductor materials exhibit significant advantages in high-temperature, high-voltage, high-power, and high-frequency applications, thanks to their wider bandgap, higher breakdown voltage, and higher electrical and thermal conductivity. They are gradually replacing the first two generations of semiconductor materials and have gained industry recognition for the widespread application and market growth of power devices made from them. They are the most widely used foundational material for future semiconductor power devices. However, existing silicon carbide power chips have high overall loop parasitic inductance, resulting in low overall module reliability. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide a symmetrical multi-chip parallel silicon carbide power module packaging structure to solve the above problems.
[0005] The utility model solves the above technical problems with a technical solution: a symmetrical multi-chip parallel silicon carbide power module packaging structure, comprising an upper ceramic substrate and a lower ceramic substrate, wherein the left end of the upper ceramic substrate is connected to the lower ceramic substrate via a DC+ copper block, and the right end of the upper ceramic substrate is connected to the lower ceramic substrate via a gate copper block, two copper layers are respectively installed on the inner sides of the upper ceramic substrate and the lower ceramic substrate, wherein the copper layer is connected to a metal gasket via a solder layer, wherein the metal gasket is connected to the silicon carbide power chip via a solder layer, and wherein the silicon carbide power chip is connected to the copper block on the copper layer via a bonding wire. The copper blocks are respectively connected to the DC+ copper block, DC- copper block, AC copper block, upper Kelvin source copper block, and lower Kelvin source copper block through bonding wires. The DC+ copper block, DC- copper block, AC copper block, upper Kelvin source copper block, and lower Kelvin source copper block are respectively connected to the DC+ power terminal, DC- power terminal, AC power terminal, upper Kelvin source power terminal, and lower Kelvin source power terminal. The silicon carbide power chip is connected to the gate resistor through bonding wires, the gate resistor is connected to the gate copper block through bonding wires, and the gate copper block is connected to the gate power terminal.
[0006] As a preferred technical solution of the present invention, the silicon carbide power chip is connected to a metal gasket via an upper nano-silver sintered layer, and the metal gasket is connected to the copper layer via a lower nano-silver sintered layer.
[0007] As a preferred technical solution of the present invention, the material of the metal gasket is gold, silver, copper or aluminum.
[0008] As a preferred technical solution of the present invention, the DC+ power terminal, DC- power terminal, AC power terminal, upper Kelvin source power terminal, and lower Kelvin source power terminal are distributed on the same side or different sides.
[0009] As a preferred technical solution of the present invention, there are at least two silicon carbide power chips on the copper layer, and they are symmetrically distributed.
[0010] As a preferred technical solution of the present invention, the upper ceramic substrate, the lower ceramic substrate, the DC+ copper block, the DC+ power terminal, the DC- power terminal, the AC power terminal, the upper Kelvin source power terminal, the lower Kelvin source power terminal, the gate power terminal, the copper layer, the silicon carbide power chip, the copper block and the gate resistor are all arranged in epoxy resin.
[0011] Since the utility model adopts such a structure, it has the following beneficial effects:
[0012] 1. The utility model can use at least 20 silicon carbide power chips in parallel to form a power module, which improves the use and scope of application;
[0013] 2. The DC+, DC-, AC, and Kelvin source power terminals of the silicon carbide power chip in this utility model can be independently selected to be distributed on the same side or on different sides according to needs, which increases the flexibility of the actual use of the module;
[0014] 3. The silicon carbide power chips in this utility model are symmetrically distributed, which can significantly reduce the parasitic inductance of the overall loop and improve the overall reliability of the module;
[0015] 4. This utility model can reduce the overall heat accumulation of the module and improve heat loss by using new nano silver sintering materials and epoxy resin;
[0016] 5. The utility model can directly use single-sided solderable chips, reducing manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 This is a schematic diagram of the structure of the utility model;
[0018] Figure 2 It is a side view of the structure of the utility model;
[0019] Figure 3 This is a schematic diagram of the lower substrate structure of the present invention;
[0020] Figure 4 This is a top view of the lower substrate structure of the present invention;
[0021] Among them: 1. Upper ceramic plate; 2. Lower ceramic plate; 3. DC+ copper block; 4. DC+ power terminal; 5. DC- power terminal; 6. AC power terminal; 7. Lower Kelvin source power terminal; 8. Upper Kelvin source power terminal; 9. Gate power terminal; 10. Copper layer; 11. Lower nano-silver sintered layer; 12. Metal gasket; 13. Upper nano-silver sintered layer; 14. Silicon carbide power chip; 15. Copper block; 16. DC- copper block; 17. AC copper block; 18. Upper Kelvin source copper block; 19. Lower Kelvin source copper block; 20. Gate resistor; 21. Gate copper block. DETAILED DESCRIPTION
[0022] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0023] like Figures 1 to 4 As shown, the utility model is a symmetrical multi-chip parallel silicon carbide power module packaging structure, including an upper ceramic substrate 1 and a lower ceramic substrate 2, the left end of the upper ceramic substrate 1 is connected to the lower ceramic substrate 2 through a DC+ copper block 3, and the right end of the upper ceramic substrate 1 is connected to the lower ceramic substrate 2 through a gate copper block 21. Two copper layers 10 are respectively installed on the inner side of the upper ceramic substrate 1 and the lower ceramic substrate 2. The copper layer 10 is connected to the metal gasket 12 through a solder layer. The metal gasket 12 is connected to the silicon carbide power chip 14 through a solder layer. The silicon carbide power chip 14 is connected to the copper block 15 on the copper layer 10 through a bonding wire. The copper blocks 15 are respectively connected to the copper layer 10 through a bonding wire. Bonding wires connect the DC+ copper block 3, DC- copper block 16, AC copper block 17, upper Kelvin source copper block 18, and lower Kelvin source copper block 19. These blocks are connected to the DC+ power terminal 4, DC- power terminal 5, AC power terminal 6, upper Kelvin source power terminal 8, and lower Kelvin source power terminal 7, respectively. The silicon carbide power chip 14 is connected to the gate resistor 20 via bonding wires. The gate resistor 20 is connected to the gate copper block 21 via bonding wires, and the gate copper block 21 is connected to the gate power terminal 9. The DC+, DC-, AC, and Kelvin source power terminals of the silicon carbide power chip can be arranged on the same or opposite sides of the module, increasing the module's flexibility. Single-sided solderable chips can also be used, reducing manufacturing costs.
[0024] Furthermore, in the present invention, the silicon carbide power chip 14 is connected to the metal gasket 12 via the upper nano-silver sintered layer 13 , and the metal gasket 12 is connected to the copper layer 10 via the lower nano-silver sintered layer 11 .
[0025] Furthermore, in the present invention, the metal gasket 12 is made of gold, silver, copper or aluminum.
[0026] Furthermore, in the present invention, the DC+ power terminal 4, the DC- power terminal 5, the AC power terminal 6, the upper Kelvin source power terminal 8, and the lower Kelvin source power terminal 7 are distributed on the same side or on different sides.
[0027] Furthermore, the present invention has at least two symmetrically distributed silicon carbide power chips 14 on the copper layer 10. The symmetrical distribution of the silicon carbide power chips can significantly reduce the overall loop parasitic inductance and improve the overall reliability of the module.
[0028] Furthermore, the present invention incorporates the upper ceramic substrate 1, lower ceramic substrate 2, DC+ copper block 3, DC+ power terminal 4, DC- power terminal 5, AC power terminal 6, upper Kelvin source power terminal 8, lower Kelvin source power terminal 7, gate power terminal 9, copper layer 10, silicon carbide power chip 14, copper block 15, and gate resistor 20 within an epoxy resin. By utilizing novel nanosilver sintering materials and epoxy resin, heat accumulation within the module can be reduced, improving heat dissipation.
[0029] Under the same conditions, the utility model can use multiple silicon carbide power chips in parallel to form a power module, and the direction of the terminals can be selected according to actual needs. At the same time, the loop parasitic inductance is low and the performance is good.
[0030] The description and application of the present invention here are illustrative and are not intended to limit the scope of the present invention to the above-described embodiments. Variations and changes to the embodiments disclosed herein are possible, and actual replacements of the embodiments and various equivalent components are well known to those of ordinary skill in the art. It should be clear to those skilled in the art that the present invention can be implemented in other forms, structures, arrangements, proportions, and with other elements, materials, and components without departing from the spirit or essential characteristics of the present invention. Other variations and changes can be made to the embodiments disclosed herein without departing from the spirit or essential characteristics of the present invention.
Claims
1. A symmetrical multi-chip parallel silicon carbide power module packaging structure, characterized by: The invention comprises an upper ceramic substrate (1) and a lower ceramic substrate (2), wherein the left end of the upper ceramic substrate (1) is connected to the lower ceramic substrate (2) via a DC+ copper block (3), and the right end of the upper ceramic substrate (1) is connected to the lower ceramic substrate (2) via a gate copper block (21), and two copper layers (10) are respectively installed on the inner sides of the upper ceramic substrate (1) and the lower ceramic substrate (2), wherein the copper layer (10) is connected to a metal gasket (12) via a solder layer, and the metal gasket (12) is connected to a silicon carbide power chip (14) via a solder layer, and the silicon carbide power chip (14) is connected to a copper block (15) on the copper layer (10) via a bonding wire, and the copper block (15) is respectively connected to the DC+ copper block (3), the DC - copper block (16), AC copper block (17), upper Kelvin source copper block (18), lower Kelvin source copper block (19), the DC+ copper block (3), DC- copper block (16), AC copper block (17), upper Kelvin source copper block (18), lower Kelvin source copper block (19) are respectively connected to the DC+ power terminal (4), DC- power terminal (5), AC power terminal (6), upper Kelvin source power terminal (8), lower Kelvin source power terminal (7), the silicon carbide power chip (14) is connected to the gate resistor (20) through a bonding wire, the gate resistor (20) is connected to the gate copper block (21) through a bonding wire, and the gate copper block (21) is connected to the gate power terminal (9).
2. The symmetrical multi-chip parallel silicon carbide power module packaging structure according to claim 1, characterized in that: The silicon carbide power chip (14) is connected to a metal gasket (12) via an upper nano-silver sintered layer (13), and the metal gasket (12) is connected to a copper layer (10) via a lower nano-silver sintered layer (11).
3. The symmetrical multi-chip parallel silicon carbide power module packaging structure according to claim 1, characterized in that: The material of the metal gasket (12) is gold, silver, copper or aluminum.
4. The symmetrical multi-chip parallel silicon carbide power module packaging structure according to claim 1, characterized in that: The DC+ power terminal (4), the DC- power terminal (5), the AC power terminal (6), the upper Kelvin source power terminal (8), and the lower Kelvin source power terminal (7) are distributed on the same side or on different sides.
5. The symmetrical multi-chip parallel silicon carbide power module packaging structure according to claim 1, characterized in that: There are at least two silicon carbide power chips (14) on the copper layer (10), and they are symmetrically distributed.
6. The symmetrical multi-chip parallel silicon carbide power module packaging structure according to claim 1, characterized in that: The upper ceramic substrate (1), the lower ceramic substrate (2), the DC+ copper block (3), the DC+ power terminal (4), the DC- power terminal (5), the AC power terminal (6), the upper Kelvin source power terminal (8), the lower Kelvin source power terminal (7), the gate power terminal (9), the copper layer (10), the silicon carbide power chip (14), the copper block (15) and the gate resistor (20) are all arranged in epoxy resin.