Hardware overcurrent and overvoltage protection circuit

Abstract

The utility model discloses and provides a hardware over-current and over-voltage protection circuit comprising an over-voltage protection circuit module which is used for pulling down an OVP signal during over-voltage; the power dissipation circuit module is connected with the overvoltage protection circuit module and used for completing overvoltage release; an overcurrent protection circuit module, wherein the overcurrent protection circuit module is used for pulling down an OCP signal during overcurrent; and the driving circuit module is connected with the over-current protection circuit module and is used for closing the inverter to enable the inverter to enter a protection state. According to the utility model, a hardware protection mode of the mode is adopted, only two NPN triodes and two voltage-regulator tubes are needed, the circuit complexity can be reduced, the requirement of sampling data on the computing power of an MCU is reduced, and the real-time performance of protection action is improved. And through the falling edge signal feedback of the OVP, the protection action of software and hardware is realized.

Description

Technical Field

[0001] The present disclosure relates to the technical field of hardware protection circuits, and in particular to a hardware overcurrent and overvoltage protection circuit. Background Art

[0002] Traditional protection circuits use voltage and current sensors to collect voltage and current signals, which are then transmitted to the MCU via an isolator. The MCU then processes the data and takes protective action. This requires high analog sampling components, complex peripheral circuitry, and data transmission and processing, making it unsuitable for scenarios requiring high real-time performance. Utility Model Content

[0003] The present disclosure provides a hardware overcurrent and overvoltage protection circuit to solve one of the technical problems recognized by the inventor.

[0004] The present disclosure provides a hardware overcurrent and overvoltage protection circuit, comprising an overvoltage protection circuit module, wherein the overvoltage protection circuit module is configured to pull down an OVP signal when an overvoltage occurs;

[0005] A power dissipation circuit module, connected to the overvoltage protection circuit module, for completing overvoltage release;

[0006] An overcurrent protection circuit module, configured to pull down the OCP signal when an overcurrent occurs;

[0007] The driving circuit module is connected to the overcurrent protection circuit module and is used to shut down the inverter and put it into a protection state.

[0008] Preferably, the overvoltage protection circuit module includes voltage-stabilizing diodes D1 and D2, resistors R1, R2, R3, and R4, capacitors C1 and C2, and transistors Q1 and Q2. The base of the transistor Q1 is connected to the emitter of the transistor Q2 and is grounded, the base of the transistor Q2 is connected to the emitter of the transistor Q1, and the collector of the transistor Q1 is connected to the collector of the transistor Q2. The resistor R4 and the capacitor C2 are connected to the collectors of the transistor Q1 and the transistor Q2 respectively. The capacitor C1 and the resistor R1 are connected in series. The emitter of the transistor Q1 is connected between the capacitor C1 and the resistor R1. One end of the resistor R1 is connected to the resistor R2 and the resistor R3. One end of the resistor R2 is connected to the voltage-stabilizing diodes D1 and D2. One end of the voltage-stabilizing diode D1 is connected to the power dissipation circuit module.

[0009] Preferably, the power dissipation circuit module includes an inverter U1, a MOSFET Q6 and a resistor R9, the drain of the MOSFET Q6 is connected to one end of the voltage regulator D1, the gate of the MOSFET Q6 is connected to the inverter U1, and the source of the MOSFET Q6 is connected to the resistor R9.

[0010] Preferably, the overcurrent protection circuit module includes resistors R5, R6, R7, R8, capacitors C3, C4 and transistors Q3, Q4, the base of the transistor Q3 is connected to the emitter of the transistor Q4 and grounded, the emitter of the transistor Q3 is connected to the base of the transistor Q4, the collector of the transistor Q3 is connected to the collector of the transistor Q4, the resistor R6 and capacitor C4 are connected between the collector of the transistor Q3 and the collector of the transistor Q4, the capacitor C3 and the resistor R5 are connected in series, the emitter of the transistor Q3 is connected between the capacitor C3 and the resistor R5, and one end of the resistor R5 is connected to the drive circuit module.

[0011] Preferably, the driving circuit module includes a MOSFET Q5 and resistors R7 and R8, the gate of the MOSFET Q5 is connected to the MCU, the source of the MOSFET Q5 is connected to the resistor R5, and resistors R7 and R8 are connected in parallel between the source of the MOSFET Q5 and the resistor R5, and one end of the resistor R7 and the resistor R8 is grounded.

[0012] The main beneficial effects of this disclosure are: The present invention utilizes this hardware protection method, requiring only two NPN transistors and two voltage regulators. This reduces circuit complexity, reduces the computing power required by the MCU for sampling data, and improves the real-time performance of the protection action. Furthermore, the feedback of the falling edge signal of the OVP enables both hardware and software protection.

[0013] It should be understood that both the foregoing general description and the following detailed description are for purposes of illustration and description and are not necessarily limiting of the present disclosure. The accompanying drawings, which are incorporated into and constitute a part of the specification, illustrate the subject matter of the present disclosure. Together, the description and the drawings serve to explain the principles of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the specific embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0015] Figure 1 This is a circuit diagram of overcurrent and overvoltage protection according to an embodiment of the present disclosure;

[0016] Icon: 1-overvoltage protection circuit module; 2-power dissipation circuit module; 3-overcurrent protection circuit module; 4-drive circuit module. DETAILED DESCRIPTION

[0017] The technical solutions of the present disclosure will be described clearly and completely below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0018] Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work shall fall within the scope of protection of the present disclosure.

[0019] In the description of this disclosure, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this disclosure and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this disclosure. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0020] In the description of this disclosure, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this disclosure based on the specific circumstances.

[0021] Example

[0022] like Figure 1 As shown, this embodiment provides a hardware overcurrent and overvoltage protection circuit, including an overvoltage protection circuit module 1, wherein the overvoltage protection circuit module 1 is used to pull down the OVP signal when overvoltage occurs;

[0023] The power dissipation circuit module 2 is connected to the overvoltage protection circuit module 1 and is used to complete overvoltage release;

[0024] An overcurrent protection circuit module 3, configured to pull down the OCP signal when an overcurrent occurs;

[0025] The driving circuit module 4 is connected to the overcurrent protection circuit module 3 and is used to shut down the inverter and put it into a protection state.

[0026] Specifically, the overvoltage protection circuit module 1 includes Zener diodes D1 and D2, resistors R1, R2, R3, and R4, capacitors C1 and C2, and transistors Q1 and Q2. The base of the transistor Q1 is connected to the emitter of the transistor Q2 and is grounded, the base of the transistor Q2 is connected to the emitter of the transistor Q1, and the collector of the transistor Q1 is connected to the collector of the transistor Q2. The resistor R4 and the capacitor C2 are connected to the collectors of the transistor Q1 and the transistor Q2, respectively. The capacitor C1 and the resistor R1 are connected in series. The emitter of the transistor Q1 is connected between the capacitor C1 and the resistor R1. One end of the resistor R1 is connected to the resistor R2 and the resistor R3. One end of the resistor R2 is connected to the Zener diodes D1 and D2. One end of the Zener diode D1 is connected to the power dissipation circuit module 2. With two NPN transistors, Q1 and Q2, at its core, Zener diodes D1 and D2 form a voltage signal clamp. When the HV voltage exceeds the rated value of Zener diode D1, Zener diode D1 breaks down and clamps the voltage to the rated value of Zener diode D2. The voltage is divided by resistors R2 and R3, filtered by resistor R1 and capacitor C1, and then transistor Q2 turns on, pulling the OVP signal low. Simultaneously, transistor Q1 turns on, accelerating the pull-down speed.

[0027] Furthermore, the power dissipation circuit module 2 includes an inverter U1, a MOSFET Q6, and a resistor R9. The drain of the MOSFET Q6 is connected to one end of the voltage regulator D1, the gate of the MOSFET Q6 is connected to the inverter U1, and the source of the MOSFET Q6 is connected to the resistor R9. When the HV voltage exceeds the rated value of the voltage regulator D1, the voltage regulator D1 breaks down and is clamped to the rated value of the voltage regulator D2. After voltage division by resistors R2 and R3, and filtering by resistor R1 and capacitor C1, the transistor Q2 is turned on, pulling down the OVP signal. At the same time, the transistor Q1 is turned on, accelerating the pulling-down speed. At the same time, the inverter U1 turns on the MOSFET Q6, and the high voltage HV is dissipated through the resistor R9 to complete the overvoltage release.

[0028] In this embodiment, the HV overvoltage value is set to 400V. A 400V Zener diode is used for Zener diode D1, and a 5V Zener diode is used for Zener diode D2. Resistors R2 and R3 serve as voltage divider resistors, with R2 = R3 = 10R. Resistor R4 serves as a pull-up resistor, with R4 = 10K, R1 = 1K, and capacitor C1 = 1nF. When the circuit operates normally, the OVP pull-up output is 10V. When HV > 400V, the high voltage breaks down Zener diodes D1, and D2 is clamped to 5V. Through voltage divider resistors R2 and R3, the voltage on transistor Q2 is 2.5V during overvoltage. Transistor Q2 turns on, the OVP is grounded, and MOSFET Q6 is turned on through inverter U1. The high voltage then flows through MOSFET Q6 and resistor R9 to ground, preventing further HV overvoltage.

[0029] Specifically, the overcurrent protection circuit module 3 includes resistors R5, R6, R7, and R8, capacitors C3 and C4, and transistors Q3 and Q4. The base of the transistor Q3 is connected to the emitter of the transistor Q4 and is grounded. The emitter of the transistor Q3 is connected to the base of the transistor Q4, and the collector of the transistor Q3 is connected to the collector of the transistor Q4. A resistor R6 and a capacitor C4 are connected between the collector of the transistor Q3 and the collector of the transistor Q4. The capacitor C3 and the resistor R5 are connected in series. The emitter of the transistor Q3 is connected between the capacitor C3 and the resistor R5. One end of the resistor R5 is connected to the drive circuit module 4.

[0030] Furthermore, the drive circuit module 4 includes a MOSFET Q5 and resistors R7 and R8. The gate of the MOSFET Q5 is connected to the MCU, the source of the MOSFET Q5 is connected to the resistor R5, and resistors R7 and R8 are connected in parallel between the source of the MOSFET Q5 and the resistor R5. One end of the resistors R7 and R8 is grounded. When overvoltage occurs, the MCU detects the OVP falling edge and instructs the MOSFET Q5 to turn off, putting the inverter into a protection state. When overcurrent occurs, the transistors Q3 and Q4 are the core, the transistors Q1 and Q2 are two NPN transistors, the MOSFET Q5 is a power transistor, and the resistors R7 and R8 are sampling resistors. When MOSFET Q5 turns on, current flows through resistors R7 and R8 to ground. The voltage across the sampling resistors of parallel resistors R7 and R8 reaches the turn-on voltage of transistor Q4. After being filtered by resistor R5 and capacitor C3, transistor Q4 turns on, pulling the OCP signal low. At the same time, transistor Q3 turns on, accelerating the pull-down speed. The OCP voltage is pulled low, turning off MOSFET Q5.

[0031] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A hardware overcurrent and overvoltage protection circuit, characterized in that: include: An overvoltage protection circuit module, configured to pull down the OVP signal when overvoltage occurs; A power dissipation circuit module, connected to the overvoltage protection circuit module, for completing overvoltage release; An overcurrent protection circuit module, configured to pull down the OCP signal when an overcurrent occurs; The driving circuit module is connected to the overcurrent protection circuit module and is used to shut down the inverter and put it into a protection state.

2. A hardware overcurrent and overvoltage protection circuit according to claim 1, characterized in that: The overvoltage protection circuit module includes voltage-stabilizing diodes D1 and D2, resistors R1, R2, R3, and R4, capacitors C1 and C2, and transistors Q1 and Q2. The base of the transistor Q1 is connected to the emitter of the transistor Q2 and to ground, the base of the transistor Q2 is connected to the emitter of the transistor Q1, and the collector of the transistor Q1 is connected to the collector of the transistor Q2. The resistor R4 and the capacitor C2 are connected to the collectors of the transistors Q1 and Q2, respectively. The capacitor C1 and the resistor R1 are connected in series. The emitter of the transistor Q1 is connected between the capacitor C1 and the resistor R1. One end of the resistor R1 is connected to the resistors R2 and R3. One end of the resistor R2 is connected to the voltage-stabilizing diodes D1 and D2. One end of the voltage-stabilizing diode D1 is connected to the power dissipation circuit module.

3. A hardware overcurrent and overvoltage protection circuit according to claim 2, characterized in that: The power dissipation circuit module includes an inverter U1, a MOSFET Q6 and a resistor R9. The drain of the MOSFET Q6 is connected to one end of the voltage regulator D1, the gate of the MOSFET Q6 is connected to the inverter U1, and the source of the MOSFET Q6 is connected to the resistor R9.

4. A hardware overcurrent and overvoltage protection circuit according to claim 3, characterized in that: The overcurrent protection circuit module includes resistors R5, R6, R7, and R8, capacitors C3 and C4, and transistors Q3 and Q4. The base of the transistor Q3 is connected to the emitter of the transistor Q4 and is grounded. The emitter of the transistor Q3 is connected to the base of the transistor Q4, and the collector of the transistor Q3 is connected to the collector of the transistor Q4. Resistor R6 and capacitor C4 are connected between the collector of the transistor Q3 and the collector of the transistor Q4. The capacitor C3 and resistor R5 are connected in series. The emitter of the transistor Q3 is connected between the capacitor C3 and the resistor R5. One end of the resistor R5 is connected to the drive circuit module.

5. The hardware overcurrent and overvoltage protection circuit according to claim 4, characterized in that: The driving circuit module includes a MOSFET Q5 and resistors R7 and R8. The gate of the MOSFET Q5 is connected to the MCU, the source of the MOSFET Q5 is connected to the resistor R5, and resistors R7 and R8 are connected in parallel between the source of the MOSFET Q5 and the resistor R5. One end of the resistor R7 and the resistor R8 is grounded.

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