Fully differential amplification circuit, chip and electronic equipment

Abstract

The embodiment of the utility model provides a fully-differential amplification circuit, a chip and electronic equipment, the fully-differential amplification circuit comprises a fully-differential amplification module and a common-mode feedback module, and the common-mode feedback module comprises a voltage acquisition unit, a piezoelectric conversion unit, a mirror image unit and a feedback output unit. A feedback loop of common-mode voltage is realized through the voltage acquisition unit, the piezoelectric conversion unit, the mirror image unit and the feedback output unit, and the feedback loop is prevented from using a voltage comparator, so that the use number of transistors in the feedback loop is reduced, and the cost and the occupied area are further reduced.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a fully differential amplifier circuit, a chip, and an electronic device. Background Art

[0002] Fully differential amplifiers usually use a feedback loop to achieve common-mode feedback, and the feedback loop is mostly implemented through a voltage comparator.

[0003] However, the voltage comparator requires a large number of transistors, which increases the cost and occupied area. Utility Model Content

[0004] In view of the above problems, embodiments of the present application provide a fully differential amplifier circuit, chip, and electronic device to alleviate the above technical problems.

[0005] In a first aspect, an embodiment of the present application provides a fully differential amplifier circuit, comprising a fully differential amplifier module and a common-mode feedback module. The fully differential amplifier module comprises a first output terminal and a second output terminal. The common-mode feedback module comprises a voltage acquisition unit, a piezoelectric conversion unit, a mirror unit, and a feedback output unit. The voltage acquisition unit is connected to the first output terminal and the second output terminal and outputs a first voltage signal; the piezoelectric conversion unit is used to convert the first voltage signal into a first current signal; the mirror unit is used to proportionally mirror the first current signal; the control terminal of the feedback output unit is connected to the common-mode terminal, and the feedback output unit is used to output a control voltage signal based on the first current signal to adjust the output voltage of the fully differential amplifier module.

[0006] In a second aspect, an embodiment of the present application further provides a chip comprising the above-mentioned fully differential amplifier circuit.

[0007] In a third aspect, an embodiment of the present application further provides an electronic device, which includes a device body and the above-mentioned chip or fully differential amplifier circuit provided in the device body.

[0008] The fully differential amplifier circuit, chip, and electronic device provided in the embodiments of the present application implement a common-mode voltage feedback loop through a voltage acquisition unit, a piezoelectric conversion unit, a mirror unit, and a feedback output unit, thereby avoiding the use of a voltage comparator in the feedback loop, thereby reducing the number of transistors used in the feedback loop, and further reducing cost and occupied area.

[0009] Furthermore, compared to the use of a voltage comparator, which results in a feedback loop with a larger number of poles, the gain bandwidth of the feedback loop is narrower, the feedback speed of the feedback loop is slower, and the ability to suppress the common-mode voltage decreases with increasing frequency. Therefore, the common-mode rejection ratio at high frequencies is relatively low, and in some cases, there may even be stability issues with the feedback loop. This application reduces the number of poles in the feedback loop by avoiding the use of a voltage comparator in the feedback loop, has a wider gain bandwidth, and thus has a faster dynamic adjustment speed of the common-mode voltage, thereby having higher gain linearity and common-mode rejection ratio, and also improves the stability of the operation.

[0010] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 A first principle block diagram of a fully differential amplifier circuit provided in an embodiment of the present application is shown.

[0013] Figure 2 A second principle block diagram of the fully differential amplifier circuit provided in an embodiment of the present application is shown.

[0014] Figure 3 Shows the circuit principle diagram of the piezoelectric conversion unit.

[0015] Figure 4 shows the circuit schematic of the mirror unit.

[0016] Figure 5 shows the circuit schematic diagram of the feedback output unit.

[0017] Figure 6 A first circuit principle diagram of a voltage acquisition unit is shown.

[0018] Figure 7 A second circuit principle diagram of the voltage acquisition unit is shown.

[0019] Figure 8 The circuit schematic diagram of the fully differential amplifier module is shown.

[0020] Figure 9 A first circuit schematic diagram of a fully differential amplifier circuit provided in an embodiment of the present application is shown.

[0021] Figure 10A second circuit schematic diagram of a fully differential amplifier circuit provided in an embodiment of the present application is shown.

[0022] Figure 11 The figure shows the structure of the chip provided in the embodiment of the present application.

[0023] Figure 12 The figure shows a structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0025] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0026] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, etc., are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0027] Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0028] In the description of the embodiments of this application, words such as "example" or "for example" are used to indicate an example, illustration, or description. Any embodiment or design described as "for example" or "for example" in the embodiments of this application is not to be construed as being preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to clearly present relative concepts.

[0029] In addition, in the embodiments of the present application, "plurality" refers to two or more. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two, or more. For example, "including at least one" means including one, two, or more, and does not limit which ones are included. For example, "including at least one of A, B, and C" means including A, B, C, A and B, A and C, B and C, or A, B, and C.

[0030] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0031] In the embodiments of the present application, the first electrode / first end of each transistor is one of the source and the drain, and the second electrode / second end of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be structurally symmetrical, the source and drain can be structurally identical. In other words, the first electrode / first end and the second electrode / second end of the transistor in the embodiments of the present application can be structurally identical.

[0032] In the circuit structure provided in the embodiments of the present application, the first node, the second node and other nodes do not represent actual components, but represent the junction points of related couplings in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0033] Figure 1 The schematic diagram of the fully differential amplifier circuit 100 provided in an embodiment of the present application is shown. The fully differential amplifier circuit 100 includes a fully differential amplifier module 10 and a common-mode feedback module 20. The common-mode feedback module 20 includes a voltage acquisition unit 21, a piezoelectric conversion unit 22, a mirror unit 23, and a feedback output unit 24. The voltage acquisition unit 21, the piezoelectric conversion unit 22, the mirror unit 23, and the feedback output unit 24 implement a common-mode voltage feedback loop, avoiding the use of a voltage comparator in the feedback loop, thereby reducing the number of transistors used in the feedback loop, and further reducing cost and occupied area.

[0034] The present embodiment provides a fully differential amplifier circuit 100. Figures 1 to 10 ,like Figure 1As shown, the fully differential amplifier circuit 100 includes a fully differential amplifier module 10 and a common-mode feedback module 20. The fully differential amplifier module 10 includes a first output terminal Vop and a second output terminal Von. The common-mode feedback module 20 includes a voltage acquisition unit 21, a piezoelectric conversion unit 22, a mirror unit 23, and a feedback output unit 24. The voltage acquisition unit 21 is connected to the first output terminal Vop and the second output terminal Von, and outputs a first voltage signal Vmid. The piezoelectric conversion unit 22 is used to convert the first voltage signal Vmid into a first current signal. The mirror unit 23 is used to proportionally mirror the first current signal. The control end of the feedback output unit 24 is connected to the common-mode terminal Vcm, and the feedback output unit 24 is used to output a control voltage signal Vctrl according to the first current signal to adjust the output voltage of the fully differential amplifier module 10.

[0035] It can be understood that the fully differential amplifier circuit 100 provided in the embodiment of the present application realizes the common-mode voltage feedback loop through the voltage acquisition unit 21, the piezoelectric conversion unit 22, the mirror unit 23 and the feedback output unit 24, avoiding the use of a voltage comparator in the feedback loop, thereby reducing the number of transistors used in the feedback loop, and further reducing the cost and occupied area.

[0036] Furthermore, compared to the use of a voltage comparator, which results in a feedback loop with a larger number of poles, the gain bandwidth of the feedback loop is narrower, the feedback speed of the feedback loop is slower, and the ability to suppress the common-mode voltage decreases with increasing frequency. Therefore, the common-mode rejection ratio at high frequencies is relatively low, and in some cases, there may even be stability issues with the feedback loop. This application reduces the number of poles in the feedback loop by avoiding the use of a voltage comparator in the feedback loop, has a wider gain bandwidth, and thus has a faster dynamic adjustment speed of the common-mode voltage, thereby having higher gain linearity and common-mode rejection ratio, and also improves the stability of the operation.

[0037] Alternatively, as Figure 2 As shown, the common-mode feedback module further includes a bias unit 25 , which is used to mirror the bias current signal of the fully differential amplifier module.

[0038] It should be noted that the bias unit 25 can obtain a stable mirror current according to the bias current signal.

[0039] Alternatively, as Figure 3 As shown, the piezoelectric conversion unit 22 includes a first transistor Q9 , a control electrode of the first transistor Q9 is used to receive the first voltage signal Vmid, a first electrode of the first transistor Q9 is connected to one end of the mirror unit 23 , and a second electrode of the first transistor Q9 is connected to the bias unit 25 .

[0040] It should be noted that the first transistor Q9 can provide a corresponding current to the mirror unit 23 according to the voltage at the output end of the voltage acquisition unit 21 .

[0041] Alternatively, as Figure 4 As shown, the mirror unit 23 includes a second transistor Q11 and a third transistor Q10. The first electrode of the second transistor Q11 is connected to the first voltage terminal, and the second electrode of the second transistor Q11 is connected to the control electrode of the second transistor Q11 and the first electrode of the first transistor Q9. The first electrode of the third transistor Q10 is connected to the first electrode of the second transistor Q11, the control electrode of the third transistor Q10 is connected to the control electrode of the second transistor Q11, and the second electrode of the third transistor Q10 is connected to the feedback output unit 24.

[0042] It should be noted that, since the channel of the first transistor Q9 and the channel of the second transistor Q11 are connected in series in the same branch, the current flowing through the first transistor Q9 is the same as the current flowing through the second transistor Q11; since the second transistor Q11 and the third transistor Q10 form a 1:1 mirror current source, the current flowing through the second transistor Q11 is the same as the current flowing through the third transistor Q10; since the channel of the third transistor Q10 and the channel of the fourth transistor Q8 are connected in series in the same branch, the current flowing through the third transistor Q10 is the same as the current flowing through the fourth transistor Q8.

[0043] Alternatively, as Figure 5 As shown, the feedback output unit 24 includes a fourth transistor Q8 , a first electrode of the fourth transistor Q8 is connected to the second electrode of the third transistor Q10 , a control electrode of the fourth transistor Q8 is used to receive a fixed common-mode voltage signal Vcm, and a second electrode of the fourth transistor Q8 is connected to the bias unit 25 .

[0044] It should be noted that the common-mode terminal is used to provide the fixed common-mode voltage signal Vcm. The fourth transistor Q8 can adjust the voltage of the control voltage signal Vctrl by the current flowing through it. The connection node between the first electrode of the fourth transistor Q8 and the second electrode of the third transistor Q10 is used to output the control voltage signal Vctrl.

[0045] The fourth transistor Q8 is the same as the first transistor Q9 and can reduce the feedback error of the common mode voltage and improve the common mode rejection ratio.

[0046] Alternatively, as Figure 6 As shown, the voltage acquisition unit 21 includes a first resistor R1 and a second resistor R2, one end of the first resistor R1 is connected to the first output terminal Vop; one end of the second resistor R2 is connected to the other end of the first resistor R1 and the control electrode of the first transistor Q9, and the other end of the second resistor R2 is connected to the second output terminal Von.

[0047] It should be noted that the resistance of the first resistor R1 can be equal to the resistance of the second resistor R2, so as to control the first voltage signal Vmid output by the voltage acquisition unit 21 to be half the difference between the voltages at the first output terminal Vop and the second output terminal Von. This embodiment is not limited to this. In other embodiments, the average value of the difference between the voltages at the first output terminal Vop and the second output terminal Von can also be calculated using other circuits.

[0048] Alternatively, as Figure 7 As shown, the voltage acquisition unit 21 also includes a first capacitor C1 and a second capacitor C2, one end of the first capacitor C1 is connected to the first output terminal Vop; one end of the second capacitor C2 is connected to the other end of the first capacitor C1, one end of the second resistor R2 and the other end of the first resistor R1, and the other end of the second capacitor C2 is connected to the second output terminal Von.

[0049] It should be noted that the feedback loop can improve the feedback speed of the common-mode voltage without using a voltage comparator. On this basis, this embodiment can further improve the feedback speed of the common-mode voltage through the connection structure of the first capacitor C1 and the second capacitor C2, thereby having a faster common-mode voltage dynamic adjustment speed.

[0050] Alternatively, as Figure 8 As shown, the fully differential amplifier module 10 includes a fifth transistor Q6, a sixth transistor Q7, a seventh transistor Q4, and an eighth transistor Q5. The first electrode of the fifth transistor Q6 is connected to the first voltage terminal, the control electrode of the fifth transistor Q6 is connected to the second electrode of the third transistor Q10, and the second electrode of the fifth transistor Q6 is connected to the first output terminal Vop. The first electrode of the sixth transistor Q7 is connected to the first voltage terminal, the control electrode of the sixth transistor Q7 is connected to the control electrode of the fifth transistor Q6, and the second electrode of the sixth transistor Q7 is connected to the second output terminal Von. The first electrode of the seventh transistor Q4 is connected to the first output terminal Vop, and the control electrode of the seventh transistor Q4 is used to receive the first voltage input signal Vip. The first electrode of the eighth transistor Q5 is connected to the second output terminal Von, the control electrode of the eighth transistor Q5 is used to receive the second voltage input signal Vin, and the second electrode of the eighth transistor Q5 is connected to the second electrode of the seventh transistor Q4.

[0051] It should be noted that the current flowing through the fifth transistor Q6 is the same as the current flowing through the sixth transistor Q7. The seventh transistor Q4 and the eighth transistor Q5 can play a role of differential amplification.

[0052] Alternatively, as Figure 9As shown, the fully differential amplifier circuit 100 further includes a ninth transistor Q1, a tenth transistor Q2, a first current source A1, and an eleventh transistor Q3. The first electrode of the ninth transistor Q1 is connected to the second electrode of the seventh transistor Q4 and the second electrode of the eighth transistor Q5, and the second electrode of the ninth transistor Q1 is connected to the second voltage terminal. The first electrode of the tenth transistor Q2 is connected to the control electrode of the tenth transistor Q2 and the control electrode of the ninth transistor Q1, and the second electrode of the tenth transistor Q2 is connected to the second voltage terminal. One end of the first current source A1 is connected to the first voltage terminal, and the other end of the first current source A1 is connected to the first electrode of the tenth transistor Q2 and the control electrode of the tenth transistor Q2.

[0053] Alternatively, as Figure 9 、 Figure 10 As shown, the bias unit 25 includes an eleventh transistor Q3, a first electrode of the eleventh transistor Q3 is connected to the second electrode of the first transistor Q9 and the second electrode of the fourth transistor Q8, a control electrode of the eleventh transistor Q3 is connected to the control electrode of the ninth transistor Q1 and the control electrode of the tenth transistor Q2, and a second electrode of the eleventh transistor Q3 is connected to the second voltage terminal.

[0054] It should be noted that the control electrode potential of the ninth transistor Q1 or the control electrode potential of the tenth transistor Q2 is represented by Vbias. The first current source A1 can be used to provide a stable bias current signal, namely Ibias. The current flowing through the tenth transistor Q2 is Ibias. The ninth transistor Q1 and the tenth transistor Q2 can form a mirror current source. At the same time, the tenth transistor Q2 also forms a mirror current source with the eleventh transistor Q3, and the eleventh transistor Q3 can provide a corresponding stable current.

[0055] Alternatively, as Figure 10 As shown, a first electrode of the ninth transistor Q1 is connected to the second voltage terminal, and a second electrode of the ninth transistor Q1 is connected to the second electrode of the seventh transistor Q4 and the second electrode of the eighth transistor Q5; a first electrode of the tenth transistor Q2 is connected to the second voltage terminal, and a second electrode of the tenth transistor Q2 is connected to the control electrode of the tenth transistor Q2 and the control electrode of the ninth transistor Q1; one end of the first current source A1 is connected to the first voltage terminal, and the other end of the first current source A1 is connected to the first electrode of the tenth transistor Q2 and the control electrode of the tenth transistor Q2.

[0056] It should be noted that, unlike Figure 10 The ninth transistor Q1 and the tenth transistor Q2 are both N-channel transistors. Figure 11 The ninth transistor Q1 and the tenth transistor Q2 are both P-channel transistors.

[0057] Figure 9FIG. 1 shows a first circuit schematic diagram of a fully differential amplifier circuit 100 provided in an embodiment of the present application, wherein the control electrode of each transistor can be a gate. Figure 9 Taking the seventh transistor Q4 and the eighth transistor Q5 as N-channel field-effect transistors as an example, the first transistor Q9, the fourth transistor Q8, the eleventh transistor Q3, the ninth transistor Q1, and the tenth transistor Q2 are all N-channel field-effect transistors, and the second transistor Q11, the third transistor Q10, the fifth transistor Q6, and the sixth transistor Q7 are all P-channel field-effect transistors.

[0058] Figure 10 A second circuit schematic diagram of the fully differential amplifier circuit 100 provided in an embodiment of the present application is shown. Figure 10 Taking the seventh transistor Q4 and the eighth transistor Q5 as P-channel field-effect transistors as an example, the first transistor Q9, the fourth transistor Q8, the eleventh transistor Q3, the ninth transistor Q1, and the tenth transistor Q2 are all P-channel field-effect transistors, and the second transistor Q11, the third transistor Q10, the fifth transistor Q6, and the sixth transistor Q7 are all N-channel field-effect transistors.

[0059] It should be noted that in Figure 9 In the embodiment, the first voltage terminal is the power supply terminal Vcc, and the second voltage terminal is the ground terminal GND. Figure 10 In the embodiment, the first voltage terminal is the ground terminal GND, and the second voltage terminal is the power supply terminal Vcc.

[0060] Figure 9 、 Figure 10 The working principle of the fully differential amplifier circuit 100 is as follows:

[0061] The eleventh transistor Q3, the ninth transistor Q1, and the tenth transistor Q2 form a mirrored constant current source. The current flowing through the tenth transistor Q2 is Ibias. The current flowing through the ninth transistor Q1 and the eleventh transistor Q3 is determined by Ibias and the current mirror ratio between the transistors. The seventh transistor Q4 and the eighth transistor Q5 form the input amplifying field-effect transistor of the fully differential amplifier. The fifth transistor Q6 and the sixth transistor Q7 form a 1:1 mirrored current source bias circuit, which provides operating bias voltages for the seventh transistor Q4 and the eighth transistor Q5, respectively. The drain current of the ninth transistor Q1 provides source bias current for the seventh transistor Q4 and the eighth transistor Q5.

[0062] Among them, the fifth transistor Q6, the sixth transistor Q7, the seventh transistor Q4, the eighth transistor Q5, the ninth transistor Q1, and the tenth transistor Q2 together constitute the main body of the fully differential amplifier. The input signal enters from the gate of the seventh transistor Q4 and the eighth transistor Q5, and the amplified output signal is output from the drain of the seventh transistor Q4 and the eighth transistor Q5. The first resistor R1, the second resistor R2, the first transistor Q9, the fourth transistor Q8, the second transistor Q11, the third transistor Q10, and the eleventh transistor Q3 constitute the feedback loop of the fully differential amplifier. Optionally, the feedback loop may also include a first capacitor C1 and a second capacitor C2, which are used to accelerate the feedback of the common-mode voltage.

[0063] Among them, the first resistor R1 and the second resistor R2 are used to sample the common-mode part of the output voltage of the fully differential amplifier. Vmid is the collected first voltage signal Vmid, which is input to the gate of the first transistor Q9, and the gate of the fourth transistor Q8 receives a fixed common-mode voltage signal Vcm. The common-mode end is the external common-mode input end of the fully differential amplifier. The eleventh transistor Q3 provides a constant current source bias for the feedback loop. The second transistor Q11 and the third transistor Q10 form a 1:1 mirror current source, which is used to mirror the drain current of the first transistor Q9 to the drain of the fourth transistor Q8 to achieve current summation. Generally, the first transistor Q9 is required to be the same as the fourth transistor Q8, but there are inevitably some slight differences in the actual process. Therefore, the parameters of the first transistor Q9 and the fourth transistor Q8 are basically matched to reduce the feedback error of the common-mode voltage and improve the common-mode rejection ratio.

[0064] The output of the feedback loop is the drain of the fourth transistor Q8, which is also connected to the gates of the fifth transistor Q6 and the sixth transistor Q7 in the current source bias circuit of the fully differential amplifier. In steady state, after feedback, the potential of the common-mode voltage signal Vcm is approximately equal to the potential of the first voltage signal Vmid output by the voltage acquisition unit 21, and is also approximately equal to the average value of the difference between the voltages at the first output terminal Vop and the second output terminal Von. Therefore, this feedback loop can achieve good steady-state accuracy.

[0065] The current flowing through the first transistor Q9 is recorded as Iq9, the current flowing through the fourth transistor Q8 is recorded as Iq8, the current flowing through the eleventh transistor Q3 is recorded as Iq3, the current flowing through the second transistor Q11 is recorded as Iq11, and the current flowing through the third transistor Q10 is recorded as Iq10.

[0066] Since Iq3 is fixed, and Iq8 + Iq9 = Iq3, when the voltage difference between the first output terminal Vop and the second output terminal Von increases, Vmid also increases, and Iq9 increases, which simultaneously causes the current in Iq8 to decrease (because the sum of Iq8 and Iq9 is fixed). Furthermore, since Q10 and Q11 form a 1:1 mirror current source, and Iq9 = Iq11, then Iq10 = Iq9. Therefore, Iq10 also increases with increasing Vmid. Since the difference between Iq10 flowing into the second terminal of the third transistor Q10 and Iq8 flowing out of the second terminal of the third transistor Q10, that is, Iq10 - Iq8, increases with increasing Vmid, Vctrl is forced to rise. Similarly, when Vmid decreases, Vctrl is forced to fall.

[0067] Compared with the feedback loop formed by the voltage comparator in the traditional technology, since the feedback loop provided by the present application has fewer stages (number) of field-effect tubes and fewer poles of the feedback loop gain, it has a wider loop gain bandwidth, thereby having a faster common-mode voltage dynamic adjustment speed, and thus having higher gain linearity and common-mode rejection ratio.

[0068] The embodiment of the present application further provides a chip 200, such as Figure 11 As shown, the chip 200 includes the above-mentioned fully differential amplifier circuit 100. The chip 200 is also called an integrated circuit (IC), and the chip 200 can be, but is not limited to, a SOC (System on Chip) chip or a SIP (System in Package) chip.

[0069] It can be understood that since the chip 200 provided in the embodiment of the present application includes the above-mentioned fully differential amplifier circuit 100, it can also realize the common-mode voltage feedback loop through the voltage acquisition unit 21, the piezoelectric conversion unit 22, the mirror unit 23 and the feedback output unit 24, avoiding the use of a voltage comparator in the feedback loop, thereby reducing the number of transistors used in the feedback loop, and further reducing the cost and occupied area.

[0070] Furthermore, compared to the use of a voltage comparator, which results in a feedback loop with a larger number of poles, the gain bandwidth of the feedback loop is narrower, the feedback speed of the feedback loop is slower, and the ability to suppress the common-mode voltage decreases with increasing frequency. Therefore, the common-mode rejection ratio at high frequencies is relatively low, and in some cases, there may even be stability issues with the feedback loop. This application reduces the number of poles in the feedback loop by avoiding the use of a voltage comparator in the feedback loop, has a wider gain bandwidth, and thus has a faster dynamic adjustment speed of the common-mode voltage, thereby having higher gain linearity and common-mode rejection ratio, and also improves the stability of the operation.

[0071] The embodiment of the present application also provides an electronic device 300, such as Figure 12 As shown, the electronic device 300 includes a device body and the above-mentioned chip 200 or fully differential amplifier circuit 100 provided in the device body. The electronic device 300 can be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control panel, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminals). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0072] It can be understood that since the electronic device 300 provided in the embodiment of the present application includes the above-mentioned chip 200 or the fully differential amplifier circuit 100, it can also realize the common-mode voltage feedback loop through the voltage acquisition unit 21, the piezoelectric conversion unit 22, the mirror unit 23 and the feedback output unit 24, avoiding the use of a voltage comparator in the feedback loop, thereby reducing the number of transistors used in the feedback loop, and further reducing the cost and occupied area.

[0073] Furthermore, compared to the use of a voltage comparator, which results in a feedback loop with a larger number of poles, the gain bandwidth of the feedback loop is narrower, the feedback speed of the feedback loop is slower, and the ability to suppress the common-mode voltage decreases with increasing frequency. Therefore, the common-mode rejection ratio at high frequencies is relatively low, and in some cases, there may even be stability issues with the feedback loop. This application reduces the number of poles in the feedback loop by avoiding the use of a voltage comparator in the feedback loop, has a wider gain bandwidth, and thus has a faster dynamic adjustment speed of the common-mode voltage, thereby having higher gain linearity and common-mode rejection ratio, and also improves the stability of the operation.

[0074] The above is only a preferred embodiment of the present application and does not constitute any form of limitation to the present application. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A fully differential amplifier circuit, characterized in that: The fully differential amplifier circuit comprises: A fully differential amplification module, the fully differential amplification module comprising a first output end and a second output end; A common-mode feedback module, comprising: a voltage acquisition unit, connected to the first output terminal and the second output terminal, and outputting a first voltage signal; a piezoelectric conversion unit, configured to convert the first voltage signal into a first current signal; a mirror unit, the mirror unit being configured to mirror the first current signal in equal proportion; A feedback output unit, wherein the control end of the feedback output unit is connected to the common mode end, and the feedback output unit is used to output a control voltage signal according to the first current signal to adjust the output voltage of the fully differential amplifier module.

2. The fully differential amplifier circuit according to claim 1, wherein: The common-mode feedback module further includes a bias unit, which is used to mirror the bias current signal of the fully differential amplification module.

3. The fully differential amplifier circuit according to claim 2, wherein: The piezoelectric conversion unit includes a first transistor, a control electrode of the first transistor is used to receive the first voltage signal, a first electrode of the first transistor is connected to one end of the mirror unit, and a second electrode of the first transistor is connected to the bias unit.

4. The fully differential amplifier circuit according to claim 3, wherein: The mirror unit includes: a second transistor, wherein a first electrode of the second transistor is connected to the first voltage terminal, and a second electrode of the second transistor is connected to the control electrode of the second transistor and the first electrode of the first transistor; a third transistor, wherein a first electrode of the third transistor is connected to the first electrode of the second transistor, a control electrode of the third transistor is connected to the control electrode of the second transistor, and a second electrode of the third transistor is connected to the feedback output unit.

5. The fully differential amplifier circuit according to claim 4, wherein: The feedback output unit includes a fourth transistor, wherein a control electrode of the fourth transistor is used to receive a fixed common-mode voltage signal, a first electrode of the fourth transistor is connected to the second electrode of the third transistor, and a second electrode of the fourth transistor is connected to the bias unit; The connection node between the first electrode of the fourth transistor and the second electrode of the third transistor is used to output the control voltage signal; and the fourth transistor is the same as the first transistor.

6. The fully differential amplifier circuit according to claim 5, wherein: The voltage acquisition unit includes: a first resistor, one end of the first resistor being connected to the first output end; A second resistor, one end of the second resistor is connected to the other end of the first resistor and the control electrode of the first transistor, and the other end of the second resistor is connected to the second output end.

7. The fully differential amplifier circuit according to claim 6, wherein: The voltage acquisition unit further includes: a first capacitor, one end of the first capacitor being connected to the first output end; a second capacitor, one end of the second capacitor being connected to the other end of the first capacitor, one end of the second resistor, and the other end of the first resistor, and the other end of the second capacitor being connected to the second output end.

8. The fully differential amplifier circuit according to claim 7, wherein: The fully differential amplification module includes: a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first voltage terminal, a control electrode of the fifth transistor is connected to the second electrode of the third transistor, and a second electrode of the fifth transistor is connected to the first output terminal; a sixth transistor, wherein a first electrode of the sixth transistor is connected to the first voltage terminal, a control electrode of the sixth transistor is connected to the control electrode of the fifth transistor, and a second electrode of the sixth transistor is connected to the second output terminal; a seventh transistor, a first electrode of the seventh transistor being connected to the first output terminal, and a control electrode of the seventh transistor being configured to receive a first voltage input signal; An eighth transistor, wherein a first electrode of the eighth transistor is connected to the second output end, a control electrode of the eighth transistor is used to receive a second voltage input signal, and a second electrode of the eighth transistor is connected to the second electrode of the seventh transistor.

9. A chip, characterized in that: The chip includes the fully differential amplifier circuit according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device includes a device body and the chip according to claim 9 provided in the device body.

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