Semiconductor device
By using the deposition process to form a heavily doped layer as the plate layer in DRAM devices, the problems of insufficient storage capacity and low device integration are solved, and higher storage capacity and smaller device size are achieved.
Patent Information
- Application Number
- CN202422536412.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-21
- Publication Date
- 2025-08-15
- Estimated Expiration
- 2034-10-21
AI Technical Summary
The storage capacity of storage capacitors in existing DRAM devices is weak and the device integration is not high.
A heavily doped layer is formed as the plate layer of the storage capacitor by using a deposition process, controlling the doping concentration of the plate layer, and by setting the storage capacitor between the semiconductor structure and the substrate structure, adjacent storage capacitors share the plate layer.
The storage capacity of storage capacitors is improved, the damage to the plate layer by the ion implantation process is avoided, the size of the device is reduced, and the integration of the device is improved.
Smart Images
Figure CN223231508U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the field of semiconductor integrated circuit manufacturing and relates to a semiconductor device. Background Art
[0002] The basic storage unit of Dynamic Random Access Memory (DRAM) is usually composed of a storage capacitor and a transistor. Currently, there are two ways to integrate capacitors in devices. One way is to integrate the storage capacitor in the substrate on one side of the transistor, such as Figure 1 As shown in FIG, it is a schematic diagram of the structure of a DRAM device, including a transistor structure 01, a substrate 02, a deep trench 021, a lower electrode 03, a dielectric layer 04 and an upper electrode 05. A deep trench is first formed in the substrate, and then the lower electrode of the storage capacitor is formed on the surface of the substrate on the inner wall of the trench by ion implantation. Then, a dielectric layer and a polysilicon upper electrode filling the trench are formed in the deep trench. However, the doping concentration of the lower electrode formed by the storage capacitor of this structure is difficult to control, and the lower electrode is easily damaged. The area of the storage capacitor and the distance between the upper and lower electrodes of the storage capacitor are also limited by the process and device size. The storage capacity of the obtained storage capacitor is relatively weak. Another method is to make a storage capacitor separately above the substrate, such as Figure 2 , which is a schematic structural diagram of another DRAM device, in which the storage capacitor is integrated above the substrate. However, the storage capacitor takes up a large space, which significantly reduces the integration of the device.
[0003] Therefore, there is an urgent need to find a semiconductor device that can improve the storage capacity of the storage capacitor and increase the device integration. Summary of the Invention
[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a semiconductor device for solving the problem in the prior art that it is difficult to improve the storage capacity of the storage capacitor while improving the integration of the device.
[0005] To achieve the above-mentioned and other related purposes, the present invention provides a semiconductor device, comprising:
[0006] A substrate structure comprising at least a first isolation layer, a laminated structure, and a second isolation layer stacked in sequence, wherein the laminated structure comprises N electrode layers and N-1 intermediate dielectric layers, wherein the N electrode layers and the N-1 intermediate dielectric layers are alternately stacked in sequence, where N is an integer not less than 3;
[0007] a semiconductor structure located on an upper surface of the substrate structure, the semiconductor structure comprising M spaced apart device structures, where M is a positive integer not greater than N-1;
[0008] M first electrodes, electrically connected to the electrode layers on the upper and lower sides of different intermediate dielectric layers respectively;
[0009] M second electrodes are electrically connected to the electrode layers on the upper and lower sides of different intermediate dielectric layers, respectively, and each of the second electrodes is electrically connected to a different electrode layer with each of the first electrodes.
[0010] Optionally, the substrate structure further includes a base, and the first isolation layer covers an upper surface of the base.
[0011] Optionally, the doping concentration of each of the electrode layers is the same; and the thicknesses of different electrode layers are different.
[0012] Optionally, at least two of the first electrodes are electrically connected to the same electrode layer; and at least two of the second electrodes are electrically connected to the same electrode layer.
[0013] Optionally, the semiconductor structure also includes a first conductive type epitaxial layer, and the device structure includes a second conductive type first region and a second conductive type second region located on the upper surface of the epitaxial layer, a gate structure located on the upper surface of the epitaxial layer, a third electrode, a fourth electrode and a fifth electrode, the first region and the second region are located on two sides of the gate structure opposite to each other, the third electrode is electrically connected to the first region, the fourth electrode is electrically connected to the second region, and the fifth electrode is electrically connected to the gate structure.
[0014] Optionally, the gate structure includes a gate dielectric layer and a gate conductive layer stacked in sequence, wherein an end of the gate conductive layer close to the first region extends above the first region, and an end of the gate conductive layer close to the second region extends above the second region.
[0015] Optionally, a third isolation layer is further provided in the epitaxial layer, penetrating the epitaxial layer, the second isolation layer, the stacked structure and the first isolation layer, and the third isolation layer surrounds the area where the M device structures are located.
[0016] Optionally, the first electrode includes a first conductive plug, each of the first conductive plugs penetrates all the plate layers and the intermediate dielectric layer, the second isolation layer and the epitaxial layer above the plate layer electrically connected to the first conductive plug, each of the first conductive plugs is insulated from the epitaxial layer and the plate layer it penetrates, and the second isolation layer is above the plate layer electrically connected to the first conductive plug, the first conductive plug only penetrates the second isolation layer and the epitaxial layer and is insulated from the epitaxial layer; the second electrode includes a second conductive plug, each of the second conductive plugs penetrates all the plate layers and the intermediate dielectric layer, the second isolation layer and the epitaxial layer above the plate layer electrically connected to the second conductive plug, each of the second conductive plugs is insulated from the epitaxial layer and the plate layer it penetrates, and the second isolation layer is above the plate layer electrically connected to the second conductive plug, the second conductive plug only penetrates the second isolation layer and the epitaxial layer and is insulated from the epitaxial layer.
[0017] Optionally, the semiconductor device is further provided with a first interconnection layer, multiple second interconnection layers, a third interconnection layer and a fourth interconnection layer, multiple first interconnection layers are respectively electrically connected to different first electrodes, multiple second interconnection layers are respectively electrically connected to different second electrodes and the fourth electrodes corresponding to the second electrodes, multiple third interconnection layers are respectively electrically connected to different third electrodes, and multiple fourth interconnection layers are respectively electrically connected to different fifth electrodes.
[0018] Optionally, the semiconductor structure further includes an interlayer dielectric layer covering an exposed surface of the device structure, and both the first electrode and the second electrode penetrate the interlayer dielectric layer.
[0019] As described above, the semiconductor device of the present invention forms a heavily doped layer as the plate layer of the storage capacitor by adopting a deposition process, which facilitates the control of the doping concentration of the plate layer, and at the same time makes the ions in the plate layer evenly distributed, avoids the damage of the plate layer by the ion implantation process, ensures the quality of the plate layer, and improves the storage capacity of the storage capacitor; by arranging the stacked structure containing multiple storage capacitors in the device between the semiconductor structure and the base in the substrate structure, and sharing a plate layer between two adjacent storage capacitors, the size of the device is reduced, the integration of the device is improved, and it has high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 Shown is a structural diagram of a DRAM device.
[0021] Figure 2 Shown is a schematic diagram of the structure of another DRAM device.
[0022] Figure 3 Shown is a schematic structural diagram of a semiconductor device of the present invention.
[0023] Explanation of Figure Numbers
[0024] 01 Transistor Structure
[0025] 02 Substrate
[0026] 021 Deep Groove
[0027] 03 Lower electrode
[0028] 04 Dielectric layer
[0029] 05 Upper electrode
[0030] 1 Substrate structure
[0031] 11 base
[0032] 12. First isolation layer
[0033] 13. Laminated structure
[0034] 131 plate layer
[0035] 132 Intermediate dielectric layer
[0036] 14 Second isolation layer
[0037] 15 Third isolation layer
[0038] 2 Semiconductor structure
[0039] 21 epitaxial layer
[0040] 22 Device Structure
[0041] 23 Gate structure
[0042] 231 gate dielectric layer
[0043] 232 gate conductive layer
[0044] 233 Isolation Side Wall
[0045] 24 First contact layer
[0046] 25 Second contact layer
[0047] 26 Third contact layer
[0048] 27 Fourth contact layer
[0049] 28 Fifth contact layer
[0050] 3 interlayer dielectric layer
[0051] 4 Insulation layer
[0052] 41 First Interconnection Layer
[0053] 42 Second interconnect layer
[0054] 43 Third Interconnection Layer
[0055] 44 Fourth interconnection layer
[0056] 5. First electrode
[0057] 51 first conductive plug
[0058] 52 third conductive plug
[0059] 53 first dielectric layer
[0060] 6 Second electrode
[0061] 61 second conductive plug
[0062] 62 fourth conductive plug
[0063] 63 second dielectric layer
[0064] 7 Third electrode
[0065] 8 Fourth electrode
[0066] 9 Fifth electrode DETAILED DESCRIPTION
[0067] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different perspectives and applications without departing from the spirit of the present invention.
[0068] See also Figure 3 It should be noted that the illustrations provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components relevant to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be arbitrarily changed, and the component layout may also be more complex.
[0069] This embodiment provides a semiconductor device such as Figure 3As shown, it is a schematic structural diagram of the semiconductor device, including a substrate structure 1, a semiconductor structure 2, a first electrode 5 and a second electrode 6, wherein the substrate structure 1 includes at least a first isolation layer 12, a stacked structure 13 and a second isolation layer 14 stacked in sequence, and the stacked structure 13 includes N-layer electrode layers 131 and N-1-layer intermediate dielectric layers 132, which are alternately stacked in sequence, wherein N is an integer not less than 3; the semiconductor structure 2 is located on the upper surface of the substrate structure 1, and the semiconductor structure 2 includes M spaced device structures 22, wherein M is a positive integer not greater than N-1; the M first electrodes 5 are respectively electrically connected to a electrode layer 131 on the upper and lower sides of different intermediate dielectric layers 132; the M second electrodes 6 are respectively electrically connected to a electrode layer 131 on the upper and lower sides of different intermediate dielectric layers 132, and each second electrode 6 is electrically connected to a different electrode layer 131 of each first electrode 5.
[0070] As an example, the substrate structure 1 further includes a base 11 , and the first isolation layer 12 covers the upper surface of the base 11 .
[0071] Specifically, the substrate 11 is a process platform for manufacturing semiconductor devices. While ensuring the performance of the device, the thickness, size and shape of the substrate 11 can be selected according to actual conditions.
[0072] Specifically, the material of the substrate 11 includes silicon, diamond, sapphire, gallium nitride, silicon carbide or other suitable materials. In this embodiment, an intrinsic silicon layer is used as the substrate 11.
[0073] Specifically, the material of the first isolation layer 12 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride or other suitable dielectric materials; the material of the second isolation layer 14 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride or other suitable dielectric materials.
[0074] Specifically, while ensuring device performance, the thickness of the first isolation layer 12 can be selected according to actual conditions; the thickness of the second isolation layer 14 can also be selected according to actual conditions.
[0075] Specifically, the material of the plate layer 131 includes a heavily doped silicon layer or other suitable conductive materials. In this embodiment, a heavily doped silicon layer formed by a deposition process is used as the plate layer 131 .
[0076] As an example, the doping concentration of each electrode layer 131 is the same, that is, the doping concentration of each electrode layer 131 in the stacked structure 13 is the same.
[0077] Specifically, under the premise of ensuring device performance, the doping concentrations of the electrode layers 131 may be different.
[0078] As an example, different electrode layers 131 have different thicknesses, that is, the thicknesses of the electrode layers 131 in the stacked structure 13 are all different.
[0079] Specifically, under the condition of ensuring the device performance, the thicknesses of the electrode layers 131 in the stacked structure 13 may be completely the same, or the thicknesses of some of the electrode layers 131 may be the same.
[0080] Specifically, the dielectric constant and thickness of each intermediate dielectric layer 132 affect the capacitance value of the capacitor structure formed by the intermediate dielectric layer 132 and the upper and lower plate layers 131 . While ensuring device performance, the thickness of each intermediate dielectric layer 132 is selected according to actual conditions.
[0081] Specifically, the storage capacitor in the device at least includes a capacitor structure composed of an intermediate dielectric layer 132 and electrode layers 131 on its upper and lower sides.
[0082] As an example, at least two first electrodes 5 are electrically connected to the same plate layer 131, that is, in the multiple storage capacitors in the stacked structure 13, three spaced-apart plate layers 131 constitute two adjacent storage capacitors, and the first electrodes 5 of the two storage capacitors are electrically connected to the same plate layer 131. In this embodiment, the stacked structure 13 is provided with four plate layers 131 and three intermediate dielectric layers 132, and each storage capacitor is a capacitor structure consisting of two plate layers 131 on the upper and lower sides of an intermediate dielectric layer 132.
[0083] Specifically, while ensuring device performance, different first electrodes 5 may also be electrically connected to different electrode layers 131 , respectively.
[0084] As an example, at least two second electrodes 6 are electrically connected to the same plate layer 131. That is, for the multiple storage capacitors in the stacked structure 13, three spaced-apart plate layers 131 constitute two adjacent storage capacitors, and the second electrodes 6 of the two storage capacitors are electrically connected to the same plate layer 131. In this embodiment, for the multiple storage capacitors in the stacked structure 13, no two adjacent storage capacitors share a plate. For example, two adjacent storage capacitors constituted by the Lth plate layer 131, the L+1th plate layer 131, and the L+2th plate layer 131 share the L+1th plate layer 131, where L is an integer greater than or equal to 1 and less than or equal to N-2.
[0085] As an example, the semiconductor structure 2 also includes a first conductive type epitaxial layer 21, and the device structure 22 includes a second conductive type first region and a second conductive type second region located on the upper surface of the epitaxial layer 21, a gate structure 23 located on the upper surface of the epitaxial layer 21, a third electrode 7, a fourth electrode 8 and a fifth electrode 9, the first region and the second region are located on two sides of the gate structure 23 opposite to each other, the third electrode 7 is electrically connected to the first region, the fourth electrode 8 is electrically connected to the second region, and the fifth electrode 9 is electrically connected to the gate structure 23.
[0086] Specifically, the first conductive type includes one of N type and P type, the second conductive type includes one of N type and P type, and the first conductive type is opposite to the second conductive type.
[0087] Specifically, the first region is the source region of the device, the second region is the drain region of the device, the contact type between the first region and the third electrode 7 is ohmic contact, and the contact type between the second region and the fourth electrode 8 is ohmic contact.
[0088] Specifically, epitaxial layer 21 covers the upper surface of substrate structure 1. The doping concentrations of the first and second regions are greater than that of epitaxial layer 21. While ensuring device performance, the thickness and doping concentration of epitaxial layer 21 can be selected based on actual conditions. The doping concentration, thickness, and shape of the first region can also be selected based on actual conditions. The doping concentration, thickness, and shape of the second region can also be selected based on actual conditions. Thickness here refers to the distance between the lower and upper surfaces of each portion.
[0089] Specifically, the method of forming the epitaxial layer 21 includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0090] Specifically, while ensuring device performance, the distance between two adjacent device structures 22 can be selected according to actual conditions.
[0091] As an example, the epitaxial layer 21 is further provided with a third isolation layer 15 that penetrates the epitaxial layer 21 , the second isolation layer 14 , the stacked structure 13 and the first isolation layer 12 . The third isolation layer 15 surrounds the area where the M device structures 22 are located.
[0092] Specifically, the third isolation layer 15 includes a first isolation portion and a second isolation portion connected in sequence. The second isolation portion and the second isolation portion are connected end-to-end in sequence and surround the region where M device structures 22 are located. A predetermined distance is provided between the third isolation layer 15 and its adjacent device structures 22. In this embodiment, the third isolation layer 15 surrounds the region where three device structures are located, i.e., M = 3.
[0093] Specifically, since the doped layer formed by ion implantation will damage the area where the ions are doped, in order to avoid using the ion implantation process to form the first electrode layer 131 and the second electrode layer 131, the intermediate dielectric layer 132 in the stacked structure 13 is usually formed after forming the epitaxial layer 21 and before forming each first region and each second region.
[0094] Specifically, forming the intermediate dielectric layer 132 in the stacked structure 13 includes the following steps: forming N+1 sacrificial layers and N-layer plate layers 131 alternately stacked on the upper surface of the substrate 11; forming an epitaxial layer 21 covering the upper surface of the N+1 sacrificial layer; forming a patterned first photoresist layer on the upper surface of the epitaxial layer 21, and etching the epitaxial layer 21, each sacrificial layer and each plate layer 131 in sequence based on the patterned first photoresist layer to obtain a first trench; removing the first photoresist layer and forming a support layer filling the first trench; after forming the support layer, A patterned second photoresist layer is formed on the upper surface of the epitaxial layer 21. A second trench is formed based on the patterned second photoresist layer, penetrating the epitaxial layer 21, each sacrificial layer, and each plate layer 131. Simultaneously, each sacrificial layer is removed based on the second trench. The second photoresist layer is removed, and a first isolation layer 12 is formed to fill the gap between the substrate 11 and the first plate layer 131. An intermediate dielectric layer 132 is formed to form the gap between two adjacent plate layers 131. A second isolation layer 14 is formed to fill the gap between the Nth plate layer 131 and the epitaxial layer 21. Furthermore, a second isolation portion is formed to fill the second trench. The gap here refers to the gap created after removing the sacrificial layer.
[0095] Specifically, the material of the sacrificial layer includes silicon germanium or other materials with a high etching selectivity ratio with the plate layer 131 and the epitaxial layer 21. Preferably, SiGe with a high etching selectivity ratio of 1:300 with silicon is used. x Ge y layers as sacrificial layers.
[0096] Specifically, forming a patterned first photoresist layer, forming a patterned second photoresist layer, removing the first photoresist layer and removing the second photoresist layer are all photoresist coating, drying, exposure, development and stripping processes commonly used in the photolithography process, which will not be repeated here.
[0097] Specifically, the method of forming the first trench includes dry etching, wet etching or other suitable methods, that is, etching the epitaxial layer 21 and alternately etching the sacrificial layer and the plate layer 131 from top to bottom by dry etching or wet etching.
[0098] Specifically, the material of the support layer includes silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride or other suitable dielectric materials.
[0099] Specifically, the method of forming the support layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0100] Specifically, during the formation of the second trench, the etching method for each film layer includes dry etching, wet etching, or other suitable methods; the method for removing the sacrificial layer includes wet etching or other suitable methods. In this embodiment, oxalic acid is used as a wet etchant to remove each sacrificial layer.
[0101] Specifically, the method for simultaneously forming the intermediate dielectric layer 132 , the first isolation layer 12 , the second isolation layer 14 and the second isolation portion includes atomic layer deposition or other suitable methods.
[0102] Specifically, after forming the second isolation portion, the intermediate dielectric layer 132 , the first isolation layer 12 and the second isolation layer 14 , the step of removing the support layer and forming the first isolation portion filling the first trench is also included.
[0103] Specifically, the method of removing the support layer includes dry etching, wet etching or other suitable methods; the method of forming the first isolation portion includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0104] Specifically, the first isolation portion and the second isolation portion are made of the same material. The support layer is removed and the first isolation portion is formed with the same material as the second isolation portion to reduce the stress difference between the first isolation portion and the second isolation portion.
[0105] Specifically, while ensuring the performance of the device, the support layer may also be retained, that is, the support layer may be used as the first isolation portion.
[0106] As an example, the first electrode 5 includes a first conductive plug 51, each of which penetrates all the plate layers 131 and the intermediate dielectric layer 132, the second isolation layer 14 and the epitaxial layer 21 above the plate layer 131 electrically connected to the first conductive plug 51, and each first conductive plug 51 is insulated from the epitaxial layer 21 and the plate layer 131 it penetrates, and the plate layer 131 electrically connected to the first conductive plug 51 is above the second isolation layer 14, and the first conductive plug 51 only penetrates the second isolation layer 14 and the epitaxial layer 21 and is between the epitaxial layer 21 and the first conductive plug 51. Insulation; the second electrode 6 includes a second conductive plug 61, each second conductive plug 61 penetrates all the electrode layers 131 and the intermediate dielectric layer 132, the second isolation layer 14 and the epitaxial layer 21 above the electrode layer 131 electrically connected to the second conductive plug 61, and each second conductive plug 61 is insulated from the epitaxial layer 21 and the electrode layer 131 it penetrates, and the second isolation layer 14 is above the electrode layer 131 electrically connected to the second conductive plug 61, and the second conductive plug 61 only penetrates the second isolation layer 14 and the epitaxial layer 21 and is insulated from the epitaxial layer 21.
[0107] Specifically, a first conductive plug 51 and a second conductive plug 61 are formed in a region corresponding to a device structure 22 .
[0108] Specifically, forming the first conductive plug 51 includes the following steps: forming a first contact hole penetrating the epitaxial layer 21, the second isolation layer 14 and the corresponding film layer in the stacked structure 13 at the corresponding position of the area surrounded by the second isolation layer 14; forming a first dielectric layer 53 covering the inner wall of the first contact hole and forming a first conductive plug 51 filling the first contact hole; repeating the steps of forming the first contact hole, the first dielectric layer 53 and the first conductive plug 51 until M corresponding first conductive plugs 51 are formed, and two adjacent first conductive plugs 51 are separated by a preset distance.
[0109] Specifically, forming the second conductive plug 61 includes the following steps: forming a second contact hole penetrating the epitaxial layer 21, the second isolation layer 14 and the corresponding film layer in the stacked structure 13 at the corresponding position of the area surrounded by the second isolation layer 14; forming a second dielectric layer 63 covering the inner wall of the second contact hole and forming a second conductive plug 61 filling the second contact hole; repeating the steps of forming the second contact hole, the second dielectric layer 63 and the second conductive plug 61 until M corresponding second conductive plugs 61 are formed, and a preset distance is separated between two adjacent second conductive plugs 61, and the second conductive plug 61 is separated from the first conductive plug 51 by a preset distance.
[0110] Specifically, while ensuring device performance, the opening size and opening shape of the first contact hole can be selected according to actual conditions; the thickness of the first dielectric layer 53 can be selected according to actual conditions; the opening size and opening shape of the second contact hole can be selected according to actual conditions; and the thickness of the second dielectric layer 63 can be selected according to actual conditions.
[0111] Specifically, the first conductive plug 51 is electrically connected to the electrode layer 131 exposed at the bottom of the first contact hole it fills, and the second conductive plug 61 is electrically connected to the electrode layer 131 exposed at the bottom of the second contact hole it fills. The first dielectric layer 53 is used to insulate the first conductive plug 51 from the epitaxial layer 21 and the electrode layer 131 exposed on the inner wall of the first contact hole. The second dielectric layer 63 is used to insulate the second conductive plug 61 from the epitaxial layer 21 and the electrode layer 131 exposed on the inner wall of the second contact hole. The material of the first dielectric layer 53 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride or other suitable dielectric materials; the material of the second dielectric layer 63 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride or other suitable dielectric materials.
[0112] Specifically, the material of the first conductive plug 51 includes polysilicon, TiN, W or other suitable conductive materials; the material of the second conductive plug 61 includes polysilicon, TiN, W or other suitable conductive materials.
[0113] Specifically, after forming each of the first conductive plugs 51 and each of the second conductive plugs 61 , the gate structure 23 , the first region, and the second region in each of the device structures 22 are formed in sequence.
[0114] As an example, the gate structure 23 includes a gate dielectric layer 231 and a gate conductive layer 232 stacked in sequence. The end of the gate conductive layer 232 close to the first region extends above the first region, and the end of the gate conductive layer 232 close to the second region extends above the second region.
[0115] Specifically, the gate structure 23 is further provided with an isolation spacer 233 covering the sidewalls of the gate conductive layer 232 and the gate dielectric layer 231 . The thickness of the isolation spacer 233 can be selected according to actual conditions while ensuring device performance.
[0116] Specifically, after forming each first conductive plug 51 and each second conductive plug 61, a gate structure 23 is formed on the upper surface of the epitaxial layer 21 in the region corresponding to each device structure 22, and the gate structure 23 is spaced apart from the first conductive plug 51 and the second conductive plug 61 in the region corresponding to the device structure 22; after forming the gate structure 23, a first region and a second region are formed on the upper surface of the epitaxial layer 21 on both sides of each gate structure 23 in the direction of the first conductive plug 51 pointing to the second conductive plug 61, the first region is located on a side of the gate structure 23 close to the first conductive plug 51 and is spaced apart from the first conductive plug 51, and the second region is located on a side of the gate structure 23 close to the second conductive plug 61 and is spaced apart from the second conductive plug 61.
[0117] Specifically, while ensuring device performance, the distance between the gate structure 23 and the first conductive plug 51 in the area corresponding to each device structure 22 can be selected according to actual conditions; the distance between the gate structure 23 and the second conductive plug 61 in the area corresponding to each device structure 22 can be selected according to actual conditions.
[0118] Specifically, the method for forming the first region includes ion implantation or other suitable methods; the method for forming the second region includes ion implantation or other suitable methods. In this embodiment, an ion implantation process is used to simultaneously form the doped regions on the upper surface of the epitaxial layer 21 on both sides of the gate structure 23. After the ion implantation is completed, a well-pull-in process is performed so that, in the region corresponding to each device structure 22, the sidewall of the first region proximate to the second region extends to directly below the gate conductive layer 232 of the region, and the sidewall of the second region proximate to the first region extends to directly below the gate conductive layer 232 of the region.
[0119] As an example, the semiconductor device is further provided with an interlayer dielectric layer 3 covering the upper surface of the semiconductor structure 2 , and both the first electrode 5 and the second electrode 6 penetrate the interlayer dielectric layer 3 .
[0120] Specifically, each first electrode 5 also includes a plurality of third conductive plugs 52 electrically connected to each first conductive plug 51, and the second electrode 6 also includes a plurality of fourth conductive plugs 62 electrically connected to each second conductive plug 61. Each third conductive plug 52 penetrates the interlayer dielectric layer 3 and is electrically connected to the corresponding first conductive plug 51, and each fourth conductive plug 62 penetrates the interlayer dielectric layer 3 and is electrically connected to the corresponding second conductive plug 61. Each third electrode 7 penetrates the interlayer dielectric layer 3 and is electrically connected to the corresponding first region, and each fourth electrode 8 penetrates the interlayer dielectric layer 3 and is electrically connected to the corresponding second region. Each fifth electrode 9 penetrates the interlayer dielectric layer 3 above the corresponding gate structure 23 and is electrically connected to the gate conductive layer 232 in the gate structure 23.
[0121] Specifically, while ensuring device performance, the thickness of the interlayer dielectric layer 3 can be selected according to actual conditions; the cross-sectional size and cross-sectional shape of each third conductive plug 52 can be selected according to actual conditions; the cross-sectional size and cross-sectional shape of each fourth conductive plug 62 can be selected according to actual conditions; the cross-sectional size and cross-sectional shape of each third electrode 7 can be selected according to actual conditions; the cross-sectional size and cross-sectional shape of each fourth electrode 8 can be selected according to actual conditions; and the cross-sectional size and cross-sectional shape of each fifth electrode 9 can be selected according to actual conditions.
[0122] Specifically, the material of the interlayer dielectric layer 3 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride or other suitable dielectric materials; the material of the third conductive plug 52 includes titanium nitride, tungsten, titanium, gold, silver, copper, nickel, aluminum or other suitable conductive materials; the material of the fourth conductive plug 62 includes titanium nitride, tungsten, titanium, gold, silver, copper, nickel, aluminum or other suitable conductive materials; the material of the third electrode 7 includes titanium nitride, tungsten, titanium, gold, silver, copper, nickel, aluminum or other suitable conductive materials; the material of the fourth electrode 8 includes titanium nitride, tungsten, titanium, gold, silver, copper, nickel, aluminum or other suitable conductive materials; the material of the fifth electrode 9 includes titanium nitride, tungsten, titanium, gold, silver, copper, nickel, aluminum or other suitable conductive materials.
[0123] Specifically, the upper surfaces of each first region, each second region and each gate conductive layer 232 are also respectively provided with a first contact layer 24, a second contact layer 25 and a third contact layer 26. The first contact layer 24 is used to reduce the contact resistance between the third electrode 7 and the first region corresponding to the third electrode 7, the second contact layer 25 is used to reduce the contact resistance between the fourth electrode 8 and the second region corresponding to the fourth electrode 8, and the third contact layer 26 is used to reduce the contact resistance between the fifth electrode 9 and the gate conductive layer 232 corresponding to the fifth electrode 9.
[0124] Specifically, a fourth contact layer 27 is provided on the upper surface of each first conductive plug 51 to reduce the contact resistance between each first conductive plug 51 and the third conductive plug 52 corresponding to the first conductive plug 51, and a fifth contact layer 28 is provided on the upper surface of each second conductive plug 61 to reduce the contact resistance between each second conductive plug 61 and the fourth conductive plug 62 corresponding to the second conductive plug 61.
[0125] Specifically, the first contact layer 24 is made of metal silicide, titanium nitride, or other suitable materials; the second contact layer 25 is made of metal silicide, titanium nitride, or other suitable materials; the third contact layer 26 is made of metal silicide, titanium nitride, or other suitable materials; the fourth contact layer 27 is made of metal silicide, titanium nitride, or other suitable materials; and the fifth contact layer 28 is made of metal silicide, titanium nitride, or other suitable materials. Preferably, in this embodiment, the first contact layer 24, the second contact layer 25, and the third contact layer 26 are metal silicide layers generated by a reaction between a metal layer and silicon on the surface of the epitaxial layer 21 and the gate conductive layer 232.
[0126] Specifically, while ensuring device performance, the thickness of each contact layer (the first contact layer 24 , the second contact layer 25 , the third contact layer 26 , the fourth contact layer 27 and the fifth contact layer 28 ) can be selected according to actual conditions.
[0127] As an example, the semiconductor device is further provided with a first interconnection layer 41, multiple second interconnection layers 42, a third interconnection layer 43 and a fourth interconnection layer 44. The multiple first interconnection layers 41 are respectively electrically connected to different first electrodes 5, the multiple second interconnection layers 42 are respectively electrically connected to different second electrodes 6 and the fourth electrodes 8 corresponding to the second electrodes 6, the multiple third interconnection layers 43 are respectively electrically connected to different third electrodes 7, and the multiple fourth interconnection layers 44 are respectively electrically connected to different fifth electrodes 9.
[0128] Specifically, the semiconductor device further includes an insulating layer 4 covering the interlayer dielectric layer 3 and the exposed upper surfaces of the electrodes. The first interconnection layers 41 , the second interconnection layers 42 , the third interconnection layers 43 and the fourth interconnection layers 44 respectively penetrate the insulating layer 4 .
[0129] Specifically, while ensuring device performance, the cross-sectional size and cross-sectional shape of each interconnection layer (first interconnection layer 41, second interconnection layer 42, third interconnection layer 43 and fourth interconnection layer 44) can be selected according to actual conditions; the distance between the first interconnection layer 41, second interconnection layer 42, third interconnection layer 43 and fourth interconnection layer 44 can be selected according to actual conditions.
[0130] Specifically, the material of the first interconnection layer 41 includes titanium nitride, tungsten, titanium, gold, silver, copper, nickel, aluminum, platinum or other suitable conductive materials; the material of the second interconnection layer 42 includes titanium nitride, tungsten, titanium, gold, silver, copper, nickel, aluminum, platinum or other suitable conductive materials; the material of the third interconnection layer 43 includes titanium nitride, tungsten, titanium, gold, silver, copper, nickel, aluminum, platinum or other suitable conductive materials; the material of the fourth interconnection layer 44 includes titanium nitride, tungsten, titanium, gold, silver, copper, nickel, aluminum, platinum or other suitable conductive materials.
[0131] Specifically, the heavily doped layers formed by the deposition process are used as the respective electrode layers 131 constituting the storage capacitors in the device, which facilitates the control of the doping concentration of the electrode layers 131 and makes the ions in the electrode layers 131 uniformly distributed, thereby avoiding the problems of uneven distribution of doped particles and damage to the electrode layers 131 produced by the ion implantation process, thereby ensuring the quality of each electrode layer 131 and improving the storage capacity of the storage capacitor and the performance of the device.
[0132] Specifically, by arranging the storage capacitors formed by each electrode layer 131 and each intermediate dielectric layer 132 below the semiconductor structure 2, and two adjacent storage capacitors share one electrode layer 131, the storage capacitors are prevented from occupying a large space, thereby reducing the size of the device and improving the integration of the device.
[0133] In summary, the semiconductor device of the present invention improves the structure of the semiconductor device and adopts a heavily doped layer formed by a deposition process as each plate layer constituting the storage capacitor in the device, which facilitates the control of the doping concentration of the plate layer and makes the ions in the plate layer uniform, thus avoiding the damage of the plate layer by the ion implantation process, ensuring the quality of the plate layer, and improving the storage capacity of the storage capacitor and the performance of the device; by arranging the storage capacitor composed of each plate layer and each intermediate dielectric layer between the substrate and each device in the semiconductor structure, and two adjacent storage capacitors share one plate layer, it avoids the storage capacitor from occupying a large space, reduces the size of the device, and improves the integration of the device. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.
[0134] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed in the present invention are intended to be covered by the claims of the present invention.
Claims
1. A semiconductor device, characterized in that: include: A substrate structure comprising at least a first isolation layer, a laminated structure, and a second isolation layer stacked in sequence, wherein the laminated structure comprises N electrode layers and N-1 intermediate dielectric layers, wherein the N electrode layers and the N-1 intermediate dielectric layers are alternately stacked in sequence, where N is an integer not less than 3; a semiconductor structure located on an upper surface of the substrate structure, the semiconductor structure comprising M spaced apart device structures, where M is a positive integer not greater than N-1; M first electrodes, electrically connected to the electrode layers on the upper and lower sides of different intermediate dielectric layers respectively; M second electrodes are electrically connected to the electrode layers on the upper and lower sides of different intermediate dielectric layers, respectively, and each of the second electrodes is electrically connected to a different electrode layer with each of the first electrodes.
2. The semiconductor device according to claim 1, wherein: The substrate structure further includes a base, and the first isolation layer covers the upper surface of the base.
3. The semiconductor device according to claim 1, wherein: The doping concentration of each of the electrode layers is the same; and the thicknesses of different electrode layers are different.
4. The semiconductor device according to claim 1, wherein: At least two of the first electrodes are electrically connected to the same electrode layer; and at least two of the second electrodes are electrically connected to the same electrode layer.
5. The semiconductor device according to claim 1, wherein: The semiconductor structure also includes a first conductive type epitaxial layer, and the device structure includes a second conductive type first region and a second conductive type second region located on the upper surface of the epitaxial layer, a gate structure located on the upper surface of the epitaxial layer, a third electrode, a fourth electrode and a fifth electrode, the first region and the second region are located on two opposite sides of the gate structure, the third electrode is electrically connected to the first region, the fourth electrode is electrically connected to the second region, and the fifth electrode is electrically connected to the gate structure.
6. The semiconductor device according to claim 5, wherein: The gate structure includes a gate dielectric layer and a gate conductive layer stacked in sequence. An end of the gate conductive layer close to the first region extends above the first region, and an end of the gate conductive layer close to the second region extends above the second region.
7. The semiconductor device according to claim 5, wherein: The epitaxial layer is further provided with a third isolation layer that penetrates the epitaxial layer, the second isolation layer, the stacked structure and the first isolation layer, and the third isolation layer surrounds the area where the M device structures are located.
8. The semiconductor device according to claim 5, wherein: The first electrode includes a first conductive plug, each of which penetrates all the plate layers and the intermediate dielectric layer, the second isolation layer and the epitaxial layer above the plate layer electrically connected to the first conductive plug, and each of the first conductive plugs is insulated from the epitaxial layer and the plate layer it penetrates, and the second isolation layer is above the plate layer electrically connected to the first conductive plug, and the first conductive plug only penetrates the second isolation layer and the epitaxial layer and is insulated from the epitaxial layer; the second electrode includes a second conductive plug, each of which penetrates all the plate layers and the intermediate dielectric layer, the second isolation layer and the epitaxial layer above the plate layer electrically connected to the second conductive plug, and each of the second conductive plugs is insulated from the epitaxial layer and the plate layer it penetrates, and the second isolation layer is above the plate layer electrically connected to the second conductive plug, and the second conductive plug only penetrates the second isolation layer and the epitaxial layer and is insulated from the epitaxial layer.
9. The semiconductor device according to claim 5, wherein: The semiconductor device is also provided with a first interconnection layer, multiple second interconnection layers, a third interconnection layer and a fourth interconnection layer. The multiple first interconnection layers are respectively electrically connected to different first electrodes, the multiple second interconnection layers are respectively electrically connected to different second electrodes and the fourth electrodes corresponding to the second electrodes, the multiple third interconnection layers are respectively electrically connected to different third electrodes, and the multiple fourth interconnection layers are respectively electrically connected to different fifth electrodes.
10. The semiconductor device according to claim 1, wherein: The semiconductor structure further includes an interlayer dielectric layer covering the exposed surface of the device structure, and the first electrode and the second electrode both penetrate the interlayer dielectric layer.