Double NMOS (N-channel metal oxide semiconductor) tube
By stacking the dual NMOS tube grains back to back and through short-circuit design, the problem of insufficient power density in the prior art is solved, and higher switching current and power density are achieved, suitable for power management.
Patent Information
- Application Number
- CN202421929053.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-09
- Publication Date
- 2025-08-15
- Estimated Expiration
- 2034-08-09
AI Technical Summary
The existing dual NMOS tubes are insufficient in power management, making it difficult to meet the needs of high-capacity lithium batteries.
The dual NMOS tube structure is adopted to stack two grains back to back up and down, and short-connected through the metal frame and metal sheet, keeping the length and width of the device unchanged while increasing the grain area or reducing the device size to improve power density.
Without changing the device size, the switching current is increased, the power density is increased, and the practical application needs of power management are met.
Smart Images
Figure CN223231512U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a semiconductor product, in particular to a MOS tube. Background Art
[0002] In existing power management applications, dual NMOS transistors are commonly used to control the charge and discharge of lithium secondary batteries. Figure 1 The diagram shows a circuit of a dual NMOS transistor 10, which includes a first MOS transistor Q1 and a second MOS transistor Q2, wherein the first MOS transistor Q1 is used for discharge control of a lithium secondary battery, and the second MOS transistor Q2 is used for discharge control of a lithium secondary battery.
[0003] The existing dual NMOS transistor 10 structure is typically packaged by placing two bare dies on the same horizontal plane on a metal frame. This is followed by wire bonding, plastic encapsulation, and other packaging operations, ultimately forming a discrete device that can be soldered to a circuit board for use. For example, in a mobile phone's lithium-ion battery, a protection circuit board is installed at one end of the cell. This circuit board houses a dual NMOS transistor 10 and an IC that controls it. As mobile phones become increasingly powerful, lithium-ion battery capacity increases, correspondingly demanding higher power density for the dual NMOS transistor 10. This, in turn, necessitates continuous improvements in the bare die and / or packaging. Utility Model Content
[0004] The technical problem to be solved by the present invention is that, in view of the above-mentioned defects of the prior art, the present invention proposes a dual NMOS transistor, which is conducive to improving power density and well meets the practical application of power management.
[0005] The technical solution adopted by the utility model to solve its technical problems includes: providing a dual NMOS tube, including: a metal frame; a first crystal grain, having a first gate and a first source on the front side and a first drain on the back side, which is installed on the metal frame with the front side facing downward; a second crystal grain, having a second gate and a second source on the front side and a second drain on the back side, which is installed on the first crystal grain with the back side facing downward; a metal sheet, which is installed on the front side of the second crystal grain and is used to short-circuit the second gate and the second source with corresponding pins on the metal frame; wherein the second drain is short-circuited with the first drain, and the metal frame is provided with a first gate pin and a first source pin short-circuited with the first gate and the first source, and a second gate pin and a second source pin short-circuited with the second gate and the second source.
[0006] In some embodiments, the metal frame includes a first bump short-circuited with the first source; and a second bump short-circuited with the first gate.
[0007] In some embodiments, the metal sheet includes a first portion short-circuited with the second source electrode and a second portion short-circuited with the second gate electrode.
[0008] In some embodiments, the first die and the second die are the same.
[0009] In some embodiments, the first die and the second die are stacked together in perfect alignment.
[0010] In some embodiments, the first die and the second die are different.
[0011] In some embodiments, an area of the first die is larger than an area of the second die.
[0012] In some embodiments, an area of the first die is smaller than an area of the second die.
[0013] In some embodiments, the dual NMOS transistor is packaged in DFN.
[0014] In some embodiments, the dual NMOS transistor has a length of 4.2 mm and a width of 2.2 mm.
[0015] Compared with the prior art, the dual NMOS tube of the present invention stacks two crystals back to back. On the one hand, while keeping the length and width of the device unchanged, the area of a single crystal can be increased, thereby increasing the switching current it carries. On the other hand, while keeping the switching current it carries, that is, while keeping the area of a single crystal unchanged, the length and width of the device can be reduced, which is beneficial to improving power density and well meeting the practical application of power management. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 The circuit of the dual NMOS tube of the present invention is schematically shown.
[0017] Figure 2 The cross-sectional structure of the dual NMOS tube of the present invention is schematically shown.
[0018] Figure 3 The bottom view structure of the dual NMOS tube of the present invention is shown.
[0019] Figure 4 The top view structure of the dual NMOS tube of the present invention is shown.
[0020] Figure 5 The figure shows the metal frame of the dual NMOS tube of the present invention.
[0021] Figure 6 The first die of the dual NMOS transistor of the present invention is schematically shown.
[0022] Figure 7 The figure shows the cooperation between the first die and the metal frame of the dual NMOS tube of the present invention.
[0023] Figure 8 The diagram illustrates the cooperation between the second die, the first die and the metal frame of the dual NMOS transistor of the present invention.
[0024] Figure 9 The figure shows the coordination between the metal sheet, the second die, the first die and the metal frame of the dual NMOS transistor of the present invention.
[0025] Wherein, the description of the reference numerals is as follows: 10 dual NMOS transistor Q1 first MOS transistor Q2 second MOS transistor; 1 metal frame 11 first bump 12 second bump S1 first source pin G1 first gate pin S2 second source pin G2 second gate pin 2 first die 21 first source 22 first gate 3 second die 31 second source 32 second gate 4 metal sheet 41 first part 42 second part 5 plastic body DETAILED DESCRIPTION
[0026] Now, in conjunction with the accompanying drawings, the preferred embodiments of the present utility model will be described in detail.
[0027] See also Figures 2 to 4 , Figure 2 The cross-sectional structure of the dual NMOS tube of the present invention is schematically shown. Figure 3 The bottom view structure of the dual NMOS tube of the present invention is shown. Figure 4 The top view of the dual NMOS transistor of the present invention is shown. This invention provides a dual NMOS transistor 10 comprising a metal frame 1, a first die 2, a second die 3, a metal sheet 4, and a plastic body 5. This dual NMOS transistor 10 utilizes a DFN (Dual Flat No-lead) package. For example, the length of this dual NMOS transistor 10 is 4.2 mm, and the width is 2.2 mm.
[0028] See also Figure 5 , Figure 5 The metal frame of the dual NMOS transistor of the present invention is shown in FIG. The metal frame 1 includes a first bump 11 and a second bump 12. The metal frame 1 is provided with a first gate pin G1, a first source pin S1, a second gate pin G2, and a second source pin S2.
[0029] See also Figure 6 , Figure 6The first crystal grain of the dual NMOS transistor of the present invention is shown schematically. The first crystal grain 2 has a first gate 22 and a first source 21 on the front side and a first drain (not shown) on the back side.
[0030] See also Figure 7 , Figure 7 The diagram illustrates the coordination between the first die and the metal frame of the dual NMOS transistor of the present invention. The first die 2 is mounted on the metal frame 1, facing downward. Specifically, the first bump 11 is short-circuited with the first source 21; the second bump 12 is short-circuited with the first gate 22.
[0031] See also Figure 8 , Figure 8 The diagram shows the coordination between the second die, the first die, and the metal frame of the dual NMOS transistor of the present invention. The second die 3 is mounted on the first die 2 with the back side facing downwards. The second drain is short-circuited with the first drain.
[0032] It is worth noting that in this embodiment, the first die 2 and the second die 3 are identical. The first die 2 and the second die 3 are completely aligned and stacked together. In other embodiments, the first die 2 and the second die 3 may be different. For example, the area of the first die 2 may be larger than that of the second die 3; or the area of the first die 2 may be smaller than that of the second die 3.
[0033] See also Figure 9 , Figure 9 The figure shows the coordination of the metal sheet, the second die, the first die and the metal frame of the dual NMOS transistor of the present invention. The metal sheet 4 includes a first portion 41 short-circuited with the second source 31 and a second portion 42 short-circuited with the second gate 32.
[0034] Ginseng Figures 1 to 9 The dual NMOS tube 10 of the present invention has a circuit structure as follows: Figure 1 As shown, the first die 2 corresponds to the first MOS transistor Q1, and the second die 3 corresponds to the second MOS transistor Q2. The second drain D2 is short-circuited with the first drain D1. The first gate 22 is short-circuited with the first gate pin G1, and the first source 21 is short-circuited with the first source pin S1. The second gate 32 is short-circuited with the second gate pin G2, and the second source 31 is short-circuited with the first source pin S2.
[0035] Compared with the prior art, the dual NMOS transistor 10 of the present invention stacks two dies 2 and 3 back to back. On the one hand, while keeping the length and width of the device 10 unchanged, the area of the single dies 2 and 3 can be increased, thereby increasing the switching current carried. On the other hand, while keeping the switching current carried, that is, while keeping the area of the single dies 2 and 3 unchanged, the length and width of the device 10 can be reduced, which is beneficial to improving the power density and well meeting the practical application of power management.
[0036] It should be understood that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. For those skilled in the art, the technical solutions described in the above embodiments can be modified, or some of the technical features therein can be replaced by equivalents; and these modifications and replacements should all fall within the scope of protection of the claims attached to the present invention.
Claims
1. A dual NMOS transistor, characterized in that: include: Metal frame; A first crystal die has a first gate and a first source on its front side and a first drain on its back side, and is mounted on the metal frame with its front side facing downward; A second crystal die has a second gate and a second source on its front side and a second drain on its back side, and is mounted on the first crystal die with its back side facing downward; a metal sheet mounted on the front surface of the second die and used for short-circuiting the second gate and the second source with corresponding pins on the metal frame; The second drain is short-circuited with the first drain; the metal frame is provided with a first gate pin and a first source pin short-circuited with the first gate and the first source, and a second gate pin and a second source pin short-circuited with the second gate and the second source.
2. The dual NMOS transistor according to claim 1, characterized in that: The metal frame includes a first bump short-circuited with the first source electrode and a second bump short-circuited with the first gate electrode.
3. The dual NMOS transistor according to claim 1, characterized in that: The metal sheet includes a first portion short-circuited with the second source electrode and a second portion short-circuited with the second gate electrode.
4. The dual NMOS transistor according to claim 1, characterized in that: The first die and the second die are identical.
5. The dual NMOS transistor according to claim 4, characterized in that: The first die and the second die are stacked together in perfect alignment.
6. The dual NMOS transistor according to claim 1, characterized in that: The first die and the second die are different.
7. The dual NMOS transistor according to claim 6, characterized in that: The area of the first die is greater than the area of the second die.
8. The dual NMOS transistor according to claim 6, characterized in that: The area of the first die is smaller than the area of the second die.
9. The dual NMOS transistor according to any one of claims 1 to 8, characterized in that: It is a DFN package.
10. The dual NMOS transistor according to claim 9, characterized in that: Its length dimension is 4.2 mm and its width dimension is 2.2 mm.