Semiconductor device

Abstract

Various embodiments of the utility model relate to a semiconductor device. The semiconductor device comprises a sensing electrode, a first dielectric layer, a second dielectric layer, an actuating diaphragm and a third dielectric layer. The sensing electrode is located above the substrate and between the plurality of isolation trenches. A plurality of portions of the first dielectric layer are on the sensing electrode. A portion of the second dielectric layer is on the sensing electrode and on the portions of the first dielectric layer. The actuating diaphragm is over the second dielectric layer, wherein the actuating diaphragm is spaced apart from the second dielectric layer by a cavity. The third dielectric layer is located on the actuating diaphragm, the third dielectric layer is located between the actuating diaphragm and the cavity, and the thickness of a part of the second dielectric layer is larger than that of the third dielectric layer.

Description

Technical Field

[0001] An embodiment of the utility model relates to a semiconductor device. Background Art

[0002] Integrated circuits can be fabricated on semiconductor wafers. Semiconductor wafers can be stacked or bonded on top of each other to form so-called three-dimensional integrated circuits. Some semiconductor wafers include micro-electromechanical-system (MEMS) devices, which involve processes for forming microstructures with dimensions on the micrometer scale (millionths of a meter). Typically, MEMS devices are constructed on silicon wafers and implemented as thin films of material. MEMS applications include inertial sensor applications (e.g., motion sensors, accelerometers, gyroscopes), pressure sensors, microfluidic devices (e.g., valves, pumps), movable mirrors, and imaging devices (e.g., micromachined ultrasonic transducers), among others. Utility Model Content

[0003] One aspect of the present invention provides a semiconductor device. The semiconductor device includes a sensing electrode located above a substrate and between a plurality of isolation trenches. The semiconductor device also includes multiple portions of a first dielectric layer located above the sensing electrode. The semiconductor device also includes a portion of a second dielectric layer located above the sensing electrode and the multiple portions of the first dielectric layer. The semiconductor device also includes an actuating diaphragm located above the second dielectric layer, wherein the actuating diaphragm is separated from the second dielectric layer by a cavity. The semiconductor device also includes a third dielectric layer located above the actuating diaphragm, wherein the third dielectric layer is located between the actuating diaphragm and the cavity, and wherein a portion of the second dielectric layer has a thickness greater than a thickness of the third dielectric layer.

[0004] Another aspect of the present invention provides a semiconductor device. The semiconductor device includes a sensing electrode located above a substrate and between a plurality of isolation trenches. The semiconductor device also includes multiple portions of a first dielectric layer located above the sensing electrode. The semiconductor device also includes a portion of a second dielectric layer located above the sensing electrode and multiple portions of the first dielectric layer. The semiconductor device also includes a portion of a third dielectric layer located above a portion of the second dielectric layer. The semiconductor device also includes an actuating diaphragm located above the third dielectric layer, wherein the actuating diaphragm and the third dielectric layer are separated by a cavity.

[0005] Another aspect of the present invention provides a method for forming a semiconductor device. The method includes forming a layer stack comprising alternating metal layers and metal nitride layers on the semiconductor device. The method also includes removing a portion of the layer stack to form a sensing electrode from the layer stack. The method also includes forming a first dielectric layer on the sensing electrode. The method also includes forming a second dielectric layer on the first dielectric layer. The method also includes forming a third dielectric layer on the second dielectric layer. The method also includes removing a first portion of the third dielectric layer such that a second portion of the third dielectric layer remains above the sensing electrode. The method also includes depositing additional material of the third dielectric layer to form a contact base structure above the sensing electrode. The method also includes bonding an actuator diaphragm to the semiconductor device.

[0006] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram of an exemplary environment in which the systems and / or methods described herein may be implemented.

[0008] Figure 2 is a diagram of an exemplary semiconductor device described herein.

[0009] Figure 3A and Figure 3B is a diagram of an exemplary embodiment of an operating mode of a capacitive micromachined ultrasonic transducer (CMUT) of a semiconductor device described herein.

[0010] Figures 4A to 4V are diagrams of exemplary embodiments for forming the semiconductor devices (or portions thereof) described herein.

[0011] Figure 5 is a diagram of an exemplary semiconductor device described herein.

[0012] Figures 6A to 6E are diagrams of exemplary embodiments for forming the semiconductor devices (or portions thereof) described herein.

[0013] Figure 7 is a diagram of an exemplary semiconductor device described herein.

[0014] Figures 8A to 8H are diagrams of exemplary embodiments for forming the semiconductor devices (or portions thereof) described herein.

[0015] Figure 9 is a diagram of exemplary components of the apparatus described herein.

[0016] Figure 10is a flow chart of an exemplary process associated with forming the semiconductor devices described herein.

[0017] Figure 11 is a flow chart of an exemplary process associated with forming the semiconductor devices described herein.

[0018] Figure 12 is a flow chart of an exemplary process associated with forming the semiconductor devices described herein. DETAILED DESCRIPTION

[0019] The present invention provides many different embodiments or examples for implementing the different features of the provided target. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," and "upper," may be used herein to describe the relationship of one component or feature to another component or feature illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0021] Micromachined ultrasonic transducers (MUTs), such as piezoelectric MUTs (PMUTs) and capacitive MUTs (CMUTs), can be included in microelectromechanical systems (MEMS) devices, such as fingerprint sensors, high-intensity focused ultrasound sensors, medical ultrasound imaging sensors, and / or other contact sensors. For example, a CMUT can include an actuation membrane, a sensing dielectric layer below the actuation membrane, and an air gap separating the actuation membrane from the sensing dielectric layer to enable displacement of the membrane. A voltage can be applied to the actuation membrane to displace the actuation membrane, which causes the CMUT to transmit an ultrasonic signal (e.g., when the CMUT is configured as an ultrasonic transmitter). Additionally and / or alternatively, the CMUT can be configured as an ultrasonic receiver, such that the ultrasonic signal can be received by the actuation membrane, causing the actuation membrane to displace. Actuating the displacement of the diaphragm may cause the CMUT to generate a signal (eg, a voltage signal, a current signal) based on the received ultrasonic signal, thereby enabling the CMUT to sense ultrasonic reflections (eg, from a fingerprint).

[0022] In some cases, a CMUT can be configured to operate in a specific operating mode, such as a free-standing mode or a collapsed mode. In the free-standing mode, the actuation diaphragm of the CMUT uses a voltage less than the collapse voltage (V collapse ) of the direct current (DC) voltage bias (V dc-bias ) to operate. This allows the actuated diaphragm to vibrate freely, resulting in fewer reliability issues than in collapsed mode. However, the sound pressure achievable by the CMUT in free-standing mode is less than that achievable by the CMUT in collapsed mode. In collapsed mode, the actuated diaphragm of the CMUT uses a V that is greater than the actuated diaphragm. collapse V dc-biasThe collapsed mode operates by stretching the actuation diaphragm against the contact pedestal of the underlying sensing dielectric layer. While the collapsed mode provides a greater sound pressure output for the CMUT and allows the frequency response of the actuation diaphragm to be adjustable, the stretching of the actuation diaphragm against the pedestal can cause damage and wear to the dielectric coating on the underside of the actuation diaphragm. This can, among other issues, lead to premature failure of the CMUT and / or reduce the operational life of the CMUT.

[0023] In some embodiments described herein, a MEMS device may include a CMUT comprising an actuating diaphragm and a sensing dielectric layer separated by a cavity (e.g., an air gap). The sensing dielectric layer may be formed to have a sufficiently high V such that the CMUT can accommodate collapse mode operation. dc-bias At the same time, the thickness of the sensing dielectric layer can extend the operating life of the CMUT. For example, the thickness of the sensing dielectric layer can be greater than the thickness of the dielectric coating on the underside of the actuating diaphragm. In this way, the thickness of the sensing dielectric layer enables the CMUT to operate in a collapse mode, which enables the CMUT to achieve a greater sound pressure output relative to other operating modes and enables the frequency response of the CMUT to be adjustable, thereby enabling the frequency response to be optimized for specific use cases and applications. In addition, the thickness of the sensing dielectric layer can enable the CMUT to operate at a sustained high collapse voltage for a longer period of time (e.g., relative to a CMUT including a thinner sensing dielectric layer), which reduces the likelihood of premature wear and extends the operating life of the CMUT.

[0024] Figure 1 1 is a diagram of an exemplary environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown in FIG, an exemplary environment 100 may include a plurality of semiconductor processing tools 102-114 and a wafer / die transport tool 116. The plurality of semiconductor processing tools 102-114 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, a bonding tool 114, and / or another type of semiconductor processing tool. The tools included in the exemplary environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing facility, and / or a fabrication facility, among others.

[0025] Deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, deposition tool 102 comprises a spin coater tool capable of depositing a photoresist layer onto a substrate (e.g., a wafer). In some embodiments, deposition tool 102 comprises a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, a low-pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, deposition tool 102 comprises a physical vapor deposition (PVD) tool (e.g., a sputtering tool or another type of PVD tool). In some embodiments, deposition tool 102 comprises an epitaxial tool configured to form layers and / or regions of a device by epitaxial growth. In some embodiments, exemplary environment 100 comprises multiple deposition tools 102 and / or multiple types of deposition tools 102.

[0026] Exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source, such as an ultraviolet (UV) light source (e.g., a deep UV light source, an extreme UV (EUV) light source, and / or the like), an x-ray source, an electron beam (e-beam) source, and / or the like. Exposure tool 104 may expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns used to form one or more semiconductor devices, patterns used to form one or more structures of a semiconductor device, patterns used to etch various portions of a semiconductor device, and / or the like. In some embodiments, exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool. In some embodiments, exemplary environment 100 includes multiple exposure tools 104 and / or multiple types of exposure tools 104.

[0027] The development tool 106 is a semiconductor processing tool capable of developing the photoresist layer that has been exposed to the radiation source to develop the pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the development tool 106 develops the pattern by removing unexposed portions of the photoresist layer. In some embodiments, the development tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some embodiments, the development tool 106 develops the pattern by dissolving the exposed or unexposed portions of the photoresist layer using a chemical developer. In some embodiments, the exemplary environment 100 includes multiple development tools 106 and / or multiple types of development tools 106.

[0028] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials on a substrate, wafer, or semiconductor device. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, and / or the like. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and a substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may involve isotropic or directional etching of the one or more portions using an ionized gas. In some embodiments, the exemplary environment 100 includes multiple etching tools 108 and / or multiple types of etching tools 108.

[0029] Planarization tool 110 is a semiconductor processing tool capable of grinding or planarizing various layers of a wafer or semiconductor device. For example, planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool for grinding or planarizing layers or surfaces of deposited or plated materials. Planarization tool 110 may utilize a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing) to grind or planarize the surface of a semiconductor device. Planarization tool 110 may utilize abrasive and corrosive chemical slurries in conjunction with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor device). The polishing pad and semiconductor device may be pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head may rotate along different axes of rotation to remove material and smooth out any irregularities in the semiconductor device's topography, thereby flattening or planarizing the semiconductor device. In some embodiments, the exemplary environment 100 includes multiple planarization tools 110 and / or multiple types of planarization tools 110 .

[0030] The plating tool 112 is a semiconductor processing tool capable of plating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion thereof with one or more metals. For example, the plating tool 112 may include a copper plating device, an aluminum plating device, a nickel plating device, a tin plating device, a compound material or alloy plating device (e.g., tin-silver, tin-lead, and / or the like), and / or a plating device for one or more other types of conductive materials, metals, and / or similar types of materials. In some embodiments, the exemplary environment 100 includes multiple plating tools 112 and / or multiple types of plating tools 112.

[0031] The wafer / die transporter 116 includes a mobile robot, a robotic arm, a tram or rail car, an overhead hoist transport (OHT) system, an automated material handling system (AMHS), and / or another type of device configured to transport substrates and / or semiconductor devices between semiconductor processing tools 102-112, to transport substrates and / or semiconductor devices between processing chambers of the same semiconductor processing tool, and / or to transport substrates and / or semiconductor devices to and from other locations (e.g., wafer racks, storage chambers, and / or the like). In some embodiments, the wafer / die transporter 116 can be a programmed device configured to travel a specific path and / or can operate semi-automatically or automatically. In some embodiments, the exemplary environment 100 includes multiple wafer / die transporters 116 and / or multiple types of wafer / die transporters 116.

[0032] For example, the wafer / die transport tool 116 may be included in a cluster tool or another type of tool that includes multiple processing chambers, and may be configured to transport substrates and / or semiconductor devices between the multiple processing chambers, transport substrates and / or semiconductor devices between a processing chamber and a buffer area, transport substrates and / or semiconductor devices between a processing chamber and an interface tool (e.g., an equipment front end module (EFEM)), and / or transport substrates and / or semiconductor devices between a processing chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), etc. In some embodiments, the wafer / die transporter 116 may be included in a multi-chamber (or cluster) deposition tool 102 that may include a pre-cleaning process chamber (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from substrates and / or semiconductor devices) and multiple types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations). In these embodiments, the wafer / die transporter 116 is configured to transport substrates and / or semiconductor devices between process chambers of the deposition tool 102 without breaking or removing vacuum (or at least partial vacuum) between process chambers and / or between process operations in the deposition tool 102, as described herein.

[0033] In some embodiments, one or more of the semiconductor processing tools 102-114 can perform one or more semiconductor processing operations described herein. For example, one or more of the semiconductor processing tools 102-114 can perform the operations described herein, for example, in conjunction with Figures 4A to 4V 、 Figures 6A to 6E 、 Figures 8A to 8H and / or Figures 10 to 12 etc. and other semiconductor processing operations described herein.

[0034] Figure 1 The number and arrangement of the devices shown in are provided as one or more examples. Figure 1 In the apparatus shown in , there may be additional apparatuses, fewer apparatuses, different apparatuses, or apparatuses arranged differently. Figure 1 Two or more of the devices shown in the figure may be implemented in a single device, or Figure 1 A single device shown in the example environment 100 may be implemented as multiple distributed devices. Additionally or alternatively, one or more devices of the example environment 100 may implement one or more functions described as being implemented by another device of the example environment 100.

[0035] Figure 2 is a diagram of an exemplary semiconductor device 200 described herein. Semiconductor device 200 may be a MEMS device, such as an ultrasonic fingerprint sensor, etc. Additionally and / or alternatively, semiconductor device 200 may include another type of MEMS device, such as a radio frequency (RF) switch, a motion sensor, and / or another type of MEMS device with mechanical contacts and high operating voltage.

[0036] like Figure 2 As shown in FIG, semiconductor device 200 may include substrate 202. Substrate 202 may include a silicon (Si) substrate, a substrate formed from a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, or another type of semiconductor substrate. Alternatively, substrate 202 may include a dielectric substrate included on a semiconductor wafer (e.g., a silicon wafer). After or as part of fabricating semiconductor device 200, semiconductor device 200 may be sliced or cut from the semiconductor wafer. The semiconductor wafer may be a round / circular wafer having a diameter of approximately 200 mm, a diameter of approximately 300 mm, or another diameter (e.g., 450 mm). Substrate 202 may be any square workpiece, rectangular workpiece, curved workpiece, or otherwise non-circular workpiece, such as a polygonal substrate.

[0037] The semiconductor device 200 may include one or more conductive structures 204 disposed in a substrate 202. The conductive structure 204 may include a conductive metallization layer that is electrically connected to one or more semiconductor devices (not shown) included in the substrate 202, such as one or more active semiconductor devices (e.g., transistors), one or more passive semiconductor devices (e.g., capacitors, resistors, inductors), and / or one or more semiconductor devices of another type.

[0038] like Figure 2 As further shown in FIG. 1 , the semiconductor device 200 may include an interconnect region 206 located above and / or on the substrate 202. The interconnect region 206 may include one or more dielectric layers and one or more conductive structures located in the one or more dielectric layers. The one or more dielectric layers may include oxide-containing materials, nitride-containing materials, silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), silicon carbonitride (SiCN), silicon oxycarbide (SiOC) and / or another dielectric material, etc.

[0039] The one or more conductive structures may include one or more interconnect structures 208, one or more metallization layers 210, and / or one or more interconnect structures 212, among others. The one or more conductive structures may include one or more conductive materials such as platinum (Pt), titanium (Ti), ruthenium (Ru), cobalt (Co), tungsten (W), copper (Cu), molybdenum (Mo), a conductive metal material, a conductive ceramic material, a metal alloy material, another conductive material, or a combination thereof. The one or more interconnect structures 208 and the one or more interconnect structures 212 may each include a via, a conductive pillar, a through silicon via (TSV), a through insulator via (TIV), a trench, and / or another type of interconnect structure. The one or more metallization layers 210 may each include a conductive trace, a trench, and / or another type of metallization layer.

[0040] The one or more interconnect structures 208 may be included above and / or on the one or more conductive structures 204. The one or more interconnect structures 208 may be electrically and / or physically coupled to the one or more conductive structures 204. The one or more metallization layers 210 may be included above and / or on the one or more interconnect structures 208. The one or more metallization layers 210 may be electrically and / or physically coupled to the one or more interconnect structures 208. The one or more interconnect structures 212 may be included above and / or on the one or more metallization layers 210. The one or more interconnect structures 212 may be electrically and / or physically coupled to the one or more metallization layers 210.

[0041] The one or more metallization layers 210 may extend through one or more dielectric layers located above the interconnect region 206. The one or more dielectric layers may include a dielectric layer 214 located above and / or on the interconnect region 206, a dielectric layer 216 located above and / or on the dielectric layer 214, and / or another dielectric layer, etc. The dielectric layers 214 and 216 may each include an oxide-containing material, a nitride-containing material, silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), and / or another dielectric material, among others. In some embodiments, dielectric layer 214 and dielectric layer 216 comprise different dielectric materials. For example, dielectric layer 214 may comprise a nitride-containing dielectric material, and dielectric layer 216 may comprise an oxide-containing dielectric material. In some embodiments, dielectric layer 214 and dielectric layer 216 comprise the same dielectric material or the same combination of dielectric materials.

[0042] like Figure 2As further shown in FIG. 2 , semiconductor device 200 may include a sensing electrode 218. The sensing electrode 218 may be included in a CMUT included in semiconductor device 200. For example, the sensing electrode 218 may correspond to a bottom electrode of the CMUT included in semiconductor device 200. The sensing electrode 218 may be formed from multiple layers included in semiconductor device 200. For example, the sensing electrode 218 may include a plurality of alternating conductive material layers, including alternating metal layers 220 and metal nitride layers 222. The metal layers 220 may include platinum (Pt), titanium (Ti), ruthenium (Ru), cobalt (Co), tungsten (W), copper (Cu), molybdenum (Mo), tantalum (Ta), aluminum copper (AlCu), and / or another metal material, among others. The metal nitride layers 222 may include titanium nitride (TiN), tantalum nitride (TaN), and / or another conductive metal nitride material.

[0043] In some embodiments, the thickness of the metal layer 220 is greater than the thickness of the metal nitride layer 222. For example, the thickness of the metal layer 220 may be approximately 2 to approximately 4 times the thickness of the metal nitride layer 222. However, other values within this range are also within the scope of the present disclosure. In some embodiments, the thickness of the metal layer 220 is within the range of approximately 750 angstroms to approximately 1250 angstroms. However, other values within this range are also within the scope of the present disclosure. In some embodiments, the thickness of the metal nitride layer 222 is within the range of approximately 200 angstroms to approximately 300 angstroms. However, other values within this range are also within the scope of the present disclosure.

[0044] The sensing electrodes 218 can be electrically isolated from other regions of the semiconductor device 200 by a plurality of isolation trenches 224. Thus, the sensing electrodes 218 can be included between the plurality of isolation trenches 224. The isolation trenches 224 can provide protection against current leakage between adjacent sensing electrodes 218. The isolation trenches 224 can include a portion of a sensing dielectric layer 226, a portion of a nitride layer 228 (e.g., a dielectric layer), and a portion of a high-density plasma (HDP) oxide layer 230 (e.g., a dielectric layer), among others. The sensing dielectric layer 226 can extend continuously through the plurality of isolation trenches 224 and over the tops of the sensing electrodes 218 included between the plurality of isolation trenches. Alternatively, the sensing dielectric layer 226 can be segmented, thereby including discontinuities in the sensing dielectric layer 226 between the isolation trenches 224.

[0045] The sensing dielectric layer 226 may be included on and / or above the sensing electrodes 218 to enable the CMUT of the semiconductor device 200 to operate in contact mode. In addition, the sensing dielectric layer 226 may be included on and / or above the sensing electrodes 218 to provide a dielectric layer capable of achieving the capacitive properties of the CMUT. The sensing dielectric layer 226 may include plasma enhanced oxide (PEOx), plasma enhanced nitride, aluminum oxide (AlOx), or a combination thereof. x O y ) and / or another dielectric material. In some embodiments, PECVD techniques (e.g., for PEOx, plasma-enhanced nitrides (e.g., plasma-enhanced silicon nitride (Si x N y )) and / or plasma enhanced silicon oxynitride (SiON)) to deposit the sensing dielectric layer 226. In some embodiments, an ALD technique (e.g., for aluminum oxide (Al x O y ))Deposit the sensing dielectric layer 226.

[0046] Above the sensing electrode 218, a portion of the dielectric layer 232 may be included between the sensing electrode 218 and the sensing dielectric layer 226. The dielectric layer 232 may include plasma enhanced oxide (PEOx), plasma enhanced nitride, aluminum oxide (Al x O y ) and / or another dielectric material. In some embodiments, PECVD techniques (e.g., for PEOx, plasma-enhanced nitrides (e.g., plasma-enhanced silicon nitride (Si x N y )) and / or plasma enhanced silicon oxynitride (SiON)) to deposit the dielectric layer 232. In some embodiments, an ALD technique (e.g., for aluminum oxide (Al x O y )) A dielectric layer 232 is deposited. The portion of dielectric layer 232 described above can be included to include a plurality of contact base structures 234 above sense electrodes 218 and between isolation trenches 224. Contact base structures 234 can include portions 234a of sense dielectric layer 226 located above portions 234b of dielectric layer 232.

[0047] like Figure 2As shown in FIG, a top surface 236 of the sensing dielectric layer 226 between adjacent contact base structures 234 and a top surface 238 of the sensing dielectric layer 226 on the contact base structures 234 may be at different heights in the semiconductor device 200. A dimension D1 of the semiconductor device 200 may correspond to the height difference between the top surface 236 and the top surface 238. In some embodiments, dimension D1 may be within a range of approximately 50 angstroms to approximately 500 angstroms to prevent or reduce the likelihood of stiction between the actuation diaphragm 240 and the sensing dielectric layer 226 while allowing the actuation diaphragm 240 to undergo sufficient deformation (e.g., a sufficient amount of stroke). If dimension D1 is less than approximately 50 angstroms, the actuation diaphragm 240 may contact the top surface 236 of the sensing dielectric layer 226 between the contact base structures 234 during operation of the CMUT, which may cause wear of the sensing dielectric layer 226 between the contact base structures 234. This may degrade the collapse voltage of the CMUT, which may cause the CMUT to no longer function. However, dimension D1 may be within another range, and ranges other than approximately 50 angstroms to approximately 500 angstroms are also within the scope of the present disclosure.

[0048] In some embodiments, dimension D2, which corresponds to the width of the contact base structure 234, can be based on the thickness of the sensing dielectric layer 226. For example, dimension D2 can be selected such that the thickness of the sensing dielectric layer 226 is approximately less than or equal to 10% of dimension D2 (e.g., if the contact base structure width is approximately 0.2 microns, the thickness of the sensing dielectric layer 226 is 2,000 angstroms). As another example, dimension D2 can be selected such that the thickness of the sensing dielectric layer 226 is within a range of approximately 5% to approximately 10% of the width of the contact base structure 234 (e.g., if the contact base structure width is approximately 0.4 microns to approximately 0.8 microns, the thickness of the sensing dielectric layer 226 is 4,000 angstroms).

[0049] The semiconductor device 200 may include an actuating diaphragm 240 of a CMUT. The actuating diaphragm 240 may be an actuator of the CMUT that selectively vibrates to generate an ultrasonic signal or vibrates upon receiving an ultrasonic signal. The actuating diaphragm 240 may include one or more layers of silicon (Si), may include portions of a silicon wafer, and / or may include another type of structure. In some embodiments, the actuating diaphragm 240 is formed from a bulk silicon wafer and bonded to the semiconductor device 200. In some embodiments, a dielectric coating 242 is formed on the actuating diaphragm 240 as part of a silicon-on-insulator (SOI) wafer fabrication process. The dielectric coating 242 may include thermal oxide (THOx) and / or another type of dielectric material. The dielectric coating 242 may be included on the underside of the actuating diaphragm 240 to achieve a sufficiently high collapse voltage, along with the sensing dielectric layer 226, to enable the CMUT to operate at high voltages.

[0050] The actuation diaphragm 240 can be separated from the contact base structure 234 and the sensing dielectric layer 226 by a cavity 244. The cavity 244 can include an air gap or space that is pumped to a vacuum to enable displacement and vibration of the actuation diaphragm 240. In some embodiments, the actuation diaphragm 240 can operate in a collapsed mode in which the actuation diaphragm 240 is stretched against the sensing dielectric layer 226. The contact base structure 234 can be included to prevent or reduce the possibility of stiction between the actuation diaphragm 240 and the sensing dielectric layer 226.

[0051] The cavity 244 can be formed by bonding the actuator diaphragm 240 to the HDP oxide layer 230 and the pressure port 246. The HDP oxide layer 230 and the pressure port 246 can serve as a standoff for the actuator diaphragm 240, thereby enabling the cavity 244 to be formed between the actuator diaphragm 240 and the contact base structure 234 and the sensing dielectric layer 226. After or during bonding of the actuator diaphragm 240 to the semiconductor device 200, the pressure port 246 can be used to control, adjust, generate, and / or otherwise influence the pressure within the cavity 244.

[0052] Various dielectric layers may be included above the actuation membrane 240, such as a dielectric layer 248, a capping layer 250, and / or a passivation layer 252. The dielectric layer 248, the capping layer 250, and the passivation layer 252 may each include an oxide-containing material, a nitride-containing material, silicon oxide (SiO x ), silicon nitride (Si x N y), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), and / or another dielectric material, etc. Two or more of the dielectric layer 248, the cap layer 250, and the passivation layer 252 may include different dielectric materials. Two or more of the dielectric layer 248, the cap layer 250, and the passivation layer 252 may include the same dielectric material.

[0053] A conductive contact 254 may be included on the actuation diaphragm 240 and may be electrically coupled to the actuation diaphragm 240. The conductive contact 254 may include platinum (Pt), titanium (Ti), ruthenium (Ru), cobalt (Co), tungsten (W), copper (Cu), molybdenum (Mo), tantalum (Ta), aluminum copper (AlCu), and / or another metal material, etc. The conductive contact 254 may enable various voltages to be applied to the actuation diaphragm 240.

[0054] In this manner, semiconductor device 200 may include sensor electrode 218 located above substrate 202 and between a plurality of isolation trenches 224. Semiconductor device 200 may include a plurality of portions 234b of a first dielectric layer (e.g., dielectric layer 232) located above sensor electrode 218. Semiconductor device 200 may include a portion 234a of a second dielectric layer (e.g., sensor dielectric layer 226) located above sensor electrode 218 and above the plurality of portions 234b of the first dielectric layer. Semiconductor device 200 may include an actuation diaphragm 240 located above the second dielectric layer, wherein actuation diaphragm 240 is separated from the second dielectric layer by a cavity 244. Semiconductor device 200 may include a third dielectric layer (e.g., dielectric coating 242) located above actuation diaphragm 240. The third dielectric layer is located between actuation diaphragm 240 and cavity 244. Portion 234a of the second dielectric layer has a thickness greater than a thickness of the third dielectric layer.

[0055] As shown above, Figure 2 are provided as examples. Other examples may differ from those described in Figure 2 The examples described.

[0056] Figure 3A and Figure 3B is a diagram of an exemplary embodiment of an operating mode of a CMUT of the semiconductor device 200 described herein. Figure 3A An exemplary embodiment 300 of a CMUT of the semiconductor device 200 configured to operate in an ultrasonic transmission mode is shown. Figure 3B An exemplary embodiment 302 of a CMUT of the semiconductor device 200 configured to operate in an ultrasonic reception mode is shown.

[0057] exist Figure 3A In the ultrasonic transmission mode shown in FIG, for example, an alternating current (AC) voltage (V ac ) can be applied to the actuated diaphragm 240 (e.g., via the conductive contacts 254) and the sensing electrodes 218 (e.g., via the conductive structures 204, 208, 210, and / or 212) to displace the actuated diaphragm 240, which causes the CMUT to transmit the ultrasonic signal 304. The displacement of the actuated diaphragm 240 causes the actuated diaphragm 240 to vibrate, thereby causing the CMUT to transmit the ultrasonic signal 304.

[0058] In the ultrasonic receiving mode, the actuating diaphragm 240 may receive the ultrasonic signal 306. The ultrasonic signal 306 may be a reflected version of the ultrasonic signal 304. For example, the ultrasonic signal 306 may be a reflected version of the ultrasonic signal 304 reflected from a finger placed on the CMUT. The ultrasonic signal 306 may cause the actuating diaphragm 240 to displace. The displacement of the actuating diaphragm 240 causes the electric field between the ultrasonic signal 306 and the sensing electrode 218 to vary over time. The actuating diaphragm 240, the sensing electrode 218 and the cavity 244, as well as the dielectric layer (e.g., the sensing dielectric layer 226, the dielectric coating 242) located between the actuating diaphragm 240 and the sensing electrode 218 operate as a capacitor. The capacitive property is used to convert the time-varying electric field generated based on the ultrasonic signal 306 into a time-varying electric signal (e.g., AC voltage (V ac )), the time-varying electrical signal can be used to generate a fingerprint scan of a finger placed on top of the CMUT.

[0059] In the ultrasonic transmission mode and in the ultrasonic reception mode, the CMUT can be configured to operate in a specific operation mode such as a self-supporting mode or a collapsed mode. In the self-supporting mode, the actuating diaphragm of the CMUT uses a voltage less than the collapse voltage (V collapse ) of the DC voltage bias (V dc-bias ) to operate. This allows the actuated diaphragm 240 to vibrate freely, which results in fewer reliability issues relative to the collapsed mode. However, the sound pressure that can be achieved by the CMUT in the free-standing mode is less than that in the collapsed mode. In the collapsed mode (which is shown in Figure 3A and Figure 3B In the middle), the actuating diaphragm 240 of the CMUT uses a V larger than the actuating diaphragm 240. collapse V dc-biasThe collapsed mode can be operated so that the actuated diaphragm 240 is stretched against the contact base structure 234 of the underlying sensing dielectric layer 226. The collapsed mode can provide a larger acoustic pressure output and / or a larger sensing sensitivity for the CMUT and can enable the frequency response of the actuated diaphragm 240 to be adjustable.

[0060] The CMUT of the semiconductor device 200 may be configured to actuate the diaphragm 240 with respect to V dc-bias Operating at a relatively high voltage (e.g., to achieve collapse of the actuation diaphragm 240), and / or for a drive signal (e.g., V ac ) operates at a relatively high voltage. For example, the V dc-bias and / or V ac The voltage may be within a range of approximately 100 volts to approximately 135 volts or greater than 135 volts. During operation of the CMUT in the collapsed mode, the high voltage may cause the actuation diaphragm 240 to rub against the base structure 234, which may cause the dielectric coating 242 on the underside of the actuation diaphragm 240 to wear in the area where the actuation diaphragm 240 contacts the base structure 234.

[0061] If the dielectric coating 242 wears away, the collapse voltage of the CMUT may decrease to such an extent that the CMUT may no longer operate because the high voltage may exceed the reduced collapse voltage of the CMUT. Simply increasing the thickness of the dielectric coating 242 to reduce the wear of the dielectric coating 242 may increase the stiffness of the actuation diaphragm 240, thereby rendering the actuation diaphragm 240 inoperable at ultrasonic frequencies.

[0062] The sensing dielectric layer 226 can be formed such that the thickness of the sensing dielectric layer 226 can extend the operating life of the CMUT while enabling the CMUT to accommodate sufficiently high voltages for collapse mode operation and enabling the actuation diaphragm 240 to still operate at ultrasonic frequencies. For example, the thickness of the sensing dielectric layer 226 can be greater than the thickness of the dielectric coating 242 on the underside of the actuation diaphragm 240. Although the dielectric strength of the dielectric coating 242 can be greater than the dielectric strength of the sensing dielectric layer 226, the greater thickness of the sensing dielectric layer 226 can enable the sensing dielectric layer 226 to provide sufficient dielectric permittivity to enable the CMUT to maintain a sustained high collapse voltage, thereby allowing the CMUT to still operate at a sufficiently high voltage even if the dielectric coating 242 does wear out. In this manner, the thickness of the sensing dielectric layer 226 enables the CMUT to operate in a collapsed mode, which enables the CMUT to achieve a greater sound pressure output relative to other operating modes and enables the CMUT's frequency response to be adjustable, thereby enabling the frequency response to be optimized for specific use cases and applications. Furthermore, the thickness of the sensing dielectric layer 226 can enable the CMUT to operate at a sustained high collapse voltage for a longer period of time (e.g., relative to a CMUT including a thinner sensing dielectric layer), which reduces the likelihood of premature wear and extends the CMUT's operational lifespan.

[0063] The thickness of the dielectric coating 242 can range from greater than 0 angstroms to approximately 3,000 angstroms. In some embodiments, if the sensing dielectric layer 226 is thick enough to provide a sufficient collapse voltage, the dielectric coating 242 can be omitted from the actuation diaphragm 240. However, in some cases, omitting the dielectric coating 242 may result in residual charge remaining on the sensing dielectric layer 226 during operation of the CMUT, which may cause the DC bias voltage to drift during operation of the CMUT. If the thickness of the dielectric coating 242 is greater than approximately 3,000 angstroms, the stiffness of the actuation diaphragm 240 may increase to the point where the actuation diaphragm 240 may be unable to operate at ultrasonic frequencies. In addition, the capacitance between the actuation diaphragm 240 and the sensing electrode 218 may be too high, which may result in an increased / slower response time of the CMUT. If the thickness of the dielectric coating 242 is within a range of greater than 0 angstroms to approximately 3,000 angstroms, the actuated diaphragm 240 may be capable of operating at ultrasonic frequencies and may reduce the likelihood of DC bias voltage drift during operation of the CMUT. However, other values and / or ranges of thickness for the dielectric coating 242 are also within the scope of the present disclosure.

[0064] The thickness of the sensing dielectric layer 226 is greater than the thickness of the dielectric coating 242. For example, the thickness of the sensing dielectric layer 226 may be within a range of approximately 1,900 angstroms to approximately 4,000 angstroms. In some embodiments, the thickness of the sensing dielectric layer 226 is based on the maximum operating voltage (V max ), the maximum operating voltage (V max ) may correspond to the maximum AC voltage or the maximum DC bias voltage of the CMUT. For example, the thickness of the sensing dielectric layer 226 may correspond to approximately to approximate As an example, if V max is 220 volts, the thickness of the sensing dielectric layer 226 may be within the range of approximately 2,200 angstroms to approximately 4,400 angstroms. to approximate The thickness of the sensing dielectric layer 226 is selected to a value that enables a sufficient driving static force and sufficient capacitance to be achieved for the CMUT while maintaining a sufficiently high collapse voltage for the CMUT (e.g., even if the dielectric coating 242 wears away). to approximate Selecting a value for the thickness of the sensing dielectric layer 226 outside the range of may result in the collapse voltage of the CMUT being too low, the driving force being too low, and / or the capacitance being too low. to approximate Other values and / or ranges outside the range are also within the scope of the present disclosure.

[0065] The thickness of the actuating diaphragm 240 may be within a range of approximately 1 micron to approximately 30 microns. At a thickness less than approximately 1 micron, the actuating diaphragm 240 may not have sufficient mechanical strength, which may cause the actuating diaphragm 240 to rupture during operation of the CMUT. At a thickness greater than approximately 1 micron, the actuating diaphragm 240 may have sufficient mechanical strength to withstand operation of the CMUT. If the thickness of the actuating diaphragm 240 is greater than approximately 30 microns, the actuating diaphragm 240 may not have sufficient flexibility to operate at ultrasonic frequencies. At a thickness less than approximately 30 microns, the actuating diaphragm 240 may have sufficient flexibility to operate at ultrasonic frequencies. However, other values and / or ranges of thickness for the actuating diaphragm 240 (e.g., other than approximately 1 micron to approximately 30 microns) are also within the scope of the present disclosure.

[0066] The thickness of sensor electrode 218 may range from approximately 400 angstroms to approximately 30,000 angstroms. At a thickness less than approximately 400 angstroms, the resistance of sensor electrode 218 may be too high, which may result in an increased / slower response time of the CMUT. If the thickness of sensor electrode 218 is greater than approximately 400 angstroms, the low resistance of sensor electrode 218 may result in a decreased / faster response time of the CMUT. Furthermore, a thickness of sensor electrode 218 greater than approximately 30,000 angstroms may result in longer processing times (e.g., longer CMP times) for sensor electrode 218 and may result in highly nonuniform surfaces of sensor electrode 218, which may lead to processing defects in other layers and / or structures in semiconductor device 200. A thickness of approximately 30,000 angstroms or less may result in reduced processing times (e.g., reduced CMP times) for sensor electrode 218 and may improve surface uniformity of sensor electrode 218. However, other values and / or ranges of thickness for the sensor electrode 218 (eg, other than approximately 400 angstroms to approximately 30,000 angstroms) are within the scope of the present disclosure.

[0067] As shown above, Figure 3A and Figure 3B are provided as examples. Other examples can be found in the Figure 3A and Figure 3B The examples described are different.

[0068] Figures 4A to 4V is a diagram of an exemplary embodiment 400 for forming the semiconductor device 200 (or portion thereof) described herein. In some embodiments, a combination of Figure 1 One or more of the semiconductor processing tools 102 to 114 described herein may be used to implement the combined Figures 4A to 4V In some embodiments, one or more of the semiconductor processing operations described herein may be used. Figure 1 Another semiconductor processing tool not shown is used to perform the combination Figures 4A to 4V One or more of the semiconductor processing operations described.

[0069] Go to Figure 4A, a substrate 202 may be provided. The substrate 202 may be provided as a semiconductor wafer, a semiconductor die, and / or another type of semiconductor substrate. In some embodiments, the substrate 202 may be a doped substrate, such as a semiconductor substrate doped with one or more p-type dopants, a semiconductor substrate doped with one or more n-type dopants, and / or another type of doped substrate. In some embodiments, the substrate 202 has a bulk resistivity (or volume resistivity) within a range of approximately 1 ohm-centimeter to approximately 100 ohm-centimeter. However, other values within this range are also within the scope of the present disclosure.

[0070] like Figure 4B As shown in FIG, a conductive structure 204 may be formed in a substrate 202. The deposition tool 102 and / or the plating tool 112 may be used in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, or a combination thereof. Figure 1 The conductive structure 204 is deposited in another deposition operation as described and / or another suitable deposition operation. In some embodiments, a seed layer is deposited first, and the conductive structure 204 is deposited on the seed layer. In some embodiments, after the conductive structure 204 is deposited, the conductive structure 204 can be planarized using a planarization tool 110.

[0071] like Figure 4C As shown in FIG, a portion of interconnect region 206 is formed on and / or above substrate 202. Deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, a combination of Figure 1 The one or more dielectric layers of the interconnect region 206 are deposited in one or more deposition operations of another type as described and / or one or more deposition operations of another suitable type. In some embodiments, after depositing the one or more dielectric layers of the interconnect region 206, a planarization tool 110 can be used to planarize the one or more dielectric layers of the interconnect region 206.

[0072] like Figure 4DAs shown in FIG, an interconnect structure 208 is formed in the one or more dielectric layers of the interconnect region 206. The interconnect structure 208 can be formed in a recess in the one or more dielectric layers, thereby electrically and / or physically coupling the interconnect structure 208 to the conductive structure 204. The recess can be formed in and / or through the one or more dielectric layers of the interconnect region 206. Specifically, the recess can be formed above the conductive structure 204. The recess can be formed completely through the one or more dielectric layers of the interconnect region 206, thereby exposing the top surface of the conductive structure 204 through the recess.

[0073] In some embodiments, a recess is formed in the one or more dielectric layers in the interconnect region 206 using a pattern in the photoresist layer. In these embodiments, a photoresist layer is formed on the one or more dielectric layers in the interconnect region 206 using a deposition tool 102. The photoresist layer is exposed to a radiation source using an exposure tool 104 to pattern the photoresist layer. A development tool 106 is used to develop the photoresist layer and remove portions of the photoresist layer to expose the pattern. An etching tool 108 is used to etch the one or more dielectric layers in the interconnect region 206 based on the pattern to form the recess. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for forming the recess based on the pattern.

[0074] The deposition tool 102 and / or the plating tool 112 may be used in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, or a combination thereof. Figure 1 In another deposition operation as described and / or another suitable deposition operation, an interconnect structure 208 is deposited over and / or on the conductive structure 204. In some embodiments, a seed layer is deposited first, and the interconnect structure 208 is deposited on the seed layer. In some embodiments, after depositing the interconnect structure 208, the interconnect structure 208 can be planarized using a planarization tool 110.

[0075] like Figure 4E As shown in FIG, another portion of the interconnect region 206 is formed above and / or on the interconnect region 206. The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, a combination of Figure 1One or more additional dielectric layers in the interconnect region 206 are deposited in one or more deposition operations of another type and / or one or more deposition operations of another suitable type as described. In some embodiments, after depositing the one or more additional dielectric layers in the interconnect region 206, the one or more additional dielectric layers in the interconnect region 206 can be planarized using a planarization tool 110.

[0076] like Figure 4F As shown in FIG, a metallization layer 210 is formed in the one or more additional dielectric layers in the interconnect region 206. The metallization layer 210 can be formed in a recess in the one or more additional dielectric layers, such that the metallization layer 210 is electrically and / or physically coupled to one or more of the interconnect structures 208. The recess can be formed in and / or through the one or more additional dielectric layers in the interconnect region 206. Specifically, the recess can be formed above the one or more interconnect structures 208. The recess can be formed completely through the one or more additional dielectric layers in the interconnect region 206, such that the top surface of the one or more interconnect structures 208 is exposed through the recess.

[0077] In some embodiments, a recess is formed in the one or more additional dielectric layers in the interconnect region 206 using a pattern in the photoresist layer. In these embodiments, a photoresist layer is formed on the one or more additional dielectric layers in the interconnect region 206 using a deposition tool 102. The photoresist layer is exposed to a radiation source using an exposure tool 104 to pattern the photoresist layer. A development tool 106 is used to develop the photoresist layer and remove portions of the photoresist layer to expose the pattern. An etching tool 108 is used to etch the one or more additional dielectric layers in the interconnect region 206 based on the pattern to form the recess. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for forming the recess based on the pattern.

[0078] The deposition tool 102 and / or the plating tool 112 may be used in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, or a combination thereof. Figure 1In another deposition operation as described and / or another suitable deposition operation, a metallization layer 210 is deposited over and / or on the one or more interconnect structures 208. In some embodiments, a seed layer is deposited first, and the metallization layer 210 is deposited on the seed layer. In some embodiments, after depositing the metallization layer 210, the interconnect structures 208 can be planarized using a planarization tool 110.

[0079] like Figure 4G As shown in FIG, one or more dielectric layers (e.g., dielectric layer 214 and / or dielectric layer 216) may be formed over and / or on interconnect region 206. In some embodiments, dielectric layer 214 is formed over and / or on interconnect region 206, and dielectric layer 216 is formed over and / or on dielectric layer 214. Deposition tool 102 may be used to deposit dielectric layer 214 in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, or a combination thereof. Figure 1 The dielectric layer 214 and / or the dielectric layer 216 are deposited in one or more deposition operations of another type and / or one or more deposition operations of another suitable type as described. In some embodiments, after depositing the one or more additional dielectric layers of the interconnect region 206, the one or more additional dielectric layers of the interconnect region 206 can be planarized using the planarization tool 110.

[0080] like Figure 4H As shown in FIG, an interconnect structure 212 can be formed in dielectric layers 214, 216 and into interconnect region 206. The interconnect structure 212 can be formed in a recess in the dielectric layers 214, 216 and into interconnect region 206, thereby electrically and / or physically coupling the interconnect structure 212 to the metallization layer 210. The recess can be formed in and / or through the dielectric layers 214, 216 and into a portion of the interconnect region 206. Specifically, the recess can be formed above the metallization layer 210. The recess can be formed such that a top surface of the metallization layer 210 is exposed through the recess.

[0081] In some embodiments, a recess is formed in dielectric layers 214, 216 using a pattern in the photoresist layer, and the recess is formed into interconnect region 206. In these embodiments, a photoresist layer is formed on dielectric layer 216 using deposition tool 102. The photoresist layer is exposed to a radiation source using exposure tool 104 to pattern the photoresist layer. A development tool 106 is used to develop the photoresist layer and remove portions of the photoresist layer to expose the pattern. An etching tool 108 is used to etch dielectric layers 214, 216 based on the pattern and to etch into interconnect region 206 to form the recess. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for forming the recess based on the pattern.

[0082] The deposition tool 102 and / or the plating tool 112 may be used in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, or a combination thereof. Figure 1 In another deposition operation as described and / or another suitable deposition operation, an interconnect structure 212 is deposited over and / or on the metallization layer 210. In some embodiments, a seed layer is deposited first, and the interconnect structure 212 is deposited over the seed layer. In some embodiments, after depositing the interconnect structure 212, the interconnect structure 208 can be planarized using the planarization tool 110.

[0083] like Figure 4I As shown in FIG, a stack of alternating metal layers 220 and metal nitride layers 222 may be formed on and / or over the dielectric layer 216. The deposition tool 102 and / or the plating tool 112 may be used in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, or a combination thereof. Figure 1 The metal layer 220 is deposited in another deposition operation as described above and / or another suitable deposition operation. In some embodiments, a seed layer is deposited first, and the metal layer 220 is deposited on the seed layer. In some embodiments, after depositing the metal layer 220, the metal layer 220 may be planarized using the planarization tool 110. The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, a combination of Figure 1The metal nitride layer 222 is deposited in one or more deposition operations of another type described and / or one or more deposition operations of another suitable type. In some embodiments, after depositing the metal nitride layer 222, the metal nitride layer 222 can be planarized using the planarization tool 110. In some embodiments, after depositing the stack of alternating metal layers 220 and metal nitride layers 222, the stack of alternating metal layers 220 and metal nitride layers 222 is annealed to remove voids and other discontinuities in the stack of alternating metal layers 220 and metal nitride layers 222.

[0084] like Figure 4J As shown in FIG, a dielectric layer 232 may be formed on and / or on the stack of alternating metal layers 220 and metal nitride layers 222. The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, a combination of Figure 1 The dielectric layer 232 is deposited in one or more deposition operations of another type as described and / or one or more deposition operations of another suitable type. In some embodiments, after the dielectric layer 232 is deposited, the dielectric layer 232 can be planarized using a planarization tool 110.

[0085] like Figure 4K As shown in FIG, a recess 402 may be formed in the dielectric layer 232. The recess 402 may be formed over the metallization stack including the conductive structure 204, the one or more interconnect structures 208, the metallization layer 210, and / or the one or more interconnect structures 212.

[0086] In some embodiments, the recess 402 is formed in the dielectric layer 232 using a pattern in the photoresist layer. In these embodiments, a deposition tool 102 is used to form the photoresist layer on the dielectric layer 232. An exposure tool 104 is used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 is used to develop the photoresist layer and remove portions of the photoresist layer to expose the pattern. An etching tool 108 is used to etch the dielectric layer 232 based on the pattern to form the recess 402. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for forming the recess 402 based on the pattern.

[0087] like Figure 4LAs shown in FIG, isolation trenches 224 may be formed through dielectric layer 232 and through the alternating stack of metal layers 220 and metal nitride layers 222. Isolation trenches 224 may be formed on opposite sides of recess 402. The formation of isolation trenches 224 results in the formation of sensor electrodes 218 of the CMUT of semiconductor device 200. Isolation trenches 224 may be configured to electrically isolate sensor electrodes 218.

[0088] In some embodiments, isolation trenches 224 are formed using a pattern in a photoresist layer through dielectric layer 232 and through the alternating stack of metal layers 220 and metal nitride layers 222. In these embodiments, a photoresist layer is formed on dielectric layer 232 using a deposition tool 102. The photoresist layer is exposed to a radiation source using an exposure tool 104 to pattern the photoresist layer. A development tool 106 is used to develop the photoresist layer and remove portions of the photoresist layer to expose the pattern. An etching tool 108 is used to perform an etching operation based on the pattern through dielectric layer 232 and through the alternating stack of metal layers 220 and metal nitride layers 222 to form isolation trenches 224. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based formation of the isolation trenches 224 .

[0089] like Figure 4M As shown in FIG, a sensing dielectric layer 226 may be formed on the semiconductor device 200. The sensing dielectric layer 226 may be formed on the dielectric layer 232 and in the isolation trench 224. The sensing dielectric layer 226 may also be formed on the sensing electrode 218. A portion 234a of the sensing dielectric layer 226 over the sensing electrode 218 covers a portion 234b of the dielectric layer 232, thereby forming a contact base structure 234 over the sensing electrode 218. The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, or a combination thereof. Figure 1 The sensing dielectric layer 226 is deposited in one or more deposition operations of another type and / or one or more deposition operations of another suitable type as described. In some embodiments, the sensing dielectric layer 226 is deposited using a PECVD technique using the deposition tool 102. The sensing dielectric layer 226 can be conformally deposited such that the sensing dielectric layer 226 conforms to the contour of the portion 234 b of the dielectric layer 232, which can form the contact base structure 234.

[0090] like Figure 4NAs shown in FIG, a nitride layer 228 may be formed on the sensing dielectric layer 226. The nitride layer 228 may be formed on the sensing dielectric layer 226 in the isolation trench 224 and on the sensing dielectric layer 226 above the sensing electrode 218. The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, a combination of Figure 1 The nitride layer 228 is deposited in another type of one or more deposition operations and / or another suitable type of one or more deposition operations. The nitride layer 228 can be conformally deposited such that the nitride layer 228 conforms to the topography of the sensing dielectric layer 226.

[0091] like Figure 4O As shown in FIG, a HDP oxide layer 230 may be formed on and / or on the nitride layer 228. The HDP oxide layer 230 may be formed on the nitride layer 228 in the isolation trench 224 and on the nitride layer 228 above the sensing electrode 218. The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, or a combination thereof. Figure 1 The HDP oxide layer 230 is deposited in another type of one or more deposition operations and / or another suitable type of one or more deposition operations as described. In some embodiments, the HDP oxide layer 230 is deposited using a high density plasma deposition technique to blanket deposit the HDP oxide layer 230 .

[0092] like Figure 4P As shown in FIG, a portion of the HDP oxide layer 230 and a portion of the nitride layer 228 can be removed from the semiconductor device 200. In some embodiments, a planarization tool 110 can be used to perform a CMP operation or another type of planarization operation to remove the portion of the HDP oxide layer 230. In some embodiments, an etching tool 108 can be used to remove the portion of the HDP oxide layer 230 and a portion of the nitride layer 228, thereby exposing the sensing dielectric layer 226 (and associated contact base structure 234) above the sensing electrode 218. Other portions of the HDP oxide layer 230 and other portions of the nitride layer 228 can remain in the isolation trench 224.

[0093] like Figure 4Q As shown in FIG, a pressure port 246 may be formed on a portion of the sensing dielectric layer 226. The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, a combination of Figure 1The pressure port 246 may be deposited in another type of one or more deposition operations as described and / or another suitable type of one or more deposition operations. Alternatively, the pressure port 246 may be bonded to the sensing dielectric layer 226 using a bonding tool 114.

[0094] like Figure 4R As shown in FIG, an actuator diaphragm 240 can be bonded to a semiconductor device 200. Specifically, the actuator diaphragm 240 can be bonded to the HDP oxide layer 230 and to a pressure port 246 of the semiconductor device 200. The bonding tool 114 can perform a dielectric-to-dielectric bonding operation to bond a dielectric coating 242 on the actuator diaphragm 240 to the HDP oxide layer 230 and to the pressure port 246 of the semiconductor device 200. The actuator diaphragm 240 is bonded to the semiconductor device 200 such that a cavity 244 is formed between the actuator diaphragm 240 and the sensing dielectric layer 226. The dielectric coating 242 can be formed on the actuator diaphragm 240 before the dielectric-to-dielectric bonding operation. The deposition tool 102 can deposit the dielectric coating 242 using a thermal oxidation deposition technique (e.g., thermal oxidation).

[0095] like Figure 4S As shown in FIG, a pressure relief port 404 can be formed in the actuator diaphragm 240 above the pressure port 246. In some embodiments, the pressure relief port 404 is formed through the actuator diaphragm 240 using a pattern in a photoresist layer. In these embodiments, a photoresist layer is formed on the dielectric layer 248 on the actuator diaphragm 240 using a deposition tool 102. The photoresist layer is exposed to a radiation source using an exposure tool 104 to pattern the photoresist layer. The photoresist layer is developed using a development tool 106 and portions of the photoresist layer are removed to expose the pattern. An etching tool 108 is used to etch through the dielectric layer 248, through the actuator diaphragm 240, and through the dielectric coating 242 to the pressure port 246. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based formation of the stress relief ports 404 .

[0096] like Figure 4TAs shown in FIG, a conductive contact 254 is formed through the dielectric layer 248 and on the actuating diaphragm 240, thereby electrically and / or physically coupling the conductive contact 254 to the actuating diaphragm 240. The conductive contact 254 can be formed in a recess in the dielectric layer 248. In some embodiments, the recess in the dielectric layer 248 is formed using a pattern in the photoresist layer. In these embodiments, a photoresist layer is formed on the dielectric layer 248 using a deposition tool 102. The photoresist layer is exposed to a radiation source using an exposure tool 104 to pattern the photoresist layer. The photoresist layer is developed using a development tool 106 and portions of the photoresist layer are removed to expose the pattern. An etching tool 108 is used to etch the dielectric layer 248 based on the pattern to form the recess. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. In some embodiments, a photoresist removal tool removes the remainder of the photoresist layer (eg, using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based formation of the recesses.

[0097] The deposition tool 102 and / or the plating tool 112 may be used in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, or a combination thereof. Figure 1 In another deposition operation as described and / or another suitable deposition operation, conductive contact 254 is deposited over actuation diaphragm 240 and / or in a recess on actuation diaphragm 240. In some embodiments, a seed layer is deposited first, and conductive contact 254 is deposited over the seed layer.

[0098] like Figure 4U , portions of dielectric layer 248 are removed after forming conductive contacts 254. Dielectric layer 248 is etched using etching tool 108 to remove portions of dielectric layer 248. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique.

[0099] like Figure 4V As shown in FIG, a cap layer 250 and a passivation layer 252 may be formed over and / or on the semiconductor device 200. The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, or a combination thereof. Figure 1 The cap layer 250 and the passivation layer 252 are deposited in another type of one or more deposition operations as described and / or another suitable type of one or more deposition operations.

[0100] As shown above, Figures 4A to 4V are provided as examples. Other examples may differ from those described in Figures 4A to 4VThe examples described.

[0101] Figure 5 is a diagram of an exemplary semiconductor device 500 described herein. Semiconductor device 500 may be a MEMS device, such as an ultrasonic fingerprint sensor, etc. Additionally and / or alternatively, semiconductor device 500 may include another type of MEMS device, such as an RF switch, a motion sensor, and / or another type of MEMS device with mechanical contacts and a high operating voltage.

[0102] like Figure 5 As shown in FIG, semiconductor device 500 may include an arrangement of components 202 to 254 similar to semiconductor device 200. However, semiconductor device 500 includes an additional sensing dielectric layer 502 located between dielectric layer 232 and sensing dielectric layer 226. Sensing dielectric layer 502 may also be included in isolation trench 224 and between sensing dielectric layer 226 and sensing electrode 218. Thus, contact base structure 234 may include portion 234a of sensing dielectric layer 226, portion 234b of dielectric layer 232, and portion 234c of sensing dielectric layer 502.

[0103] The sensing dielectric layer 502 may include plasma enhanced oxide (PEOx), plasma enhanced nitride, aluminum oxide (Al x O y ) and / or another dielectric material. In some embodiments, PECVD techniques (e.g., for PEOx, plasma-enhanced nitrides (e.g., plasma-enhanced silicon nitride (Si x N y )) and / or plasma enhanced silicon oxynitride (SiON)) to deposit the sensing dielectric layer 502. In some embodiments, ALD techniques (e.g., for aluminum oxide (Al x O y ))Deposit a sensing dielectric layer 502.

[0104] The combination of the sensing dielectric layer 226 and the sensing dielectric layer 502 can provide sufficient thickness to protect against collapse voltage degradation in the CMUT of the semiconductor device 500 while enabling the dielectric constant of the CMUT to be tuned or optimized. For example, the sensing dielectric layer 226 and the sensing dielectric layer 502 can be formed of different materials, such as an oxide-containing dielectric material for the sensing dielectric layer 226 and a nitride-containing dielectric material (e.g., silicon nitride (SiN) and / or another nitride-containing dielectric material) for the sensing dielectric layer 502. The oxide-containing dielectric material can be formed of a low dielectric constant (low-k) dielectric material, while the nitride-containing dielectric material can be formed of a high dielectric constant (high-k) dielectric material. This allows different dielectric constant materials to be combined to achieve a desired overall dielectric constant for the CMUT.

[0105] The combined thickness of the sensing dielectric layer 226 and the thickness of the sensing dielectric layer 502 is greater than the thickness of the dielectric coating 242. For example, the combined thickness of the sensing dielectric layer 226 and the thickness of the sensing dielectric layer 502 may be within a range of approximately 1,900 angstroms to approximately 4,000 angstroms. In some embodiments, the thickness of the sensing dielectric layer 502 may be greater relative to the thickness of the sensing dielectric layer 226. In some embodiments, the thickness of the sensing dielectric layer 226 may be greater relative to the thickness of the sensing dielectric layer 502.

[0106] In some embodiments, the thickness of the sensing dielectric layer 226 combined with the thickness of the sensing dielectric layer 502 is based on the maximum operating voltage (V max ), the maximum operating voltage (V max ) may correspond to the maximum AC voltage or the maximum DC bias voltage of the CMUT. For example, the thickness of the sensing dielectric layer 226 may correspond to approximately to approximate As an example, if V max is 220 volts, the combined thickness of the sensing dielectric layer 226 and the thickness of the sensing dielectric layer 502 may be within the range of approximately 2,200 angstroms to approximately 4,400 angstroms. to approximate The range of is selected so that the combined thickness of the sensing dielectric layer 226 and the thickness of the sensing dielectric layer 502 can achieve a sufficient driving force and sufficient capacitance for the CMUT while maintaining a sufficiently high collapse voltage for the CMUT (e.g., even if the dielectric coating 242 wears out). to approximate Selecting a value for the combination of the thickness of the sensing dielectric layer 226 and the thickness of the sensing dielectric layer 502 outside the range of may result in the collapse voltage being too low, the driving force being too low, and / or the capacitance of the CMUT being too low. to approximate Other values and / or ranges outside the range are also within the scope of the present disclosure.

[0107] As shown above, Figure 5 are provided as examples. Other examples may differ from those described in Figure 5 The examples described.

[0108] Figures 6A to 6E is a diagram of an exemplary embodiment 600 for forming the semiconductor device 500 (or portion thereof) described herein. In some embodiments, a combination of Figure 1 One or more of the semiconductor processing tools 102 to 114 described herein may be used to implement the combined Figures 6A to 6EIn some embodiments, one or more of the semiconductor processing operations described herein may be used. Figure 1 Another semiconductor processing tool not shown is used to perform the combination Figures 6A to 6E One or more of the semiconductor processing operations described.

[0109] Go to Figure 6A One or more semiconductor processing operations may be performed to form the components 202 to 224 and 232 of the semiconductor device 500 and the recess 602 in the dielectric layer 232 above the sensor electrode 218 of the semiconductor device 500. Figures 4A to 4L The semiconductor processing operations described are similar to the semiconductor processing operations.

[0110] like Figure 6B As shown in FIG, a sensing dielectric layer 502, a sensing dielectric layer 226, and a nitride layer 228 may be formed on a semiconductor device 500. The sensing dielectric layer 502 may be formed on the dielectric layer 232 and in the isolation trench 224. The sensing dielectric layer 502 may also be formed on the sensing electrode 218. A portion 234c of the sensing dielectric layer 502 above the sensing electrode 218 covers a portion 234b of the dielectric layer 232. The sensing dielectric layer 226 may be formed above and / or on the sensing dielectric layer 502. Specifically, the sensing dielectric layer 226 may be formed above and / or on the sensing dielectric layer 502 in the isolation trench 224 and above the sensing electrode 218. The nitride layer 228 may be formed above and / or on the sensing dielectric layer 226. Specifically, a nitride layer 228 may be formed on and / or over the sensing dielectric layer 226 in the isolation trench 224 and over the sensing electrode 218 .

[0111] The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, a combination of Figure 1 The sensing dielectric layer 502, the sensing dielectric layer 226, and the nitride layer 228 are deposited in one or more deposition operations of another type and / or one or more deposition operations of another suitable type. In some embodiments, the sensing dielectric layer 502 is deposited using a PECVD technique using the deposition tool 102. The sensing dielectric layer 502 can be deposited conformally such that the sensing dielectric layer 502 conforms to the contour of the portion 234b of the dielectric layer 232. In some embodiments, the sensing dielectric layer 226 is deposited using a PECVD technique using the deposition tool 102. The sensing dielectric layer 226 can be deposited conformally such that the sensing dielectric layer 226 conforms to the contour of the sensing dielectric layer 502. The nitride layer 228 can be deposited conformally such that the nitride layer 228 conforms to the contour of the sensing dielectric layer 226.

[0112] like Figure 6C As shown in FIG, a HDP oxide layer 230 may be formed on and / or on the nitride layer 228. The HDP oxide layer 230 may be formed on the nitride layer 228 in the isolation trench 224 and on the nitride layer 228 above the sensing electrode 218. The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, or a combination thereof. Figure 1 The HDP oxide layer 230 is deposited in another type of one or more deposition operations and / or another suitable type of one or more deposition operations as described. In some embodiments, the HDP oxide layer 230 is deposited using a high density plasma deposition technique to blanket deposit the HDP oxide layer 230 .

[0113] like Figure 6D As shown in FIG, a portion of the HDP oxide layer 230 and a portion of the nitride layer 228 can be removed from the semiconductor device 500. In some embodiments, a planarization tool 110 can be used to perform a CMP operation or another type of planarization operation to remove the portion of the HDP oxide layer 230. In some embodiments, an etching tool 108 can be used to remove the portion of the HDP oxide layer 230 and a portion of the nitride layer 228, thereby exposing the sensing dielectric layer 226 (and associated contact base structure 234) above the sensing electrode 218. Other portions of the HDP oxide layer 230 and other portions of the nitride layer 228 can remain in the isolation trench 224.

[0114] like Figure 6E As shown in , it can then be implemented in conjunction with Figures 4Q to 4V Similar operations are performed to form the remaining layers and / or structures of the CMUT of the semiconductor device 500 .

[0115] As shown above, Figures 6A to 6E are provided as examples. Other examples may differ from those described in Figures 6A to 6E The examples described.

[0116] Figure 7 is a diagram of an exemplary semiconductor device 700 described herein. Semiconductor device 700 may be a MEMS device, such as an ultrasonic fingerprint sensor, etc. Additionally and / or alternatively, semiconductor device 700 may include another type of MEMS device, such as an RF switch, a motion sensor, and / or another type of MEMS device with mechanical contacts and a high operating voltage.

[0117] like Figure 7 As shown in FIG, semiconductor device 700 may include an arrangement of components 202 to 254 and 502 similar to semiconductor device 500. Figure 7 As further shown in FIG. 7 , semiconductor device 700 may include a combination of isolation trenches 224a and floating electrode trenches 224b extending through a stack of alternating metal layers 220 and metal nitride layers 222. The floating electrode trenches 224b may further segment or partition the sensor electrodes 218 in semiconductor device 700. The floating electrode trenches 224b may enable the sensor electrodes 218 to electrically float (e.g., not be connected to a ground structure). This may further extend the life of the CMUT of semiconductor device 700 by reducing the electrical collapse of the CMUT if one or more of the dielectric layers underlying the contact base structure 234 are damaged.

[0118] like Figure 7 As shown in FIG, the width of floating electrode trench 224b can be smaller than the width of isolation trench 224a to enable a high density of sense electrodes 218 to be included in semiconductor device 700. Isolation trench 224a and floating electrode trench 224b can each include a portion of dielectric layer 232 (the portion omitted from isolation trench 224 in semiconductor devices 200 and 500), a portion of sensing dielectric layer 502, a portion of sensing dielectric layer 226, a portion of nitride layer 228, and a portion of HDP oxide layer 230, among others. Semiconductor device 700 can further include a buffer tank 702 that extends through sensing dielectric layer 226, through sensing dielectric layer 502, through dielectric layer 232, and through top metal nitride layer 222. Buffer tank 702 can be included to tune or optimize the pressure in cavity 244.

[0119] As shown above, Figure 7 are provided as examples. Other examples may differ from those described in Figure 7 The examples described.

[0120] Figures 8A to 8H is a diagram of an exemplary embodiment 800 for forming the semiconductor device 700 (or portion thereof) described herein. In some embodiments, a combination of Figure 1 One or more of the semiconductor processing tools 102 to 114 described herein may be used to implement the combined Figures 8A to 8H In some embodiments, one or more of the semiconductor processing operations described herein may be used. Figure 1 Another semiconductor processing tool not shown is used to perform the combination Figures 8A to 8H One or more of the semiconductor processing operations described.

[0121] Go to Figure 8A , one or more semiconductor processing operations may be performed to form components 202 to 224 of semiconductor device 700. Figures 4A to 4I The semiconductor processing operations described are similar to the semiconductor processing operations.

[0122] like Figure 8B As shown in FIG, the isolation trench 224a and the floating electrode trench 224b can be formed by alternating stacks of metal layers 220 and metal nitride layers 222. Figure 4L Isolation trench 224 is formed in semiconductor device 200. Isolation trench 224a and floating electrode trench 224b can be formed in semiconductor device 700 before dielectric layer 232 is formed. This process may be referred to as a "pedestal last" process. The formation of isolation trench 224a and floating electrode trench 224b allows for the formation of sensor electrode 218 of the CMUT of semiconductor device 700. Isolation trench 224a electrically isolates sensor electrode 218, while floating electrode trench 224b allows for a floating ground connection for the ground connection of sensor electrode 218.

[0123] In some embodiments, the isolation trenches 224a and the floating electrode trenches 224b are formed using a pattern in the photoresist layer through the alternating stack of metal layers 220 and metal nitride layers 222. In these embodiments, a photoresist layer is formed on the top metal nitride layer 222 using a deposition tool 102. The photoresist layer is exposed to a radiation source using an exposure tool 104 to pattern the photoresist layer. The photoresist layer is developed using a development tool 106 and portions of the photoresist layer are removed to expose the pattern. An etching tool 108 is used to etch through the alternating stack of metal layers 220 and metal nitride layers 222 based on the pattern to form the isolation trenches 224a and the floating electrode trenches 224b. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based formation of the isolation trench 224 a and the floating electrode trench 224 b .

[0124] like Figure 8CAs shown in FIG, dielectric layer 232, sensing dielectric layer 502, and sensing dielectric layer 226 may be formed on semiconductor device 700. Dielectric layer 232 may be formed on top metal nitride layer 222 and in isolation trench 224a and floating electrode trench 224b. Dielectric layer 232 may also be formed on sensor electrode 218. Sensing dielectric layer 502 may be formed over and / or on dielectric layer 232. Specifically, sensing dielectric layer 502 may be formed over dielectric layer 232 in isolation trench 224a and floating electrode trench 224b and / or over dielectric layer 232 in isolation trench 224a and floating electrode trench 224b and over sensor electrode 218. Sensing dielectric layer 226 may be formed over and / or on sensing dielectric layer 502. Specifically, the sensing dielectric layer 226 may be formed over the sensing dielectric layer 502 in the isolation trench 224a and the floating electrode trench 224b and / or over the sensing dielectric layer 502 in the isolation trench 224a and the floating electrode trench 224b and over the sensor electrode 218 .

[0125] The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, a combination of Figure 1 The dielectric layer 232, the sensing dielectric layer 502, and the sensing dielectric layer 226 are deposited in one or more deposition operations of another type and / or one or more deposition operations of another suitable type. In some embodiments, the sensing dielectric layer 502 is deposited using a PECVD technique using the deposition tool 102. The sensing dielectric layer 502 can be deposited conformally such that the sensing dielectric layer 502 conforms to the contours of the isolation trench 224a and the floating electrode trench 224b. In some embodiments, the sensing dielectric layer 226 is deposited using a PECVD technique using the deposition tool 102. The sensing dielectric layer 226 can be deposited conformally such that the sensing dielectric layer 226 conforms to the contours of the isolation trench 224a and the floating electrode trench 224b.

[0126] like Figure 8DAs shown in FIG, portions of the sensing dielectric layer 226 may be removed to facilitate forming the contact base structure 234. For example, portions of the sensing dielectric layer 226 may be removed from one or more of the isolation trenches 224a, from one or more of the floating electrode trenches 224b, and / or from one or more portions of the sensing dielectric layer 502. In some embodiments, portions of the sensing dielectric layer 226 are removed using a pattern in a photoresist layer. In these embodiments, a deposition tool 102 is used to form the photoresist layer on the sensing dielectric layer 226. An exposure tool 104 is used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 is used to develop the photoresist layer and remove portions of the photoresist layer to expose a pattern. An etching tool 108 is used to etch through the sensing dielectric layer 226 based on the pattern to remove portions of the sensing dielectric layer 226. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. In some embodiments, a photoresist removal tool removes the remainder of the photoresist layer (eg, using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based removal of portions of the sensing dielectric layer 226.

[0127] like Figure 8E , additional material for the sensing dielectric layer 226 may be deposited. The additional material for the sensing dielectric layer 226 may be formed over the sensing dielectric layer 226 to create a contact base structure 234. The additional material for the sensing dielectric layer 226 may also be deposited in the isolation trenches 224a and the floating electrode trenches 224b. In some embodiments, the additional material for the sensing dielectric layer 226 is deposited using PECVD techniques using the deposition tool 102.

[0128] like Figure 8E As further shown in FIG. 1 , a nitride layer 228 may be formed on the sensing dielectric layer 226. The nitride layer 228 may be formed on the sensing dielectric layer 226 in the isolation trench 224a, on the sensing dielectric layer 226 in the floating electrode trench 224b, and on the sensing dielectric layer 226 above the sensing electrode 218. The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, or a combination thereof. Figure 1 The nitride layer 228 is deposited in another type of one or more deposition operations and / or another suitable type of one or more deposition operations. The nitride layer 228 can be conformally deposited such that the nitride layer 228 conforms to the topography of the sensing dielectric layer 226.

[0129] like Figure 8EAs further shown in FIG. 1 , a HDP oxide layer 230 may be formed on and / or on the nitride layer 228. The HDP oxide layer 230 may be formed on the nitride layer 228 in the isolation trench 224a, on the nitride layer 228 in the floating electrode trench 224b, and on the nitride layer 228 on the sensing electrode 218. The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, or a combination thereof. Figure 1 The HDP oxide layer 230 is deposited in another type of one or more deposition operations and / or another suitable type of one or more deposition operations as described. In some embodiments, the HDP oxide layer 230 is deposited using a high density plasma deposition technique to blanket deposit the HDP oxide layer 230 .

[0130] like Figure 8F As shown in FIG, a portion of the HDP oxide layer 230 and a portion of the nitride layer 228 can be removed from the semiconductor device 700. In some embodiments, a planarization tool 110 can be used to perform a CMP operation or another type of planarization operation to remove the portion of the HDP oxide layer 230. In some embodiments, an etching tool 108 can be used to remove the portion of the HDP oxide layer 230 and a portion of the nitride layer 228, thereby exposing the sensing dielectric layer 226 (and associated contact base structure 234) above the sensing electrode 218. Other portions of the HDP oxide layer 230 and other portions of the nitride layer 228 can remain in the isolation trench 224a and the floating electrode trench 224b.

[0131] like Figure 8GAs shown in FIG, a buffer tank 702 can be formed in and / or through the sensing dielectric layer 226, the sensing dielectric layer 502, the dielectric layer 232, and / or the top metal nitride layer 222. In some embodiments, the buffer tank 702 is formed using a pattern in a photoresist layer. In these embodiments, a photoresist layer is formed on the sensing dielectric layer 226 using a deposition tool 102. The photoresist layer is exposed to a radiation source using an exposure tool 104 to pattern the photoresist layer. The photoresist layer is developed using a development tool 106 and portions of the photoresist layer are removed to expose a pattern. An etching tool 108 is used to etch the sensing dielectric layer 226, the sensing dielectric layer 502, the dielectric layer 232, and / or the top metal nitride layer 222 based on the pattern to form the buffer tank 702. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for forming the buffer tank 702 based on the pattern.

[0132] like Figure 8H As shown in , it can then be implemented in conjunction with Figures 4Q to 4V Similar operations are performed to form the remaining layers and / or structures of the CMUT of the semiconductor device 700 .

[0133] As shown above, Figures 8A to 8H are provided as examples. Other examples may differ from those described in Figures 8A to 8H The examples described.

[0134] Figure 9 is a diagram of exemplary components of the apparatus 900 described herein. In some embodiments, one or more of the semiconductor processing tools 102-114 and / or the wafer / die transport 116 may include one or more apparatuses 900 and / or one or more components of the apparatus 900. Figure 9 As shown in FIG, the device 900 may include a bus 910 , a processor 920 , a memory 930 , an input component 940 , an output component 950 and / or a communication component 960 .

[0135] The bus 910 may include one or more components that enable wired and / or wireless communication between components of the device 900. The bus 910 may include one or more components that enable wired and / or wireless communication between components of the device 900. Figure 9Two or more components are shown coupled together (e.g., via operational coupling, communicative coupling, electronic coupling, and / or electrical coupling). For example, bus 910 may include electrical connections (e.g., wiring, traces, and / or leads) and / or a wireless bus. Processor 920 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application-specific integrated circuit, and / or another type of processing component. Processor 920 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 920 may include one or more processors that are capable of being programmed to perform one or more operations or processes described elsewhere herein.

[0136] Memory 930 may include volatile memory and / or non-volatile memory. For example, memory 930 may include random access memory (RAM), read-only memory (ROM), a hard drive, and / or another type of memory (e.g., flash memory, magnetic storage, and / or optical storage). Memory 930 may include internal memory (e.g., RAM, ROM, or a hard drive) and / or removable memory (e.g., removable via a universal serial bus connection). Memory 930 may be a non-transitory computer-readable medium. Memory 930 may store information related to the operation of device 900, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, memory 930 may include one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 920) via bus 910. The communicative coupling between processor 920 and memory 930 may enable processor 920 to read and / or process information stored in memory 930 and / or store information in memory 930.

[0137] Input components 940 enable device 900 to receive input, such as user input and / or sensed input. For example, input components 940 may include a touch screen, a keyboard, a keypad, a mouse, buttons, a microphone, a switch, a sensor, a GPS sensor, a GNSS sensor, an accelerometer, a gyroscope, and / or an actuator. Output components 950 enable device 900 to provide output, such as via a display, a speaker, and / or a light-emitting diode. Communication components 960 enable device 900 to communicate with other devices via wired and / or wireless connections. For example, communication components 960 may include a receiver, a transmitter, a transceiver, a modem, a network adapter, and / or an antenna.

[0138] The device 900 may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 930) may store a set of instructions (e.g., one or more instructions or codes) for execution by the processor 920. The processor 920 may execute the set of instructions to perform one or more operations or processes described herein. In some embodiments, execution of the set of instructions by the one or more processors 920 causes the one or more processors 920 and / or the device 900 to perform one or more operations or processes described herein. In some embodiments, hardwired circuitry may be used in place of or in combination with the instructions to perform one or more operations or processes described herein. Additionally or alternatively, the processor 920 may be configured to perform one or more operations or processes described herein. Thus, the embodiments described herein are not limited to any specific combination of hardwired circuitry and software.

[0139] Figure 9 The number and arrangement of components shown in are provided as examples. Figure 9 , device 900 may include additional components, fewer components, different components, or components arranged differently. Additionally or alternatively, one set of components (e.g., one or more components) of device 900 may perform one or more functions described as being performed by another set of components of device 900.

[0140] Figure 10 is a flow chart of an exemplary process 1000 associated with forming a semiconductor device as described herein. In some embodiments, Figure 10 One or more process blocks are shown as being performed using one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-114). Additionally or alternatively, Figure 10 One or more of the process blocks shown may be implemented by one or more components of the apparatus 900 , such as the processor 920 , the memory 930 , the input component 940 , the output component 950 , and / or the communication component 960 .

[0141] like Figure 10 As shown in FIG, process 1000 may include forming a layer stack including alternating metal layers and metal nitride layers on a semiconductor device (block 1010). For example, a layer stack including alternating metal layers 220 and metal nitride layers 222 may be formed on semiconductor device 200 using one or more of semiconductor processing tools 102-114 as described herein.

[0142] like Figure 10As further shown in FIG, process 1000 may include forming a first dielectric layer on the layer stack (block 1020). For example, the first dielectric layer (e.g., dielectric layer 232) may be formed on the layer stack using one or more of semiconductor processing tools 102-114 as described herein.

[0143] like Figure 10 As further shown in FIG, process 1000 may include removing a first portion of the first dielectric layer such that a second portion of the first dielectric layer remains on the layer stack (block 1030). For example, as described herein, one or more of semiconductor processing tools 102-114 may be used to remove the first portion of the first dielectric layer such that a second portion of the first dielectric layer (e.g., portion 234b) remains on the layer stack.

[0144] like Figure 10 As further shown in FIG. 1 , process 1000 may include removing a portion of the layer stack to form a sensor electrode from the layer stack (block 1040). For example, as described herein, one or more of semiconductor processing tools 102 to 114 may be used to remove a portion of the layer stack to form sensor electrode 218 from the layer stack. In some embodiments, a second portion of the first dielectric layer is included on sensor electrode 218. In some embodiments, removing the portion of the layer stack forms isolation trench 224 on opposite sides of sensor electrode 218.

[0145] like Figure 10 As further shown in FIG. 1 , process 1000 may include forming a second dielectric layer on the sense electrode and on the second portion of the first dielectric layer (block 1050). For example, as described herein, the second dielectric layer (e.g., sense dielectric layer 226) may be formed on the sense electrode and on the second portion of the first dielectric layer using one or more of semiconductor processing tools 102-114. In some embodiments, the second dielectric layer is formed in isolation trench 224. In some embodiments, forming the second dielectric layer on the second portion of the first dielectric layer forms a plurality of contact pedestal structures 234 above sense electrode 218. In some embodiments, a nitride layer 228 and a HDP oxide layer 230 may be formed on the second dielectric layer in isolation trench 224. In some embodiments, a pressure port 246 may be formed on the second dielectric layer adjacent to sense electrode 218. In some embodiments, forming the second dielectric layer includes performing a PECVD technique to deposit a plasma-enhanced oxide material for the second dielectric layer.

[0146] like Figure 10As further shown in FIG. 1 , process 1000 may include bonding the actuator diaphragm to the semiconductor device (block 1060). For example, as described herein, the actuator diaphragm 240 may be bonded to the semiconductor device 200 using one or more of the semiconductor processing tools 102 to 112. In some embodiments, the actuator diaphragm 240 is bonded to the semiconductor device 200 such that a cavity 244 is formed between the actuator diaphragm 240 and the second dielectric layer. In some embodiments, a dielectric coating 242 is formed on the actuator diaphragm 240 before bonding the actuator diaphragm 240 to the semiconductor device 200. In some embodiments, the dielectric coating 242 faces the cavity 244. In some embodiments, the dielectric coating 242 is formed using a thermal oxidation technique. In some embodiments, the second dielectric layer has a thickness greater than a thickness of the dielectric coating 242.

[0147] Process 1000 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0148] although Figure 10 Example blocks of process 1000 are shown, however, in some embodiments, compared to Figure 10 , process 1000 may include additional blocks, fewer blocks, different blocks, or blocks arranged differently than the blocks depicted in . Additionally or alternatively, two or more of the blocks of process 1000 may be performed in parallel.

[0149] Figure 11 is a flow chart of an exemplary process 1100 associated with forming a semiconductor device described herein. In some embodiments, Figure 11 One or more process blocks shown are performed using one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-114). Additionally or alternatively, Figure 11 One or more of the process blocks shown may be implemented by one or more components of the apparatus 900 , such as the processor 920 , the memory 930 , the input component 940 , the output component 950 , and / or the communication component 960 .

[0150] like Figure 11 As shown in FIG, process 1100 may include forming a layer stack including alternating metal layers and metal nitride layers on a semiconductor device (block 1110). For example, a layer stack including alternating metal layers 220 and metal nitride layers 222 may be formed on semiconductor device 500 using one or more of semiconductor processing tools 102-114 as described herein.

[0151] like Figure 11As further shown in FIG, process 1100 may include forming a first dielectric layer on the layer stack (block 1120). For example, the first dielectric layer (e.g., dielectric layer 232) may be formed on the layer stack using one or more of semiconductor processing tools 102-114 as described herein.

[0152] like Figure 11 As further shown in FIG, process 1100 may include removing a first portion of the first dielectric layer such that a second portion of the first dielectric layer remains on the layer stack (block 1130). For example, as described herein, one or more of semiconductor processing tools 102-114 may be used to remove the first portion of the first dielectric layer such that a second portion of the first dielectric layer (e.g., portion 234b) remains on the layer stack.

[0153] like Figure 11 As further shown in FIG. 1 , process 1100 may include removing a portion of the layer stack to form a sensor electrode from the layer stack (block 1140). For example, as described herein, one or more of semiconductor processing tools 102 to 114 may be used to remove a portion of the layer stack to form sensor electrode 218 from the layer stack. In some embodiments, a second portion of the first dielectric layer is included on sensor electrode 218. In some embodiments, removing the portion of the layer stack forms isolation trench 224 on opposite sides of sensor electrode 218.

[0154] like Figure 11 As further shown in FIG. 1 , process 1100 may include forming a second dielectric layer on the sense electrode and on the second portion of the first dielectric layer (block 1150). For example, as described herein, the second dielectric layer (e.g., sense dielectric layer 502) may be formed on the sense electrode and on the second portion of the first dielectric layer using one or more of semiconductor processing tools 102-114. In some embodiments, the second dielectric layer is formed in isolation trench 224. In some embodiments, forming the second dielectric layer on the second portion of the first dielectric layer allows for formation of a plurality of contact pedestal structures 234 above the sense electrode 218. In some embodiments, a nitride layer 228 and a HDP oxide layer 230 may be formed on the second dielectric layer in the isolation trench 224. In some embodiments, a pressure port 246 may be formed on the second dielectric layer adjacent to the sense electrode 218. In some embodiments, forming the second dielectric layer includes performing a PECVD technique to deposit a plasma-enhanced oxide material for the second dielectric layer.

[0155] like Figure 11As further shown in FIG. 1 , process 1100 may include forming a third dielectric layer on the second dielectric layer (block 1160). For example, as described herein, the third dielectric layer (e.g., sensing dielectric layer 226) may be formed on the second dielectric layer using one or more of semiconductor processing tools 102 through 114. In some embodiments, the third dielectric layer is formed within isolation trenches 224. In some embodiments, the third dielectric layer is formed on a second portion of the second dielectric layer such that a plurality of contact pedestal structures 234 are formed above sensing electrode 218. In some embodiments, a nitride layer 228 and a HDP oxide layer 230 may be formed above the third dielectric layer within isolation trenches 224. In some embodiments, pressure port 246 may be formed above the third dielectric layer adjacent to sensing electrode 218. In some embodiments, forming the third dielectric layer includes performing a PECVD technique to deposit a plasma-enhanced nitride material for the third dielectric layer. In some embodiments, the second and third dielectric layers comprise different dielectric materials. In some embodiments, the first dielectric layer and the third dielectric layer include the same dielectric material combination.

[0156] like Figure 11 As further shown in FIG. 1 , process 1100 may include bonding the actuator membrane to the semiconductor device (block 1170). For example, the actuator membrane 240 may be bonded to the semiconductor device 500 using one or more of the semiconductor processing tools 102 to 112, as described herein. In some embodiments, the actuator membrane 240 is bonded to the semiconductor device 500 such that a cavity 244 is formed between the actuator membrane 240 and the third dielectric layer. In some embodiments, a dielectric coating 242 is formed on the actuator membrane 240 before bonding the actuator membrane 240 to the semiconductor device 500. In some embodiments, the dielectric coating 242 faces the cavity 244. In some embodiments, the dielectric coating 242 is formed using a thermal oxidation technique. In some embodiments, the combined thickness of the second dielectric layer and the third dielectric layer is greater than the thickness of the dielectric coating 242.

[0157] Process 1100 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0158] although Figure 11 Example blocks of process 1100 are shown, however, in some embodiments, compared to Figure 10 , process 1100 may include additional blocks, fewer blocks, different blocks, or blocks arranged differently than the blocks depicted in . Additionally or alternatively, two or more of the blocks of process 1100 may be performed in parallel.

[0159] Figure 12is a flow chart of an exemplary process 1200 associated with forming a semiconductor device described herein. In some embodiments, Figure 12 One or more process blocks shown are performed using one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-114). Additionally or alternatively, Figure 12 One or more of the process blocks shown may be implemented by one or more components of the apparatus 900 , such as the processor 920 , the memory 930 , the input component 940 , the output component 950 , and / or the communication component 960 .

[0160] like Figure 12 As shown in FIG, process 1200 may include forming a layer stack including alternating metal layers and metal nitride layers on a semiconductor device (block 1210). For example, a layer stack including alternating metal layers 220 and metal nitride layers 222 may be formed on semiconductor device 700 using one or more of semiconductor processing tools 102-114 as described herein.

[0161] like Figure 12 As further shown in FIG1 , process 1200 may include removing portions of the layer stack to form a sense electrode from the layer stack (block 1220). For example, as described herein, one or more of semiconductor processing tools 102-114 may be used to remove portions of the layer stack to form sense electrode 218 from the layer stack. In some embodiments, removing portions of the layer stack forms isolation trenches 224a on opposite sides of sense electrode 218. In some embodiments, removing portions of the layer stack forms one or more floating electrode trenches 224b between isolation trench 224a and sense electrode 218.

[0162] like Figure 12 As further shown in FIG1 , process 1200 may include forming a first dielectric layer on the sense electrode (block 1230). For example, as described herein, the first dielectric layer (e.g., dielectric layer 232) may be formed on the sense electrode 218 using one or more of semiconductor processing tools 102-114. In some embodiments, the first dielectric layer is formed in the isolation trench 224a. In some embodiments, the first dielectric layer is formed in the floating electrode trench 224b.

[0163] like Figure 12As further shown in FIG. 1 , process 1200 may include forming a second dielectric layer on the first dielectric layer (block 1240). For example, as described herein, the second dielectric layer (e.g., sensing dielectric layer 502) may be formed on the first dielectric layer using one or more of semiconductor processing tools 102-114. In some embodiments, the second dielectric layer is formed over and / or on the first dielectric layer in isolation trench 224a. In some embodiments, the second dielectric layer is formed over and / or on the first dielectric layer in floating electrode trench 224b. In some embodiments, the second dielectric layer is formed over and / or on the first dielectric layer over sensor electrode 218.

[0164] like Figure 12 As further shown in FIG. 1 , process 1200 may include forming a third dielectric layer on the second dielectric layer (block 1250). For example, as described herein, the third dielectric layer (e.g., sensing dielectric layer 226) may be formed on the second dielectric layer using one or more of semiconductor processing tools 102-114. In some embodiments, the third dielectric layer is formed over the second dielectric layer in isolation trench 224a and / or on the second dielectric layer in isolation trench 224a. In some embodiments, the third dielectric layer is formed over the second dielectric layer in floating electrode trench 224b and / or on the second dielectric layer in floating electrode trench 224b. In some embodiments, the third dielectric layer is formed over the second dielectric layer over sensor electrode 218 and / or on the second dielectric layer over sensor electrode 218.

[0165] like Figure 12 As further shown in FIG, process 1200 may include removing a first portion of the third dielectric layer such that a second portion of the third dielectric layer remains over the sense electrode (block 1260). For example, as described herein, one or more of semiconductor processing tools 102-114 may be used to remove the first portion of the third dielectric layer such that a second portion of the third dielectric layer (e.g., portion 234a) remains over the sense electrode 218. In some embodiments, the first portion may be removed as part of forming a contact base structure 234 over the sense electrode 218.

[0166] like Figure 12As further shown in FIG. 1 , process 1200 may include depositing additional material of the third dielectric layer to form a contact base structure over the sense electrode (block 1270). For example, as described herein, one or more of semiconductor processing tools 102 to 114 may be used to deposit additional material of the third dielectric layer to form contact base structure 234 over the sense electrode 218. In some embodiments, the additional material may be deposited in one or more of the isolation trenches 224a. In some embodiments, the additional material may be deposited in one or more of the floating electrode trenches 224b.

[0167] like Figure 12 As further shown in FIG. 1 , process 1200 may include bonding the actuator diaphragm to the semiconductor device (block 1280). For example, the actuator diaphragm 240 may be bonded to the semiconductor device 700 using one or more of the semiconductor processing tools 102 to 112, as described herein. In some embodiments, the actuator diaphragm 240 is bonded to the semiconductor device 700 such that a cavity 244 is formed between the actuator diaphragm 240 and the third dielectric layer. In some embodiments, a dielectric coating 242 is formed on the actuator diaphragm 240 before bonding the actuator diaphragm 240 to the semiconductor device 700. In some embodiments, the dielectric coating 242 faces the cavity 244. In some embodiments, the dielectric coating 242 is formed using a thermal oxidation technique. In some embodiments, the combined thickness of the second dielectric layer and the third dielectric layer is greater than the thickness of the dielectric coating 242.

[0168] Process 1200 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0169] although Figure 12 Example blocks of process 1200 are shown, however, in some embodiments, compared to Figure 12 , process 1200 may include additional blocks, fewer blocks, different blocks, or blocks arranged differently than the blocks shown in FIG. Additionally or alternatively, two or more of the blocks of process 1200 may be performed in parallel.

[0170] In this manner, a MEMS device may include a CMUT comprising an actuating diaphragm and a sensing dielectric layer separated by a cavity (e.g., an air gap). The sensing dielectric layer may be formed to be at a sufficiently high V that the CMUT can accommodate for collapse mode operation. dc-biasAt the same time, the thickness of the sensing dielectric layer can extend the operating life of the CMUT. For example, the thickness of the sensing dielectric layer can be greater than the thickness of the dielectric coating on the underside of the actuating diaphragm. In this way, the thickness of the sensing dielectric layer enables the CMUT to operate in a collapse mode, which enables the CMUT to achieve a greater sound pressure output relative to other operating modes and enables the frequency response of the CMUT to be adjustable, thereby enabling the frequency response to be optimized for specific use cases and applications. In addition, the thickness of the sensing dielectric layer can enable the CMUT to operate at a sustained high collapse voltage for a longer period of time (e.g., relative to a CMUT including a thinner sensing dielectric layer), which reduces the likelihood of premature wear and extends the operating life of the CMUT.

[0171] As described in greater detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a sensing electrode located above a substrate and between a plurality of isolation trenches. The semiconductor device includes multiple portions of a first dielectric layer located above the sensing electrode. The semiconductor device includes a portion of a second dielectric layer located above the sensing electrode and above the multiple portions of the first dielectric layer. The semiconductor device includes an actuating diaphragm located above the second dielectric layer, wherein the actuating diaphragm is separated from the second dielectric layer by a cavity. The semiconductor device includes a third dielectric layer located above the actuating diaphragm, wherein the third dielectric layer is located between the actuating diaphragm and the cavity, and wherein the portion of the second dielectric layer has a thickness greater than a thickness of the third dielectric layer.

[0172] In some embodiments, portions of the first dielectric layer and portions of the second dielectric layer form a plurality of contact base structures above the sensor electrode. In some embodiments, the sensor electrode, the actuation membrane, and the plurality of contact base structures correspond to capacitive micromachined ultrasonic transducers included in the semiconductor device. In some embodiments, the first dielectric layer comprises at least one of the following: plasma-enhanced oxide, plasma-enhanced nitride, or aluminum oxide. In some embodiments, the second dielectric layer comprises at least one of the following: plasma-enhanced oxide, plasma-enhanced nitride, or aluminum oxide. In some embodiments, the third dielectric layer comprises thermal oxide.

[0173] As described in greater detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a sensing electrode located above a substrate and between a plurality of isolation trenches. The semiconductor device includes multiple portions of a first dielectric layer located above the sensing electrode. The semiconductor device includes a portion of a second dielectric layer located above the sensing electrode and above the multiple portions of the first dielectric layer. The semiconductor device includes a portion of a third dielectric layer located above the portion of the second dielectric layer. The semiconductor device includes an actuation diaphragm located above the third dielectric layer, wherein the actuation diaphragm is separated from the third dielectric layer by a cavity.

[0174] In some embodiments, the second dielectric layer has a thickness greater than that of the first dielectric layer; and the second dielectric layer has a thickness greater than that of the third dielectric layer. In some embodiments, the second dielectric layer, the third dielectric layer, the fourth dielectric layer, and the fifth dielectric layer are included in a plurality of isolation trenches. In some embodiments, the first dielectric layer comprises a plasma-enhanced oxide. In some embodiments, the second dielectric layer comprises a plasma-enhanced nitride. In some embodiments, the third dielectric layer comprises another plasma-enhanced oxide. In some embodiments, portions of the first dielectric layer, a portion of the second dielectric layer, and a portion of the third dielectric layer form a plurality of contact base structures above the sensor electrode. In some embodiments, the sensor electrode, the actuation membrane, and the plurality of contact base structures correspond to capacitive micromachined ultrasonic transducers included in the semiconductor device.

[0175] As described in more detail above, some embodiments described herein provide a method of forming a semiconductor device, comprising: forming a layer stack comprising alternating metal layers and metal nitride layers on the semiconductor device; removing portions of the layer stack to form a sensing electrode from the layer stack; forming a first dielectric layer on the sensing electrode; forming a second dielectric layer on the first dielectric layer; forming a third dielectric layer on the second dielectric layer; removing a first portion of the third dielectric layer such that a second portion of the third dielectric layer remains over the sensing electrode; depositing additional material of the third dielectric layer to form a contact base structure over the sensing electrode; and bonding an actuating diaphragm to the semiconductor device.

[0176] In some embodiments, the first, second, third, fourth, and fifth dielectric layers are included in an isolation trench. In some embodiments, the first, second, third, fourth, and fifth dielectric layers are included in a floating electrode trench. In some embodiments, the first dielectric layer comprises a plasma-enhanced oxide; the second dielectric layer comprises a plasma-enhanced nitride; and the third dielectric layer comprises another plasma-enhanced oxide. In some embodiments, the fourth dielectric layer comprises another plasma-enhanced nitride; and the fifth dielectric layer comprises a high-density plasma oxide. In some embodiments, the sensing electrode, actuation membrane, and contact base structures correspond to capacitive micromachined ultrasonic transducers included in the semiconductor device.

[0177] As described in greater detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a sensing electrode located above a substrate and between a first isolation trench and a second isolation trench. The semiconductor device includes a contact base structure located above the sensing electrode and between the first isolation trench and the floating electrode trench, the contact base structure including a portion of a first dielectric layer located above the sensing electrode, a portion of a second dielectric layer located above the sensing electrode and above the portion of the first dielectric layer, and a portion of a third dielectric layer located above the portion of the second dielectric layer. The semiconductor device includes an actuation diaphragm located above the third dielectric layer, wherein the actuation diaphragm is separated from the contact base structure by a cavity.

[0178] As used herein, “satisfying a threshold” may refer to a value that is greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, or the like, depending on the context.

[0179] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: include: a sensing electrode disposed above the substrate and between the plurality of isolation trenches; a plurality of portions of a first dielectric layer located on the sensing electrodes; A portion of the second dielectric layer is located on the sensing electrode and the portions of the first dielectric layer, an actuating diaphragm located above the second dielectric layer, wherein the actuating diaphragm is separated from the second dielectric layer by a cavity; as well as a third dielectric layer, located on the actuating diaphragm, wherein the third dielectric layer is located between the actuating diaphragm and the cavity, and The thickness of the portion of the second dielectric layer is greater than the thickness of the third dielectric layer.

2. The semiconductor device according to claim 1, wherein The portions of the first dielectric layer and the portion of the second dielectric layer form a plurality of contact base structures over the sensor electrodes.

3. The semiconductor device according to claim 2, wherein The sensing electrodes, the actuating membrane, and the plurality of contact base structures correspond to capacitive micromachined ultrasonic transducers included in the semiconductor device.

4. The semiconductor device according to claim 1, wherein The sensing electrode comprises a layer stack of alternating metal layers and metal nitride layers.

5. A semiconductor device, characterized in that: include: a sensing electrode disposed above the substrate and between the plurality of isolation trenches; a plurality of portions of a first dielectric layer located on the sensing electrodes; a portion of a second dielectric layer located on the sensing electrode and the portions of the first dielectric layer; a portion of a third dielectric layer located on the portion of the second dielectric layer; as well as an actuating diaphragm located above the third dielectric layer, The actuating membrane and the third dielectric layer are separated by a cavity.

6. The semiconductor device according to claim 5, wherein The thickness of the second dielectric layer is greater than the thickness of the first dielectric layer; and The thickness of the second dielectric layer is greater than the thickness of the third dielectric layer.

7. The semiconductor device according to claim 5, wherein The second dielectric layer, the third dielectric layer, the fourth dielectric layer, and the fifth dielectric layer are included in the plurality of isolation trenches.

8. The semiconductor device according to claim 5, wherein The portions of the first dielectric layer, the portion of the second dielectric layer, and the portion of the third dielectric layer form a plurality of contact base structures over the sensor electrodes.

9. The semiconductor device according to claim 8, wherein The sensing electrodes, the actuating membrane, and the plurality of contact base structures correspond to capacitive micromachined ultrasonic transducers included in the semiconductor device.

10. The semiconductor device according to claim 5, wherein The sensing electrode comprises a layer stack of alternating metal layers and metal nitride layers.

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