FPGA (Field Programmable Gate Array) chip aging test system, configuration module and integrated circuit test carrier plate

Abstract

The utility model discloses a field programmable gate array (FPGA) chip aging test system, a configuration module and an integrated circuit test carrier plate, and belongs to the field of semiconductor chip test. Comprising a configuration module and an integrated circuit test carrier plate which are connected in a pluggable mode through a configuration interface, the integrated circuit test carrier plate comprises a plurality of FPGA chips which are sequentially connected in series, and a configuration output pin of the former FPGA chip is connected with a configuration input pin of the latter FPGA chip. An input pin and an output pin of the configuration interface are respectively connected with a configuration input pin of the first FPGA chip and a configuration output pin of the last FPGA chip; the configuration module comprises a main control system, a power management circuit and a configuration interface circuit, the main control system, the configuration interface circuit and the configuration interface circuit are connected in sequence, and the power management circuit is connected with the main control system and the configuration interface circuit and supplies power. According to the utility model, the manual operation is greatly reduced, and the interference risk in the testing process of the aging test is reduced.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor chip testing, in particular to an FPGA chip burn-in test system, a configuration module and an integrated circuit test carrier board. Background Art

[0002] During burn-in testing, the internal circuits of FPGA chips must first be configured. In the existing technology, each FPGA chip has a different number of pins or the signals that the pins need to receive are different. Therefore, when FPGA chip testing is required, a configuration module is required to configure multiple (for example, 12) FPGA chips to be tested on the integrated circuit test carrier one by one.

[0003] However, on existing integrated circuit test boards, each FPGA chip corresponds to a configuration interface. Configuration requires plugging a configuration module into the interface, unplugging it after configuration is complete, and then plugging it into the next interface, configuring each FPGA chip in turn. This configuration method significantly increases manual labor, consumes configuration time, and increases testing costs. Furthermore, the frequent plugging and unplugging of the configuration module from the integrated circuit test board increases the connection strength between the chip under test and the integrated circuit test board, which undoubtedly increases the risk of interference during the burn-in test and affects the test results. Utility Model Content

[0004] The utility model provides an FPGA chip burn-in test system, a configuration module and an integrated circuit test carrier board, which greatly reduce manual operations, reduce configuration time and test costs, and reduce interference risks during the burn-in test process.

[0005] The utility model provides the following technical solutions:

[0006] An FPGA chip burn-in test system includes a configuration module and an integrated circuit test carrier, wherein the configuration module and the integrated circuit test carrier are pluggable connected via a configuration interface, wherein:

[0007] The integrated circuit test carrier includes multiple FPGA chips, which are sequentially connected in series, with the configuration output pin of the previous FPGA chip connected to the configuration input pin of the next FPGA chip, the input pin of the configuration interface connected to the configuration input pin of the first FPGA chip, and the output pin of the configuration interface connected to the configuration output pin of the last FPGA chip;

[0008] The configuration module includes a main control system, a power management circuit and a configuration interface circuit. The main control system, the configuration interface circuit and the configuration interface are connected in sequence. The power management circuit is connected to the main control system and the configuration interface circuit and supplies power.

[0009] Furthermore, the mode selection pin and the clock pin of the configuration interface are respectively connected in parallel with the mode selection pin and the clock pin of each FPGA chip.

[0010] Furthermore, the integrated circuit test carrier board further includes a power supply module, the power supply module is connected to each FPGA chip and supplies power, and the power supply module is connected to the power pin of the configuration interface;

[0011] The power management circuit includes a first power supply end connected to the power pin of the configuration interface, a second power supply end connected to the power pin of the main control system, a MOS transistor Q1, and a MOS transistor Q2. The S pole and D pole of the MOS transistor Q1 are respectively connected to the first power supply end and the second power supply end. The G pole of the MOS transistor Q2 is connected to the power-up and power-down control pins of the main control system. The S pole of the MOS transistor Q2 is grounded, and the D pole of the MOS transistor Q2 is connected to the G pole of the MOS transistor Q1.

[0012] Furthermore, the power management circuit also includes a diode D1, the anode of the diode D1 is connected to the upper and lower power control pins, and the cathode is connected to the G pole of the MOS tube Q2. The first end of the power supply is connected to the G pole of the MOS tube Q2 through the parallel capacitor C1 and capacitor C2. The G pole of the MOS tube Q2 is connected to the resistor R6 and then grounded.

[0013] Furthermore, the first end of the power supply is connected to the parallel resistors R4 and C3 and then grounded, the second end of the power supply is connected to the parallel resistors R5 and C4 and then grounded, and the first end of the power supply is connected to the resistor R3 and then connected to the G pole of the MOS tube Q1.

[0014] Furthermore, the configuration interface circuit includes an input signal configuration circuit, an output signal configuration circuit, a mode selection signal configuration circuit and a clock signal configuration circuit. The input pin, mode selection pin and clock pin of the main control system are connected to the input pin, mode selection pin and clock pin of the configuration interface through the input signal configuration circuit, mode selection signal configuration circuit and clock signal configuration circuit respectively, and the output pin of the configuration interface is connected to the output pin of the main control system through the output signal configuration circuit.

[0015] Furthermore, the input signal configuration circuit, the output signal configuration circuit, the mode selection signal configuration circuit, and the clock signal configuration circuit each include a respective MOS transistor; the G poles of the MOS transistors of the input signal configuration circuit, the mode selection signal configuration circuit, and the clock signal configuration circuit are respectively connected to the input pin, the mode selection pin, and the clock pin of the main control system; the D poles are respectively connected to the input pin, the mode selection pin, and the clock pin of the configuration interface; and the D poles are respectively connected to three resistors connected in parallel and then connected to the first end of the power supply;

[0016] The G pole of the MOS tube of the output signal configuration circuit is connected to the output pin of the configuration interface, the D pole is connected to the output pin of the main control system, and the D pole is connected to the second end of the power supply through a resistor;

[0017] The S poles of the MOS tubes of the input signal configuration circuit, the output signal configuration circuit, the mode selection signal configuration circuit and the clock signal configuration circuit are grounded.

[0018] Furthermore, the configuration interface is divided into a plurality of interface units, the FPGA chips are divided into groups having the same number as the interface units, and each group of FPGA chips corresponds to one interface unit, wherein:

[0019] The FPGA chips in the same group are connected in series in sequence. The configuration output pin of the previous FPGA chip in the same group is connected to the configuration input pin of the next FPGA chip. The input pin of the interface unit corresponding to the FPGA chips in the same group is connected to the configuration input pin of the first FPGA chip in the group. The output pin of the interface unit corresponding to the FPGA chips in the same group is connected to the configuration output pin of the last FPGA chip in the group.

[0020] The D-pole of the MOS tube of the input signal configuration circuit is connected to the input pin of the first interface unit, the output pin of the previous interface unit is connected to the input pin of the next interface unit, and the output pin of the last interface unit is connected to the G-pole of the MOS tube of the output signal configuration circuit;

[0021] The D poles of the MOS tubes of the mode selection signal configuration circuit and the clock signal configuration circuit are respectively connected in parallel to the mode selection pin and the clock pin of each interface unit.

[0022] Furthermore, the configuration module also includes a configuration status display circuit, and the configuration status display circuit is connected to the main control system.

[0023] Furthermore, the configuration interface is provided on one of the configuration module and the integrated circuit test carrier, and a plug-in structure corresponding to the configuration interface is provided on the other one.

[0024] A configuration module is used for FPGA chip burn-in testing. The configuration module includes a main control system, a power management circuit, a configuration interface circuit, and a configuration interface. The main control system, the configuration interface circuit, and the configuration interface are connected in sequence. The power management circuit is connected to the main control system and the configuration interface circuit and supplies power.

[0025] Furthermore, the power management circuit includes a first power supply end connected to the power pin of the configuration interface, a second power supply end connected to the power pin of the main control system, a MOS transistor Q1, and a MOS transistor Q2. The S pole and D pole of the MOS transistor Q1 are respectively connected to the first power supply end and the second power supply end, the G pole of the MOS transistor Q2 is connected to the upper and lower power control pins of the main control system, the S pole of the MOS transistor Q2 is grounded, and the D pole of the MOS transistor Q2 is connected to the G pole of the MOS transistor Q1.

[0026] Furthermore, the power management circuit further includes a diode D1, wherein the anode of the diode D1 is connected to the upper and lower power control pins, and the cathode is connected to the G terminal of the MOS transistor Q2. The first end of the power supply is connected to the G terminal of the MOS transistor Q2 via a capacitor C1 and a capacitor C2 connected in parallel. The G terminal of the MOS transistor Q2 is connected to a resistor R6 and then grounded.

[0027] The first end of the power supply is connected to the parallel resistors R4 and C3 and then grounded. The second end of the power supply is connected to the parallel resistors R5 and C4 and then grounded. The first end of the power supply is connected to the resistor R3 and then connected to the G terminal of the MOS tube Q1.

[0028] Furthermore, the configuration interface circuit includes an input signal configuration circuit, an output signal configuration circuit, a mode selection signal configuration circuit, and a clock signal configuration circuit; the input pin, mode selection pin, and clock pin of the main control system are connected to the input pin, mode selection pin, and clock pin of the configuration interface through the input signal configuration circuit, the mode selection signal configuration circuit, and the clock signal configuration circuit, respectively; the output pin of the configuration interface is connected to the output pin of the main control system through the output signal configuration circuit;

[0029] The input signal configuration circuit, the output signal configuration circuit, the mode selection signal configuration circuit, and the clock signal configuration circuit each include a respective MOS transistor, wherein the G electrodes of the MOS transistors of the input signal configuration circuit, the mode selection signal configuration circuit, and the clock signal configuration circuit are respectively connected to the input pin, the mode selection pin, and the clock pin of the main control system, and the D electrodes are respectively connected to the input pin, the mode selection pin, and the clock pin of the configuration interface, and the D electrodes are respectively connected to three resistors connected in parallel and then connected to the first end of the power supply;

[0030] The G pole of the MOS tube of the output signal configuration circuit is connected to the output pin of the configuration interface, the D pole is connected to the output pin of the main control system, and the D pole is connected to the second end of the power supply through a resistor;

[0031] The S poles of the MOS tubes of the input signal configuration circuit, the output signal configuration circuit, the mode selection signal configuration circuit and the clock signal configuration circuit are grounded.

[0032] Furthermore, the configuration interface is divided into multiple interface units, the D pole of the MOS tube of the input signal configuration circuit is connected to the input pin of the first interface unit, the output pin of the previous interface unit is connected to the input pin of the next interface unit, and the output pin of the last interface unit is connected to the G pole of the MOS tube of the output signal configuration circuit;

[0033] The D poles of the MOS tubes of the mode selection signal configuration circuit and the clock signal configuration circuit are respectively connected in parallel to the mode selection pin and the clock pin of each interface unit.

[0034] Furthermore, the configuration module also includes a configuration status display circuit, and the configuration status display circuit is connected to the main control system.

[0035] An integrated circuit test carrier board is used for FPGA chip burn-in testing, comprising a plug-in structure and multiple FPGA chips. The multiple FPGA chips are connected in series in sequence, with the configuration output pin of the previous FPGA chip connected to the configuration input pin of the next FPGA chip. The input interface of the plug-in structure is connected to the configuration input pin of the first FPGA chip, and the output interface of the plug-in structure is connected to the configuration output pin of the last FPGA chip.

[0036] Furthermore, the mode selection interface and the clock interface of the plug-in structure are respectively connected in parallel with the mode selection pin and the clock pin of each FPGA chip.

[0037] Furthermore, the integrated circuit test carrier also includes a power module, which is connected to each FPGA chip and supplies power, and the power module is connected to the power interface of the plug-in structure.

[0038] The utility model has the following beneficial effects:

[0039] The utility model inserts the configuration module into the integrated circuit test carrier board, and can realize centralized and automatic configuration of all FPGA chips on the integrated circuit test carrier board. There is no need to configure and plug in each FPGA chip one by one, which greatly reduces manual operation, reduces configuration time and testing costs, and does not affect the firmness of the connection between the chip to be tested and the integrated circuit test carrier board due to frequent plugging and unplugging of the configuration module, thereby reducing the risk of interference during the burn-in test process. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 This is a schematic diagram of the FPGA chip burn-in test system of the present invention;

[0041] Figure 2 This is a schematic diagram of the configuration module;

[0042] Figure 3 is a schematic diagram of the main control system 5;

[0043] Figure 4 is a schematic diagram of a power management circuit;

[0044] Figure 5 A schematic diagram of the configuration interface circuit;

[0045] Figure 6 This is a schematic diagram of the configuration interface;

[0046] Figure 7 A schematic diagram showing the circuit in its configured state. DETAILED DESCRIPTION

[0047] In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0048] The utility model provides a FPGA chip burn-in test system, such as Figure 1-7 As shown, it includes a configuration module 1 and an integrated circuit test carrier 2, and the configuration module 1 and the integrated circuit test carrier 2 are connected in a pluggable manner through a configuration interface 3, wherein:

[0049] The configuration interface 3 includes an input pin T_TDI, an output pin T_TDO, a mode selection pin T_TMS, a clock pin T_TCK, a power pin +Vcc, and a ground pin CND.

[0050] The configuration module 1 includes a main control system 5 (such as a single-chip microcomputer, etc.), a power management circuit 6 and a configuration interface circuit 7. The main control system 5, the configuration interface circuit 7 and the configuration interface 3 are connected in sequence, and the power management circuit 6 is connected to the main control system 5 and the configuration interface circuit 7 and supplies power.

[0051] The integrated circuit test carrier 2 includes multiple FPGA chips 4, which are connected in series in sequence. The configuration output pin of the previous FPGA chip is connected to the configuration input pin of the next FPGA chip, the input pin T_TDI of the configuration interface 3 is connected to the configuration input pin of the first FPGA chip, and the output pin T_TDO of the configuration interface 3 is connected to the configuration output pin of the last FPGA chip.

[0052] In the present invention, the main control system 5 is connected to the integrated circuit test carrier 2 via the configuration interface circuit 7 and the configuration interface 3. The main control system 5 is used to transmit configuration data, configuration instructions, and clock signals to the FPGA chip 4 of the integrated circuit test carrier 2. During configuration, the configuration data is input via the input pin T_TDI of the configuration interface 3 to the configuration input pin of the first FPGA chip for configuration. After the first FPGA chip is configured, its configuration output pin is connected to the configuration input pin of the second FPGA chip, and the second FPGA chip is configured. This process continues until all FPGA chips are configured.

[0053] When the present invention is in use, the configuration module 1 is inserted into the integrated circuit test carrier 2. The main control system 5 sequentially configures the FPGA chip 4 on the integrated circuit test carrier 2 through the configuration interface circuit 7 and the configuration interface 3. During the configuration process, multiple FPGA chips 4 connected in series are configured sequentially until the configuration is complete.

[0054] The utility model inserts the configuration module into the integrated circuit test carrier board, and can realize centralized and automatic configuration of all FPGA chips on the integrated circuit test carrier board. There is no need to configure and plug in each FPGA chip one by one, which greatly reduces manual operation, reduces configuration time and testing costs, and does not affect the firmness of the connection between the chip to be tested and the integrated circuit test carrier board due to frequent plugging and unplugging of the configuration module, thereby reducing the risk of interference during the burn-in test process.

[0055] The mode selection pin T_TMS and clock pin T_TCK of the aforementioned configuration interface are respectively connected in parallel with the mode selection pin and clock pin of each FPGA chip 4, and are used to set the configuration mode and provide the clock for each FPGA chip 4.

[0056] The integrated circuit test carrier board 2 further includes a power module, which is connected to each FPGA chip 4 and supplies power. The power module is connected to the power pin +Vcc of the configuration interface 3 .

[0057] Configuration module 1 does not have a power supply, but instead uses an integrated circuit to test the power supply of the power module of carrier board 2 via configuration interface 3. Power management circuit 6 includes a first power supply terminal 8 (+Vcc) connected to the power supply pin +Vcc of configuration interface 3, a second power supply terminal 9 (+3v3) connected to the power supply pin +3v3 (i.e., the positive 3.3V power supply) of main control system 5, and MOS transistors Q1 and Q2. MOS transistor Q1 is a PMOS transistor, and MOS transistor Q2 is an NMOS transistor.

[0058] Specifically, power supply first terminal 8 is connected to the power module (i.e., +Vcc) of integrated circuit test carrier 2 and converted into a +3V3 power supply by power management circuit 6 to power configuration module 1. MOS transistor Q2 is used to control the on / off switching of MOS transistor Q1, while MOS transistor Q1 is used to control the isolation between power supply first terminal 8 and power supply second terminal 9. When MOS transistor Q1 is turned off, power supply second terminal 9 is powered off, thereby powering down configuration module 1.

[0059] Specifically, the D pole and S pole of the MOS transistor Q1 are connected to the first power supply terminal 8 and the second power supply terminal 9 respectively, the G pole of the MOS transistor Q2 is connected to the power-up and power-down control pin DROP_PWR_N of the main control system 5, the S pole of the MOS transistor Q2 is grounded, and the D pole of the MOS transistor Q2 is connected to the G pole of the MOS transistor Q1.

[0060] The power management circuit 6 also includes a diode D1, the anode of which is connected to the power-on / off control pin DROP_PWR_N, and the cathode of which is connected to the G terminal of the MOS transistor Q2. The first power supply terminal 8 is connected to the G terminal of the MOS transistor Q2 via capacitors C1 and C2 connected in parallel. The G terminal of the MOS transistor Q2 is connected to the resistor R6 and then to ground.

[0061] The first power supply terminal 8 is connected to the parallel resistors R4 and C3 and then grounded. The second power supply terminal 9 is connected to the parallel resistors R5 and C4 and then grounded. The first power supply terminal is connected to the resistor R3 and then connected to the G terminal of the MOS tube Q1.

[0062] When the configuration module 1 is inserted into the integrated circuit test carrier 2, the first power supply terminal 8 is connected to the power module of the integrated circuit test carrier 2, and capacitors C1 and C2 are charged. During the charging process, the main control system 5 is powered on and started. The design of capacitors C1 and C2 should ensure that their charging time (for example, 100ms) meets the startup time of the main control system 5.

[0063] After the main control system 5 is started, the power-on and power-off control pin DROP_PWR_N of the main control system 5 is kept at a high level, that is, the G terminal of the MOS transistor Q2 is at a high level, so that the MOS transistor Q2 is turned on. The turning on of the MOS transistor Q2 makes the G terminal of the MOS transistor Q1 at a low level, so that the MOS transistor Q1 is turned on. The second power supply terminal 9 continuously maintains the +3v3 power supply to continuously power the main control system 5. Therefore, the main control system 5 is continuously powered on during the configuration process.

[0064] After the configuration is completed, the high level of the power-on and power-off control pin DROP_PWR_N of the main control system 5 is removed, and the G electrode level of the MOS transistor Q2 gradually decreases, eventually turning off the MOS transistor Q2. After the MOS transistor Q2 is turned off, the G electrode level of the MOS transistor Q1 is pulled high, and the MOS transistor Q1 is turned off. The second power supply terminal 9 is powered off, and the configuration module 1 is powered off.

[0065] The utility model can realize automatic power on and off. When configuring the chip to be tested, the configuration module supplies power to the configuration module through the integrated circuit test carrier board, so that the configuration module completes self-starting and the chip configuration can be completed. After the chip configuration is completed, the configuration module can automatically power off and the chip to be tested enters the test state.

[0066] Since the burn-in test is conducted at high temperatures, if the configuration module 1 is energized at high temperatures, the life of the circuit components may be shortened. Therefore, the present invention automatically powers off the configuration module 1 after configuration is completed. During the subsequent burn-in test, the configuration module 1 is not energized, thereby extending the life of the circuit components of the configuration module 1.

[0067] The aforementioned configuration interface circuit 7 includes an input signal configuration circuit 10, an output signal configuration circuit 11, a mode selection signal configuration circuit 12 and a clock signal configuration circuit 13. The input pin M_TDI, mode selection pin M_TMS and clock pin M_TCK of the main control system 5 are respectively connected to the input pin T_TDI, mode selection pin T_TMS and clock pin T_TCK of the configuration interface 3 through the input signal configuration circuit 10, the mode selection signal configuration circuit 12 and the clock signal configuration circuit 13. The output pin T_TDO of the configuration interface 3 is connected to the output pin M_TDO of the main control system 5 through the output signal configuration circuit 11.

[0068] Specifically, the input signal configuration circuit 10, the output signal configuration circuit 11, the mode selection signal configuration circuit 12, and the clock signal configuration circuit 13 each include respective MOS transistors Q5, Q6, Q4, and Q3, all of which are NMOS transistors. The G terminals of the MOS transistors Q5, Q4, and Q3 in the input signal configuration circuit 10, the mode selection signal configuration circuit 12, and the clock signal configuration circuit 13 are respectively connected to the input pin M_TDI, the mode selection pin M_TMS, and the clock pin M_TCK of the main control system. The D terminals of Q5, Q4, and Q3 are respectively connected to the input pin T_TDI, the mode selection pin T_TMS, and the clock pin T_TCK of the configuration interface 3. Furthermore, the D terminals of Q5, Q4, and Q3 are each connected to three parallel resistors (R13, R14, and R15 in parallel for Q5, R10, R10, and R10 in parallel for Q4, and R7, R8, and R9 in parallel for Q3), and then connected to the first power supply terminal 8.

[0069] The G terminal of the MOS transistor Q6 of the output signal configuration circuit 11 is connected to the output pin T_TDO of the configuration interface 3, the D terminal of Q6 is connected to the output pin M_TDO of the main control system 5, and the D terminal of Q6 is connected to the second power supply terminal 9 through a resistor R19.

[0070] The S electrodes of the MOS transistors Q5 , Q6 , Q4 and Q3 of the input signal configuration circuit 10 , the output signal configuration circuit 11 , the mode selection signal configuration circuit 12 and the clock signal configuration circuit 13 are grounded.

[0071] To facilitate the configuration of the configuration interface 3, the configuration interface 3 is divided into multiple interface units (for example, J1, J2, and J3). The FPGA chips 4 are divided into groups with the same number of interface units. Each group of FPGA chips corresponds to one interface unit.

[0072] The FPGA chips in the same group are connected in series in sequence. The configuration output pin of the previous FPGA chip in the same group is connected to the configuration input pin of the next FPGA chip. The input pin of the interface unit corresponding to the FPGA chips in the same group is connected to the configuration input pin of the first FPGA chip in the group. The output pin of the interface unit corresponding to the FPGA chips in the same group is connected to the configuration output pin of the last FPGA chip in the group.

[0073] The D-pole of MOS transistor Q5 in input signal configuration circuit 10 is connected to input pin T_TDI of the first interface unit J1. The output pin of the previous interface unit is connected to the input pin of the next interface unit, with a resistor optionally connected in between. For example, output pin T_TDO1 of J1 is connected to input pin T_TDI2 of J2 via resistor R2. Output pin T_TDO2 of J2 is connected to input pin T_TDI3 of J3 via resistor R1. Output pin T_TDO of the last interface unit J3 is connected to the G-pole of MOS transistor Q6 in output signal configuration circuit 11.

[0074] The D terminals of the MOS transistors Q4 and Q3 of the mode selection signal configuration circuit 12 and the clock signal configuration circuit 13 are respectively connected in parallel to the mode selection pin T_TMS and the clock pin T_TCK of each interface unit J1, J2, and J3, providing a mode selection signal and a clock signal to each interface unit J1, J2, and J3.

[0075] The aforementioned configuration module 1 further includes a configuration status display circuit 14 , which is connected to the main control system 5 .

[0076] Exemplarily, the configuration status display circuit 14 includes green and red LEDs D2 and D3. The anodes of D2 and D3 are connected to the second power supply terminal 9, and the cathodes are connected to the D terminals of their respective MOS transistors Q7 and Q8. The G terminals of MOS transistors Q7 and Q8 are connected to the corresponding pins LED_G and LED_R of the main control system 5, respectively. The S terminals of MOS transistors Q7 and Q8 are grounded. One of LEDs D2 and D3 corresponds to the configuration-in-progress state, and the other corresponds to the configuration-completed state. When configuration is in progress or completed, LED_G or LED_R of the main control system 5 sends a signal, and LED D2 or D3 lights up, indicating the configuration status through different colors.

[0077] The aforementioned configuration interface 3 can be provided on one of the configuration module 1 and the integrated circuit test carrier 2, with the other provided with a plug-in structure that mates with the configuration interface 3. The interface layout of the plug-in structure is consistent with the layout of the various pins of the configuration interface 3. For example, the configuration interface 3 is in the form of a socket provided on the configuration module 1, and the integrated circuit test carrier 2 is provided with pins that mate with the socket.

[0078] The present invention also provides a configuration module 1 for FPGA chip burn-in test, such as Figure 2-7 As shown, it includes a main control system 5 (such as a single-chip microcomputer, etc.), a power management circuit 6, a configuration interface circuit 7 and a configuration interface 3. The main control system 5, the configuration interface circuit 7 and the configuration interface 3 are connected in sequence, and the power management circuit 6 is connected to the main control system 5 and the configuration interface circuit 7 and supplies power.

[0079] The power management circuit 6 includes a first power supply terminal 8 (+Vcc) connected to the power supply pin +Vcc of the configuration interface 3, a second power supply terminal 9 (+3v3) connected to the power supply pin +3v3 (i.e., positive 3.3v power supply) of the main control system 5, a MOS transistor Q1 and a MOS transistor Q2, where the MOS transistor Q1 is a PMOS transistor and the MOS transistor Q2 is an NMOS transistor.

[0080] Specifically, power supply first terminal 8 is connected to the power module (i.e., +Vcc) of integrated circuit test carrier 2 and converted into a +3V3 power supply by power management circuit 6 to power configuration module 1. MOS transistor Q2 is used to control the on / off switching of MOS transistor Q1, while MOS transistor Q1 is used to control the isolation between power supply first terminal 8 and power supply second terminal 9. When MOS transistor Q1 is turned off, power supply second terminal 9 is powered off, thereby powering down configuration module 1.

[0081] Specifically, the D pole and S pole of the MOS transistor Q1 are connected to the first power supply terminal 8 and the second power supply terminal 9 respectively, the G pole of the MOS transistor Q2 is connected to the power-up and power-down control pin DROP_PWR_N of the main control system 5, the S pole of the MOS transistor Q2 is grounded, and the D pole of the MOS transistor Q2 is connected to the G pole of the MOS transistor Q1.

[0082] The power management circuit 6 also includes a diode D1, the anode of which is connected to the power-on / off control pin DROP_PWR_N, and the cathode of which is connected to the G terminal of the MOS transistor Q2. The first power supply terminal 8 is connected to the G terminal of the MOS transistor Q2 via capacitors C1 and C2 connected in parallel. The G terminal of the MOS transistor Q2 is connected to the resistor R6 and then to ground.

[0083] The first power supply terminal 8 is connected to the parallel resistors R4 and C3 and then grounded. The second power supply terminal 9 is connected to the parallel resistors R5 and C4 and then grounded. The first power supply terminal is connected to the resistor R3 and then connected to the G terminal of the MOS tube Q1.

[0084] When the configuration module 1 is inserted into the integrated circuit test carrier 2, the first power supply terminal 8 is connected to the power module of the integrated circuit test carrier 2, and capacitors C1 and C2 are charged. During the charging process, the main control system 5 is powered on and started. The design of capacitors C1 and C2 should ensure that their charging time (for example, 100ms) meets the startup time of the main control system 5.

[0085] After the main control system 5 is started, the power-on and power-off control pin DROP_PWR_N of the main control system 5 is kept at a high level, that is, the G terminal of the MOS transistor Q2 is at a high level, so that the MOS transistor Q2 is turned on. The turning on of the MOS transistor Q2 makes the G terminal of the MOS transistor Q1 at a low level, so that the MOS transistor Q1 is turned on. The second power supply terminal 9 continuously maintains the +3v3 power supply to continuously power the main control system 5. Therefore, the main control system 5 is continuously powered on during the configuration process.

[0086] After the configuration is completed, the high level of the power-on and power-off control pin DROP_PWR_N of the main control system 5 is removed, and the G electrode level of the MOS transistor Q2 gradually decreases, eventually turning off the MOS transistor Q2. After the MOS transistor Q2 is turned off, the G electrode level of the MOS transistor Q1 is pulled high, and the MOS transistor Q1 is turned off. The second power supply terminal 9 is powered off, and the configuration module 1 is powered off.

[0087] The utility model can realize automatic power on and off. When configuring the chip to be tested, the configuration module supplies power to the configuration module through the integrated circuit test carrier board, so that the configuration module completes self-starting and the chip configuration can be completed. After the chip configuration is completed, the configuration module can automatically power off and the chip to be tested enters the test state.

[0088] Since the burn-in test is conducted at high temperatures, if the configuration module 1 is energized at high temperatures, the life of the circuit components may be shortened. Therefore, the present invention automatically powers off the configuration module 1 after configuration is completed. During the subsequent burn-in test, the configuration module 1 is not energized, thereby extending the life of the circuit components of the configuration module 1.

[0089] The aforementioned configuration interface circuit 7 includes an input signal configuration circuit 10, an output signal configuration circuit 11, a mode selection signal configuration circuit 12 and a clock signal configuration circuit 13. The input pin M_TDI, mode selection pin M_TMS and clock pin M_TCK of the main control system 5 are respectively connected to the input pin T_TDI, mode selection pin T_TMS and clock pin T_TCK of the configuration interface 3 through the input signal configuration circuit 10, the mode selection signal configuration circuit 12 and the clock signal configuration circuit 13. The output pin T_TDO of the configuration interface 3 is connected to the output pin M_TDO of the main control system 5 through the output signal configuration circuit 11.

[0090] Specifically, the input signal configuration circuit 10, the output signal configuration circuit 11, the mode selection signal configuration circuit 12, and the clock signal configuration circuit 13 each include respective MOS transistors Q5, Q6, Q4, and Q3, all of which are NMOS transistors. The G terminals of the MOS transistors Q5, Q4, and Q3 in the input signal configuration circuit 10, the mode selection signal configuration circuit 12, and the clock signal configuration circuit 13 are respectively connected to the input pin M_TDI, the mode selection pin M_TMS, and the clock pin M_TCK of the main control system. The D terminals of Q5, Q4, and Q3 are respectively connected to the input pin T_TDI, the mode selection pin T_TMS, and the clock pin T_TCK of the configuration interface 3. Furthermore, the D terminals of Q5, Q4, and Q3 are each connected to three parallel resistors (R13, R14, and R15 in parallel for Q5, R10, R10, and R10 in parallel for Q4, and R7, R8, and R9 in parallel for Q3), and then connected to the first power supply terminal 8.

[0091] The G terminal of the MOS transistor Q6 of the output signal configuration circuit 11 is connected to the output pin T_TDO of the configuration interface 3, the D terminal of Q6 is connected to the output pin M_TDO of the main control system 5, and the D terminal of Q6 is connected to the second power supply terminal 9 through a resistor R19.

[0092] The S electrodes of the MOS transistors Q5 , Q6 , Q4 and Q3 of the input signal configuration circuit 10 , the output signal configuration circuit 11 , the mode selection signal configuration circuit 12 and the clock signal configuration circuit 13 are grounded.

[0093] To facilitate the configuration of the configuration interface 3, the configuration interface 3 is divided into multiple interface units (for example, J1, J2, and J3). The FPGA chips 4 are divided into groups with the same number of interface units. Each group of FPGA chips corresponds to one interface unit.

[0094] The FPGA chips in the same group are connected in series in sequence. The configuration output pin of the previous FPGA chip in the same group is connected to the configuration input pin of the next FPGA chip. The input pin of the interface unit corresponding to the FPGA chips in the same group is connected to the configuration input pin of the first FPGA chip in the group. The output pin of the interface unit corresponding to the FPGA chips in the same group is connected to the configuration output pin of the last FPGA chip in the group.

[0095] The D-pole of MOS transistor Q5 in input signal configuration circuit 10 is connected to input pin T_TDI of the first interface unit J1. The output pin of the previous interface unit is connected to the input pin of the next interface unit, with a resistor optionally connected in between. For example, output pin T_TDO1 of J1 is connected to input pin T_TDI2 of J2 via resistor R2. Output pin T_TDO2 of J2 is connected to input pin T_TDI3 of J3 via resistor R1. Output pin T_TDO of the last interface unit J3 is connected to the G-pole of MOS transistor Q6 in output signal configuration circuit 11.

[0096] The D terminals of the MOS transistors Q4 and Q3 of the mode selection signal configuration circuit 12 and the clock signal configuration circuit 13 are respectively connected in parallel to the mode selection pin T_TMS and the clock pin T_TCK of each interface unit J1, J2, and J3, providing a mode selection signal and a clock signal to each interface unit J1, J2, and J3.

[0097] The aforementioned configuration module 1 further includes a configuration status display circuit 14 , which is connected to the main control system 5 .

[0098] Exemplarily, the configuration status display circuit 14 includes green and red LEDs D2 and D3. The anodes of D2 and D3 are connected to the second power supply terminal 9, and the cathodes are connected to the D terminals of their respective MOS transistors Q7 and Q8. The G terminals of MOS transistors Q7 and Q8 are connected to the corresponding pins LED_G and LED_R of the main control system 5, respectively. The S terminals of MOS transistors Q7 and Q8 are grounded. One of LEDs D2 and D3 corresponds to the configuration-in-progress state, and the other corresponds to the configuration-completed state. When configuration is in progress or completed, LED_G or LED_R of the main control system 5 sends a signal, and LED D2 or D3 lights up, indicating the configuration status through different colors.

[0099] The aforementioned configuration interface 3 can be set on one of the configuration module 1 and the integrated circuit test carrier 2, and the other one is provided with a plug-in structure that cooperates with the configuration interface 3. For example, the configuration interface 3 is in the form of a socket and is set on the configuration module 1, and the integrated circuit test carrier 2 is provided with pins that cooperate with the socket.

[0100] The utility model also provides an integrated circuit test carrier 2 for FPGA chip burn-in test, such as Figure 1 As shown, it includes a plug-in structure 3 and multiple FPGA chips 4. The multiple FPGA chips 4 are connected in series in sequence. The configuration output pin of the previous FPGA chip is connected to the configuration input pin of the next FPGA chip. The input interface of the plug-in structure is connected to the configuration input pin of the first FPGA chip, and the output interface of the plug-in structure is connected to the configuration output pin of the last FPGA chip.

[0101] The interface layout of the plug-in structure is consistent with the pin layout of the configuration module. The mode selection interface and clock interface of the plug-in structure are respectively connected in parallel with the mode selection pin and clock pin of each FPGA chip.

[0102] The integrated circuit test carrier board 2 further includes a power module, which is connected to each FPGA chip 4 and supplies power, and is connected to the power interface of the plug-in structure.

[0103] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An FPGA chip burn-in test system, characterized in that: It includes a configuration module and an integrated circuit test carrier, wherein the configuration module and the integrated circuit test carrier are pluggable connected via a configuration interface, wherein: The integrated circuit test carrier includes multiple FPGA chips, which are sequentially connected in series, with the configuration output pin of the previous FPGA chip connected to the configuration input pin of the next FPGA chip, the input pin of the configuration interface connected to the configuration input pin of the first FPGA chip, and the output pin of the configuration interface connected to the configuration output pin of the last FPGA chip; The configuration module includes a main control system, a power management circuit and a configuration interface circuit. The main control system, the configuration interface circuit and the configuration interface are connected in sequence. The power management circuit is connected to the main control system and the configuration interface circuit and supplies power.

2. The FPGA chip burn-in test system according to claim 1, characterized in that: The mode selection pin and the clock pin of the configuration interface are respectively connected in parallel with the mode selection pin and the clock pin of each FPGA chip.

3. The FPGA chip burn-in test system according to claim 2, characterized in that: The integrated circuit test carrier further includes a power module, the power module being connected to each FPGA chip and supplying power, and the power module being connected to a power pin of the configuration interface; The power management circuit includes a first power supply end connected to the power pin of the configuration interface, a second power supply end connected to the power pin of the main control system, a MOS transistor Q1, and a MOS transistor Q2. The S pole and D pole of the MOS transistor Q1 are respectively connected to the first power supply end and the second power supply end. The G pole of the MOS transistor Q2 is connected to the power-up and power-down control pins of the main control system. The S pole of the MOS transistor Q2 is grounded, and the D pole of the MOS transistor Q2 is connected to the G pole of the MOS transistor Q1.

4. The FPGA chip burn-in test system according to claim 3, characterized in that: The power management circuit also includes a diode D1, the anode of which is connected to the upper and lower power control pins, and the cathode of which is connected to the G terminal of the MOS transistor Q2. The first end of the power supply is connected to the G terminal of the MOS transistor Q2 via capacitors C1 and C2 connected in parallel. The G terminal of the MOS transistor Q2 is connected to a resistor R6 and then to ground.

5. The FPGA chip burn-in test system according to claim 4, characterized in that: The first end of the power supply is connected to the parallel resistors R4 and C3 and then grounded. The second end of the power supply is connected to the parallel resistors R5 and C4 and then grounded. The first end of the power supply is connected to the resistor R3 and then connected to the G terminal of the MOS tube Q1.

6. The FPGA chip burn-in test system according to claim 5, characterized in that: The configuration interface circuit includes an input signal configuration circuit, an output signal configuration circuit, a mode selection signal configuration circuit and a clock signal configuration circuit. The input pin, mode selection pin and clock pin of the main control system are connected to the input pin, mode selection pin and clock pin of the configuration interface through the input signal configuration circuit, mode selection signal configuration circuit and clock signal configuration circuit respectively. The output pin of the configuration interface is connected to the output pin of the main control system through the output signal configuration circuit.

7. The FPGA chip burn-in test system according to claim 6, characterized in that: The input signal configuration circuit, the output signal configuration circuit, the mode selection signal configuration circuit, and the clock signal configuration circuit each include a respective MOS transistor, wherein the G electrodes of the MOS transistors of the input signal configuration circuit, the mode selection signal configuration circuit, and the clock signal configuration circuit are respectively connected to the input pin, the mode selection pin, and the clock pin of the main control system, and the D electrodes are respectively connected to the input pin, the mode selection pin, and the clock pin of the configuration interface, and the D electrodes are respectively connected to three resistors connected in parallel and then connected to the first end of the power supply; The G pole of the MOS tube of the output signal configuration circuit is connected to the output pin of the configuration interface, the D pole is connected to the output pin of the main control system, and the D pole is connected to the second end of the power supply through a resistor; The S poles of the MOS tubes of the input signal configuration circuit, the output signal configuration circuit, the mode selection signal configuration circuit and the clock signal configuration circuit are grounded.

8. The FPGA chip burn-in test system according to claim 7, characterized in that: The configuration interface is divided into a plurality of interface units, and the FPGA chips are divided into groups with the same number as the interface units, and each group of FPGA chips corresponds to one interface unit, wherein: The FPGA chips in the same group are connected in series in sequence. The configuration output pin of the previous FPGA chip in the same group is connected to the configuration input pin of the next FPGA chip. The input pin of the interface unit corresponding to the FPGA chips in the same group is connected to the configuration input pin of the first FPGA chip in the group. The output pin of the interface unit corresponding to the FPGA chips in the same group is connected to the configuration output pin of the last FPGA chip in the group. The D-pole of the MOS tube of the input signal configuration circuit is connected to the input pin of the first interface unit, the output pin of the previous interface unit is connected to the input pin of the next interface unit, and the output pin of the last interface unit is connected to the G-pole of the MOS tube of the output signal configuration circuit; The D poles of the MOS tubes of the mode selection signal configuration circuit and the clock signal configuration circuit are respectively connected in parallel to the mode selection pin and the clock pin of each interface unit.

9. The FPGA chip burn-in test system according to any one of claims 1 to 8, characterized in that: The configuration module further includes a configuration status display circuit, and the configuration status display circuit is connected to the main control system.

10. The FPGA chip burn-in test system according to any one of claims 1 to 8, characterized in that: The configuration interface is provided on one of the configuration module and the integrated circuit test carrier, and a plug-in structure corresponding to the configuration interface is provided on the other one.

11. A configuration module for FPGA chip burn-in test, characterized in that: The configuration module includes a main control system, a power management circuit, a configuration interface circuit and a configuration interface. The main control system, the configuration interface circuit and the configuration interface are connected in sequence. The power management circuit is connected to the main control system and the configuration interface circuit and supplies power.

12. The configuration module according to claim 11, characterized in that: The power management circuit includes a first power supply end connected to the power pin of the configuration interface, a second power supply end connected to the power pin of the main control system, a MOS transistor Q1, and a MOS transistor Q2. The S pole and D pole of the MOS transistor Q1 are respectively connected to the first power supply end and the second power supply end. The G pole of the MOS transistor Q2 is connected to the power-up and power-down control pins of the main control system. The S pole of the MOS transistor Q2 is grounded, and the D pole of the MOS transistor Q2 is connected to the G pole of the MOS transistor Q1.

13. The configuration module according to claim 12, characterized in that: The power management circuit further includes a diode D1, wherein the anode of the diode D1 is connected to the upper and lower power control pins, and the cathode is connected to the G terminal of the MOS transistor Q2. The first end of the power supply is connected to the G terminal of the MOS transistor Q2 via a capacitor C1 and a capacitor C2 connected in parallel. The G terminal of the MOS transistor Q2 is connected to a resistor R6 and then to ground. The first end of the power supply is connected to the parallel resistors R4 and C3 and then grounded. The second end of the power supply is connected to the parallel resistors R5 and C4 and then grounded. The first end of the power supply is connected to the resistor R3 and then connected to the G terminal of the MOS tube Q1.

14. The configuration module according to claim 13, characterized in that: The configuration interface circuit includes an input signal configuration circuit, an output signal configuration circuit, a mode selection signal configuration circuit, and a clock signal configuration circuit. The input pin, mode selection pin, and clock pin of the main control system are connected to the input pin, mode selection pin, and clock pin of the configuration interface through the input signal configuration circuit, the mode selection signal configuration circuit, and the clock signal configuration circuit, respectively. The output pin of the configuration interface is connected to the output pin of the main control system through the output signal configuration circuit. The input signal configuration circuit, the output signal configuration circuit, the mode selection signal configuration circuit, and the clock signal configuration circuit each include a respective MOS transistor, wherein the G electrodes of the MOS transistors of the input signal configuration circuit, the mode selection signal configuration circuit, and the clock signal configuration circuit are respectively connected to the input pin, the mode selection pin, and the clock pin of the main control system, and the D electrodes are respectively connected to the input pin, the mode selection pin, and the clock pin of the configuration interface, and the D electrodes are respectively connected to three resistors connected in parallel and then connected to the first end of the power supply; The G pole of the MOS tube of the output signal configuration circuit is connected to the output pin of the configuration interface, the D pole is connected to the output pin of the main control system, and the D pole is connected to the second end of the power supply through a resistor; The S poles of the MOS tubes of the input signal configuration circuit, the output signal configuration circuit, the mode selection signal configuration circuit and the clock signal configuration circuit are grounded.

15. The configuration module according to claim 14, characterized in that: The configuration interface is divided into multiple interface units, the D pole of the MOS tube of the input signal configuration circuit is connected to the input pin of the first interface unit, the output pin of the previous interface unit is connected to the input pin of the next interface unit, and the output pin of the last interface unit is connected to the G pole of the MOS tube of the output signal configuration circuit; The D poles of the MOS tubes of the mode selection signal configuration circuit and the clock signal configuration circuit are respectively connected in parallel to the mode selection pin and the clock pin of each interface unit.

16. The configuration module according to any one of claims 11 to 15, characterized in that: The configuration module further includes a configuration status display circuit, and the configuration status display circuit is connected to the main control system.

17. An integrated circuit test carrier board for FPGA chip burn-in test, characterized in that: It includes a plug-in structure and multiple FPGA chips, which are connected in series in sequence. The configuration output pin of the previous FPGA chip is connected to the configuration input pin of the next FPGA chip. The input interface of the plug-in structure is connected to the configuration input pin of the first FPGA chip, and the output interface of the plug-in structure is connected to the configuration output pin of the last FPGA chip.

18. The integrated circuit test carrier according to claim 17, wherein: The mode selection interface and the clock interface of the plug-in structure are respectively connected in parallel with the mode selection pin and the clock pin of each FPGA chip.

19. The integrated circuit test carrier according to claim 18, wherein: The integrated circuit test carrier also includes a power supply module, which is connected to each FPGA chip and supplies power, and is connected to the power interface of the plug-in structure.

Images