Switch and switching system integrated with IO-Link master station transceiver chip

Abstract

The utility model relates to the technical field of switches, and discloses a switch and a switching system integrated with an IO-Link master station transceiver chip, and the switch comprises the IO-Link master station transceiver chip, a master control chip and a switch chip. The IO-Link master station transceiver chip comprises a first communication port and an IO-Link interface, and the IO-Link interface is connected with an IO-Link device; the main control chip comprises a second communication port and a third communication port, and the main control chip is connected with the first communication port through the second communication port, receives data of the IO-Link equipment and sends an instruction to the IO-Link equipment; the switch chip comprises a fourth communication port, and the main control chip is connected with the fourth communication port through the third communication port, sends data to the switch chip and receives an instruction; and the switch chip is connected with the network equipment through the fifth communication port. According to the invention, the IO-Link master station transceiver chip is integrated into the switch, so that the system integration level of the switch is improved, and the cost is saved.

Description

Technical Field

[0001] The present application relates to the technical field of switches, and in particular to a switch and a switching system integrating an IO-Link master transceiver chip. Background Art

[0002] Existing IO-Link Master transceivers and switches are two separate devices. For example, there are IO-Link Master transceivers with eight ports, and there are also switches with five or eight ports. In practical applications, a 100M switch with five 100M ports is often required, while also requiring the connection of multiple IO-Link Master transceivers. If the system is implemented using a five-port switch and an eight-port IO-Link Master transceiver, the overall system integration cost and installation space will be increased, and the overall system maintenance process will be more cumbersome. Utility Model Content

[0003] In view of this, the embodiments of the present application provide a switch and a switching system with an integrated IO-Link master transceiver chip, which integrates the IO-Link master transceiver chip into a switch with multiple communication ports, thereby significantly reducing the cost of the entire system.

[0004] In a first aspect, an embodiment of the present application provides a switch integrating an IO-Link master transceiver chip, comprising: an IO-Link master transceiver chip, a main control chip, and a switch chip;

[0005] The IO-Link master transceiver chip includes a first communication port and an IO-Link interface, wherein the IO-Link interface is used to connect to an IO-Link device;

[0006] The main control chip includes a second communication port and a third communication port. The main control chip is connected to the first communication port of the IO-Link master transceiver chip through the second communication port, and is used to receive data from each of the IO-Link devices and send instructions generated by the switch chip to each of the IO-Link devices;

[0007] The switch chip includes a fourth communication port, and the main control chip is connected to the fourth communication port of the switch chip through the third communication port, so as to send the data to the switch chip and receive the instructions;

[0008] The switch chip further includes a fifth communication port, and the fifth communication port is used to connect to an external network device.

[0009] In a first possible embodiment of the first aspect, the main control chip has at least one built-in SPI controller, and the SPI controller is used to communicate with the IO-Link master transceiver chip through a serial interface protocol.

[0010] In a second possible embodiment of the first aspect, the main control chip has at least one built-in Ethernet controller, and the Ethernet controller is used to communicate with the switch chip through a network protocol.

[0011] In a third possible embodiment of the first aspect, both the first communication port and the second communication port are SPI ports.

[0012] In a fourth possible embodiment of the first aspect, both the third communication port and the fourth communication port are MAC interfaces configured in MII mode.

[0013] In a fifth possible embodiment of the first aspect, the network protocol is an industrial network protocol based on the CIP protocol.

[0014] In a sixth possible embodiment of the first aspect, there are multiple IO-Link interfaces.

[0015] In a seventh possible embodiment of the first aspect, there are multiple fifth communication ports, and each of the fifth communication ports is a 100M port.

[0016] In an eighth possible embodiment of the first aspect, the IO-Link device is a sensor, a controller, or an actuator.

[0017] In a second aspect, an embodiment of the present application provides a switching system, comprising a plurality of network devices and a switch with the above-mentioned integrated IO-Link master transceiver chip.

[0018] The embodiments of the present application have the following beneficial effects:

[0019] The present embodiment provides a switch with an integrated IO-Link master transceiver chip, comprising: an IO-Link master transceiver chip, a main control chip, and a switch chip; the IO-Link master transceiver chip comprises a first communication port and an IO-Link interface, wherein each IO-Link interface is used to connect to an IO-Link device; the main control chip comprises a second communication port and a third communication port, the main control chip is connected to the first communication port of the IO-Link master transceiver chip via the second communication port, for receiving data collected by each IO-Link device and sending instructions generated by the switch chip to each IO-Link device; the switch chip comprises a fourth communication port, the main control chip is connected to the fourth communication port of the switch chip via the third communication port, for sending data to the switch chip and receiving instructions; the switch chip also comprises a fifth communication port, the fifth communication port being used to connect to an external network device. Based on the above solution, the present application improves the system integration of the switch by integrating the IO-Link master transceiver chip into the switch, thereby saving costs for the overall system, saving installation space, and making installation and maintenance more convenient. At the same time, in terms of after-sales technical support, customers only need to connect with one supplier, reducing communication costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 A schematic diagram of the structure of a switch integrating an IO-Link master transceiver chip according to an embodiment of the present application is shown;

[0022] Figure 2 A schematic diagram of the architecture of a switch integrating an IO-Link master transceiver chip according to an embodiment of the present application is shown;

[0023] Figure 3 A structural diagram of a switching system according to an embodiment of the present application is shown.

[0024] Description of main component symbols:

[0025] 100-Switch; 110-IO-Link master transceiver chip; 120-Master control chip; 130-Switch chip. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0027] The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but rather merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0028] Hereinafter, the terms "including", "having" and their cognates used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the aforementioned items, and should not be understood as excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the aforementioned items or adding the possibility of one or more features, numbers, steps, operations, elements, components or combinations of the aforementioned items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and should not be understood as indicating or implying relative importance.

[0029] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the various embodiments of the present application belong. Terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as in the context of the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present application.

[0030] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0031] The IO-Link master transceiver is a key device connecting IO-Link devices and switch devices. The switch device monitors and controls the status of the IO-Link device by collecting, processing, and transmitting data information from the IO-Link device. It is widely used in the field of switching communication systems, improving the degree of production automation and efficiency. However, existing switching communication systems lack integrated devices that have both the functions of a switch device and an IO-Link master transceiver. Therefore, this application proposes to integrate the IO-Link master transceiver into the switch device based on the structure of the switch device itself, so as to reduce the overall integration cost of the switch device and give full play to the hardware performance of the switch device.

[0032] The switch 100 integrated with the IO-Link master transceiver chip is described below with reference to some specific embodiments.

[0033] Figure 1 A schematic diagram of the structure of a switch 100 with an integrated IO-Link master transceiver chip according to an embodiment of the present application is shown. Exemplarily, the switch 100 with an integrated IO-Link master transceiver chip includes an IO-Link master transceiver chip 110, a main control chip 120, and a switch chip 130, which are connected in sequence. The switch 100 with an integrated IO-Link master transceiver chip is used to implement data transmission, communication control, and parameter configuration with multiple externally connected IO-Link devices. The switch 100 with an integrated IO-Link master transceiver chip is also used to exchange data with other network devices, enabling data exchange and sharing within a local area network.

[0034] like Figure 2 As shown, in the embodiment of the present application, the IO-Link master transceiver chip 110 includes a first communication port and an IO-Link interface, wherein each IO-Link interface is used to connect to an IO-Link device.

[0035] Exemplarily, the IO-Link master transceiver chip 110 is used to provide an IO-Link interface for electrical connection to an IO-Link device. The IO-Link master transceiver chip 110 connects to multiple IO-Link devices through each IO-Link interface. The IO-Link master transceiver chip 110 also communicates with the main control chip 120 via a first communication port. The IO-Link master transceiver chip 110 is also used to receive data from IO-Link devices and transmit the data to the main control chip 120. It can also convert instructions issued by the switch chip 130 into a language recognizable by the IO-Link device and transmit the instructions to the IO-Link device.

[0036] Optionally, the number of IO-Link interfaces can be multiple. IO-Link devices can be sensors, controllers, or actuators. When the IO-Link master transceiver chip 110 has two built-in channels, the hardware performance can be fully utilized. The IO-Link master transceiver chip 110 can simultaneously connect to multiple IO-Link devices. An IO-Link device can be any one or a combination of sensors, controllers, or actuators. The sensor can be a pressure sensor, temperature sensor, accelerometer, or the like.

[0037] Specifically, the IO-Link master transceiver chip 110 is also used to parse and decode the data sent by the IO-Link device, which may include the status, real-time data, and configuration information of various sensors, controllers, and actuators. The IO-Link master transceiver chip 110 is also used to perform on-site error diagnosis and response, monitor the faults or fault events of the IO-Link device, and send the status change message of the IO-Link device according to the fault code of the protocol standard. Among them, the IO-Link device has features such as automatic configuration and rapid fault diagnosis, making it easy to install, configure, and maintain; the IO-Link device also adopts technologies such as digital signal transmission and multi-layer fault detection, and has a high degree of anti-interference and fault tolerance; the IO-Link device also supports real-time data transmission and remote configuration, and can quickly respond to changes in the production line and production needs; the IO-Link device is used to interconnect with the switch chip 130 to achieve comprehensive intelligent and automated control.

[0038] As can be appreciated, the IO-Link master transceiver chip 110 has multiple built-in channels and can connect to a variety of IO-Link devices, making it intelligent, interconnected, and programmable. IO-Link devices require no additional hardware or tools, simply using the IO-Link master transceiver chip 110, making it low-cost, easy to integrate, and widely available.

[0039] Optionally, the IO-Link master transceiver chip 110 can adopt the IO-Link host transceiver model MAX14819. When the IO-Link host transceiver is integrated into the switch 100, combined with software control, the switch 100 can have a frame processing circuit, a frame control program with an asynchronous transceiver and a synchronous transceiver, which can simplify the selection of the microcontroller and simplify the timing-critical control of all variable-length M sequences. The IO-Link host transceiver also has an autonomous cycle timer, which reduces the requirements for high-precision controller timing. This time, the IO-Link host transceiver integrates two low-power sensors and a power controller, with advanced current limiting, reverse current protection and reverse polarity protection capabilities, supporting low-power and reliable solutions. The IO-Link host transceiver uses a 48-pin (7mm×7mm) leadless package and operates in an extended temperature range of -40°C to +125°C.

[0040] like Figure 2 As shown, in an embodiment of the present application, the main control chip 120 includes a second communication port and a third communication port. The main control chip 120 is connected to the first communication port of the IO-Link master transceiver chip 110 through the second communication port. The main control chip 120 is used to receive data from each IO-Link device and send instructions generated by the switch chip 130 to each IO-Link device through the second communication port.

[0041] Exemplarily, the main control chip 120 includes an SPI controller to connect to the first communication interface of the IO-Link master transceiver chip 110 through the second communication port to receive various different data of each IO-Link device and send instructions to each IO-Link device to enable the switch chip 130 to configure and control each IO-Link device to meet application requirements.

[0042] For example, in one embodiment, the main control chip 120 includes at least one SPI controller to communicate with the IO-Link master transceiver chip 110 through a serial interface protocol, wherein the first communication port and the second communication port are both SPI ports (Serial Peripheral Interface).

[0043] Specifically, the SPI controller is a peripheral controller on master chip 120, responsible for managing and controlling data communications with serial peripherals. The SPI controller is used to connect to the IO-Link master transceiver chip 110 via a serial interface protocol. The SPI controller also coordinates data transmission between master chip 120 and various IO-Link devices, enabling master chip 120 to control and manage each IO-Link device. In master chip 120, the SPI controller provides fast data communication and control capabilities, enabling convenient communication with IO-Link devices requiring high-speed performance.

[0044] Exemplarily, when both the first communication port and the second communication port use SPI ports, the SPI port can be used to quickly send data collected by the IO-Link device to the main control chip 120, and to transmit instructions from the switch chip 130 to the IO-Link device, so as to manage and control the IO-Link device.

[0045] Optionally, the main control chip 120 also includes an Ethernet controller to connect to the fourth communication interface of the switch chip 130 through the third communication port to send various different data of each IO-Link device to the switch chip 130, and enable the main control chip 120 to receive instructions generated by the switch chip 130.

[0046] For example, in one embodiment, the main control chip 120 includes at least one Ethernet controller to communicate with the switch chip 130 through a network protocol, and the network protocol is set to an industrial network protocol based on the CIP protocol.

[0047] Specifically, the Ethernet controller is a network controller on the main control chip 120, responsible for Ethernet data transmission and reception. The Ethernet controller can support multiple network protocols, such as Internet Protocol (IP), User Datagram Protocol (UDP), and Hypertext Transfer Protocol (HTTP). It also supports high-speed network data transmission and network management functions such as quality of service. Within the main control chip 120, the Ethernet controller connects the switch chip 130 to the main control chip 120 to facilitate data and command transmission, and enables data sharing and communication between the switch chip 130 and the main control chip 120.

[0048] Exemplarily, the network protocol is an industrial network protocol based on the Common Industrial Protocol (CIP). The Ethernet controller uses this CIP-based industrial network protocol to send instructions generated by the switch chip 130 to the master chip 120. The master chip 120 then transmits the instructions to each IO-Link device, which receives and responds to them. The Ethernet controller also uses this CIP-based industrial network protocol to ensure the stability and reliability of data transmission between the master chip 120 and the switch chip 130.

[0049] Optionally, the main control chip 120 may be a high-performance SOC chip for embedded applications. Specifically, the high-performance SOC chip may support a main frequency of 100 MHz, have a certain amount of built-in memory, and also have multiple Ethernet controllers and multiple SPI controllers.

[0050] like Figure 2 As shown, in an embodiment of the present application, the switch chip 130 includes a fourth communication port, the main control chip 120 is connected to the fourth communication port of the switch chip 130 through the third communication port, and the main control chip 120 sends data and receives instructions to the switch chip 130 through the third communication port.

[0051] Exemplarily, the third communication port and the fourth communication port are both configured in MII (Medium Independent Interface) mode, and the interface modes of the third communication port and the fourth communication port are matched and connected to each other so that the main control chip 120 and the switch chip 130 can communicate with each other. The data collected by the IO-Link device can be transmitted to the switch chip 130 through the main control chip 120, and the control instructions or parameter configuration instructions generated by the switch chip 130 can also be transmitted to the IO-Link device through the main control chip 120.

[0052] For example, in the embodiment of the present application, the third communication port and the fourth communication port are both MAC (Media Access Control) interfaces configured as MII mode.

[0053] Among them, the MII mode is a physical layer interface standard that is independent of the transmission medium and is used to connect the media access control sublayer and the physical layer (PHY). The MAC interface is responsible for the transmission and reception of data frames, and implements Ethernet frame format and error detection functions. The PHY interface is responsible for converting data frames into electrical signals for transmission, as well as receiving electrical signals and converting electrical signals into data frames. It is also responsible for adjusting parameters such as the data transmission rate and bandwidth. In MII mode, the MAC interface and the PHY interface communicate through a bidirectional 16-bit data bus, which can achieve high-speed and reliable data transmission. In MII mode, the MAC interface is responsible for encapsulating data frames into 16-bit data packets and transmitting them to the PHY interface, while the PHY interface is responsible for converting the 16-bit data packets into corresponding electrical signals for transmission through the physical medium. In the switch chip 130, the third communication port and the fourth communication port are configured as MII mode MAC interfaces for connecting the switch chip 130 and the main control chip 120 to realize data transmission and reception, and also support multiple data transmission modes and rates. For example, the data transmission rate can be 10Mbps, 100Mbps and 1000Mbps, etc.

[0054] like Figure 2 As shown, in the embodiment of the present application, there are multiple fifth communication ports, each of which is a 100M port, wherein the fifth communication ports can be interchanged with each other.

[0055] Optionally, the 100M port supports a maximum data transmission rate of 100 Mbps. In switch 100 applications, 100M ports include Fast Ethernet and 100M Ethernet (100BASE-TX). Each 100M port is connected using physical media such as twisted pair cables or optical fiber, and can be used to connect a variety of network devices. Fast Ethernet utilizes the physical layer of twisted-pair Gigabit Ethernet (10BASE-T) and the data link layer of 100M Ethernet (100BASE-TX), supporting a maximum data transmission rate of 100 Mbps. Fast Ethernet utilizes full-duplex transmission mode, enabling simultaneous transmission and reception, effectively improving the communication efficiency of switch 100. 100M Ethernet is a 100M Ethernet standard based on twisted-pair cables, supporting a maximum data transmission rate of 100 Mbps. It utilizes four twisted-pair pairs, two for transmitting data and two for receiving data. 100M Ethernet also supports full-duplex and half-duplex transmission modes, adapting to different network topologies and transmission requirements.

[0056] Optionally, the switch chip 130 may be a switch controller with multiple built-in 10 / 100M ports, integrating multiple MAC ports and a physical layer transceiver for operating twisted pair Ethernet into a single chip.

[0057] It can be understood that the switch 100 with integrated IO-Link master transceiver chip can connect to multiple different IO-Link devices, transmit the data and status information of each IO-Link device to the switch chip 130, and realize monitoring and control of each IO-Link device.

[0058] Figure 3 A schematic diagram of the switching system according to an embodiment of the present application is shown. Exemplarily, the switching system includes multiple network devices and a switch 100 with the aforementioned integrated IO-Link master transceiver chip. The network devices can be any device with a network interface, such as a computer, router, network storage device, network printer, webcam, or Internet phone.

[0059] Specifically, each network device is used to connect to the fifth communication port of the switch 100 through a network interface. The switch 100, as a core device in the local area network, provides a stable and efficient network infrastructure for communication between various network devices by providing functions such as high-speed data exchange, data filtering, flow control and virtual local area network isolation.

[0060] Optionally, the switching system may also include IO-Link devices. IO-Link is a digital communication protocol used to connect various IO-Link devices, such as sensors, controllers, and actuators, and plays an important role in the field of switching communication systems. IO-Link devices can be connected to the switch 100, and communication between the switch 100 and other network devices enables centralized control, monitoring, and diagnosis of IO-Link devices. The switching system can simultaneously support multiple device types and communication protocols, including IO-Link devices and Ethernet devices, thereby achieving efficient integration and management of the switching communication system.

[0061] The above is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the protection scope of the present application.

Claims

1. A switch with an integrated IO-Link master transceiver chip, characterized in that: include: IO-Link master transceiver chip, main control chip and switch chip; The IO-Link master transceiver chip includes a first communication port and an IO-Link interface, wherein the IO-Link interface is used to connect to an IO-Link device; The main control chip includes a second communication port and a third communication port. The main control chip is connected to the first communication port of the IO-Link master transceiver chip through the second communication port, and is used to receive data from each of the IO-Link devices and send instructions generated by the switch chip to each of the IO-Link devices; The switch chip includes a fourth communication port, and the main control chip is connected to the fourth communication port of the switch chip through the third communication port, so as to send the data to the switch chip and receive the instructions; The switch chip further includes a fifth communication port, and the fifth communication port is used to connect to an external network device.

2. The switch with integrated IO-Link master transceiver chip according to claim 1, characterized in that: The main control chip has at least one SPI controller built in, and the SPI controller is used to communicate with the IO-Link master transceiver chip through a serial interface protocol.

3. The switch with integrated IO-Link master transceiver chip according to claim 1, characterized in that: The main control chip has at least one built-in Ethernet controller, and the Ethernet controller is used to communicate with the switch chip through a network protocol.

4. The switch with integrated IO-Link master transceiver chip according to claim 1, characterized in that: The first communication port and the second communication port are both SPI ports.

5. The switch with integrated IO-Link master transceiver chip according to claim 1, characterized in that: The third communication port and the fourth communication port are both MAC interfaces configured as MII mode.

6. The switch integrated with the IO-Link master transceiver chip according to claim 3, characterized in that: The network protocol is an industrial network protocol based on the CIP protocol.

7. The switch integrated with the IO-Link master transceiver chip according to claim 1, characterized in that: There are multiple IO-Link interfaces.

8. The switch with integrated IO-Link master transceiver chip according to claim 1, characterized in that: There are multiple fifth communication ports, and each of the fifth communication ports is a 100M port.

9. The switch integrated with the IO-Link master transceiver chip according to claim 1, characterized in that: The IO-Link device is a sensor, a controller or an actuator.

10. A switching system, characterized in that: A switch comprising a plurality of network devices and an integrated IO-Link master transceiver chip according to any one of claims 1 to 9.

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